Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
  • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Definitions

• Fig. 1 is a block diagram of a prior art memory system.
• the system of Fig. 1 includes three memory modules 10, 12, and 14 that are coupled to a memory controller 16 through a bus 18.
• Each memory module is fabricated on a circuit board that plugs into a connector 20 on a mother board 22.
• Each module includes multiple memory devices 24, 26, and 28 that are coupled to the bus 18 to allow the memory controller to access the memory devices .
• each data line in the bus 18 has a total capacitance that equals the sum of the capacitance of each portion of the signal line running through sections A, B, and C of the bus, plus the capacitance of the portion of the data line in sections 30, 32, and 34 that couple the memory devices to the bus, plus the sum of the input capacitance of all of the memory devices (which are attached to sections 30, 32, and 34 in parallel).
• FIG. 1 is a block diagram of a prior art memory system.
• Fig. 2 is a block diagram of an embodiment of a memory module in accordance " with the present invention.
• Fig. 3 is a side view showing the mechanical arrangement of an embodiment of a memory module in accordance with the present invention.
• Fig. 4 is a block diagram of an embodiment of a memory system in accordance with the present invention.
• FIG. 2 is a block diagram of an embodiment of a memory module 100 in accordance with the present invention.
• Module 100 includes a first memory device 104 which is mounted on a circuit board 108.
• a second memory device 106 is stacked on top of the first memory device to form a stack 102.
• a buffer 110 is mounted on the circuit board and electrically coupled to the memory devices 104 and 106 through signal lines 112.
• a connector 114 is attached to the circuit board for coupling the memory module to a bus that leads to a memory controller on another circuit board, e.g., a computer mother board.
• the buffer 110 is arranged to capacitively isolate the stack of memory devices from the bus. Therefore, the capacitive loading seen by a memory controller (or other device) driving the bus is reduced. This increases the maximum operating speed of the memory module and reduces power consumption.
• the buffer 110 sends and receives signals to and from the memory controller through connector 114 over signal lines 120.
• the buffer 110 is designed to receive signals from the memory controller over a first bus and redrive them back out the connector over signal lines 122 (shown in broken lines) and to a second memory module over a second bus.
• Fig. 3 is a side view showing the mechanical arrangement of an embodiment of a memory module in accordance with the present invention.
• the stack 102 can be extended to include additional memory devices (shown in broken lines). Additional stacks can also be added, and they can be buffered by the first buffer 110, or a separate buffer can be used for each stack.
• Fig. 4 is a block diagram of an embodiment of a memory system in accordance with the present invention.
• the system of Fig. 4 includes two modules 100A and 100B coupled to a memory controller 116 on a computer mother board 117 through a bus system 118 which includes buses 118 A and 118B.
• the modules may be coupled through connectors 130A and 130B which plug into connectors 132A and 132B, respectively, on the mother board.
• Each module a stack of memory devices 102A,102B and a buffer 110A, 110B that isolates the corresponding stack from the bus system.
• the modules are coupled to the memory controller in a point-to-point arrangement.
• the memory controller 116 is coupled to module 100A, which is designed to receive signals from the memory controller and redrive them to module 100B.
• module 100A which is designed to receive signals from the memory controller and redrive them to module 100B.
• the use of point-to-point wiring further reduces the capacitive loading seen by the memory controller.
• the modules 110A and HOB and memory controller 116 may be coupled together in a multi-drop arrangement in which both of the modules are essentially coupled in parallel on a single bus.
• the memory controller 116 is shown in Fig. 4 as part of a central processing unit (CPU) 126, however, it may alternatively be implemented as one chip of a chipset, or in any other suitable form.
• the memory system shown in Fig. 4 includes two memory modules for purposes of illustration, but may be implemented with only a single memory module or with any number of modules.
• the buffers need not be mounted on the memory modules, but can also be mounted on the mother board or any other device on which the bus system resides.
• the stacks of memory devices need not be mounted on modules. Instead, an entire memory system in accordance with the present invention may be fabricated on a single circuit board including the memory controller, bus, stacks of memory devices, and buffers arranged to capacitively isolate the stacks from the bus.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Dram (AREA)

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• 2001
  • 2001-09-13 TW TW090122785A patent/TW528948B/zh not_active IP Right Cessation
  • 2001-09-14 WO PCT/US2001/028627 patent/WO2002025454A2/en not_active Ceased
  • 2001-09-14 KR KR1020037003689A patent/KR100554081B1/ko not_active Expired - Fee Related
  • 2001-09-14 AU AU2001289067A patent/AU2001289067A1/en not_active Abandoned
  • 2001-09-14 CN CNA018156630A patent/CN1484833A/zh active Pending
  • 2001-09-14 EP EP01968854A patent/EP1320804A2/de not_active Withdrawn

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