AU2001289067A1 - Memory module having buffer for isolating stacked memory devices - Google Patents

Memory module having buffer for isolating stacked memory devices

Info

Publication number
AU2001289067A1
AU2001289067A1 AU2001289067A AU8906701A AU2001289067A1 AU 2001289067 A1 AU2001289067 A1 AU 2001289067A1 AU 2001289067 A AU2001289067 A AU 2001289067A AU 8906701 A AU8906701 A AU 8906701A AU 2001289067 A1 AU2001289067 A1 AU 2001289067A1
Authority
AU
Australia
Prior art keywords
buffer
memory devices
memory module
isolating
isolating stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001289067A
Inventor
Randy M Bonella
John Halbert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/666,528 external-priority patent/US6487102B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001289067A1 publication Critical patent/AU2001289067A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
AU2001289067A 2000-09-14 2001-09-14 Memory module having buffer for isolating stacked memory devices Abandoned AU2001289067A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23259600P 2000-09-14 2000-09-14
US60/232,596 2000-09-14
US09/666,528 2000-09-18
US09/666,528 US6487102B1 (en) 2000-09-18 2000-09-18 Memory module having buffer for isolating stacked memory devices
PCT/US2001/028627 WO2002025454A2 (en) 2000-09-14 2001-09-14 Memory module having buffer for isolating stacked memory devices

Publications (1)

Publication Number Publication Date
AU2001289067A1 true AU2001289067A1 (en) 2002-04-02

Family

ID=26926151

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001289067A Abandoned AU2001289067A1 (en) 2000-09-14 2001-09-14 Memory module having buffer for isolating stacked memory devices

Country Status (6)

Country Link
EP (1) EP1320804A2 (en)
KR (1) KR100554081B1 (en)
CN (1) CN1484833A (en)
AU (1) AU2001289067A1 (en)
TW (1) TW528948B (en)
WO (1) WO2002025454A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6745268B1 (en) 2000-08-11 2004-06-01 Micron Technology, Lnc. Capacitive multidrop bus compensation
US20050289316A1 (en) * 2004-06-24 2005-12-29 David Durham Mechanism for sequestering memory for a bus device
KR100763352B1 (en) * 2005-05-10 2007-10-04 삼성전자주식회사 Memory systems, modules, controllers and methods using dedicated data and control busses
US7577760B2 (en) 2005-05-10 2009-08-18 Samsung Electronics Co., Ltd. Memory systems, modules, controllers and methods using dedicated data and control busses
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US8516185B2 (en) * 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8582373B2 (en) 2010-08-31 2013-11-12 Micron Technology, Inc. Buffer die in stacks of memory dies and methods
KR20180004562A (en) * 2016-07-04 2018-01-12 에스프린팅솔루션 주식회사 Electronic apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970003915B1 (en) * 1987-06-24 1997-03-22 미다 가쓰시게 Semiconductor device and the use memory module
US5270964A (en) * 1992-05-19 1993-12-14 Sun Microsystems, Inc. Single in-line memory module
IN188196B (en) * 1995-05-15 2002-08-31 Silicon Graphics Inc
WO1999030240A1 (en) * 1997-12-05 1999-06-17 Intel Corporation Memory system including a memory module having a memory module controller

Also Published As

Publication number Publication date
KR20030048036A (en) 2003-06-18
KR100554081B1 (en) 2006-02-22
TW528948B (en) 2003-04-21
EP1320804A2 (en) 2003-06-25
WO2002025454A3 (en) 2002-08-22
WO2002025454A2 (en) 2002-03-28
CN1484833A (en) 2004-03-24

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