EP1299876A1 - Method and device for controlling a matrix electron source, with regulation by the emitted charge - Google Patents

Method and device for controlling a matrix electron source, with regulation by the emitted charge

Info

Publication number
EP1299876A1
EP1299876A1 EP01954091A EP01954091A EP1299876A1 EP 1299876 A1 EP1299876 A1 EP 1299876A1 EP 01954091 A EP01954091 A EP 01954091A EP 01954091 A EP01954091 A EP 01954091A EP 1299876 A1 EP1299876 A1 EP 1299876A1
Authority
EP
European Patent Office
Prior art keywords
column
emission
columns
potential
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP01954091A
Other languages
German (de)
French (fr)
Other versions
EP1299876B1 (en
Inventor
Pierre Nicolas
Denis Sarrasin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1299876A1 publication Critical patent/EP1299876A1/en
Application granted granted Critical
Publication of EP1299876B1 publication Critical patent/EP1299876B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/027Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0275Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0209Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • G09G3/2014Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention relates to a method and a device for controlling an electron source with a matrix structure.
  • Hot cathodes, photoemissive cathodes and microdots with field effect microdots are known for example (see document [1] which, like the other documents cited below, is mentioned at the end of this description), nanofissures with field effect (see document [2]) flat electron sources of the graphite or carbon diamond type (see document [3]) and devices called LEDs.
  • Such electron sources find applications mainly in the field of visualization with flat screens but also in other fields, for example physical instrumentation, lasers and X-ray emission sources (see the document [4]).
  • Examples of the invention which will be given in the following are limited to the field of visualization, which is the largest (it includes flat screens).
  • FIG. 1 schematically illustrates the operating principle of a display screen which uses a field emission electron source 2.
  • the screen of FIG. 1 also includes an anode 4 comprising an anode conductor 6.
  • the cathode which constitutes the electron source 2 is generally voltage-controlled. Under the influence of this voltage, it emits a flow of electrons 8.
  • a microtip screen which is schematically and partially shown in perspective in FIG. 2.
  • This screen comprises a cathode comprising a substrate 10, provided with cathode conductors 12 on which microtips 14 are formed, and grids 16 formed above the cathode conductors and provided with holes 18 opposite the microtips.
  • the screen also includes an anode comprising a substrate 20 and an anode conductor 22 which is located opposite the grids 16. Let us return to FIG. 1. We see the voltage source 24 making it possible to apply the high voltage V a to the anode conductor 6.
  • polarization means 26 intended to apply the voltage V g to the gate of the electron source 2 and the voltage V c to the cathode of this source.
  • V gc the control voltage which is equal to V g -V c .
  • Cathode characteristics are shown in Figure 3 (curves I and II).
  • V tll the threshold voltage.
  • the curve I corresponds to a cathode current lo while the curve II corresponds to a current Io- ⁇ l. '
  • the electrons emitted by the electron source are accelerated and collected by the anode subjected to the high voltage V a . If a layer of phosphor material (in English "phosphor") 28 is deposited on the anode conductor 6 then the kinetic energy of the electrons is converted into light.
  • FIG. 1 It is possible to obtain a display screen by organizing the basic structure of FIG. 1 in the form of a matrix structure. The latter must allow the addressing of each pixel of the screen and therefore the control of the luminance of the pixel considered (see document [5]).
  • a screen with a matrix structure using an electron source with a matrix structure 30 is schematically represented in FIG. 4.
  • Each pixel of the electron source 30 is defined by the intersection of a line electrode and a storage electrode. column from this source.
  • L x , L 2 ... Lj . ... L n the line electrodes of this source and the column electrodes of the source are denoted C x ,
  • the screen in Figure 4 includes a line scan generator 34. This generator is provided with a source 36 of voltage V ⁇ ns and a source 38 of voltage V ⁇ s . We denote by V xi the control voltage of the line Lj . . The screen also includes means 40 for generating the column control voltages. V Cj denotes the control voltage of column C j .
  • a control circuit is assigned to each line and to each column of the screen and addressing is carried out one line at a time for a time t ⁇ ig .
  • the rows are therefore brought sequentially to a potential V ls called row selection potential while the columns are brought to a potential corresponding to the information to be displayed.
  • V ls a potential corresponding to the information to be displayed.
  • the non-selected lines are brought to a potential V ⁇ ns such that the voltages present on the columns do not affect the display on these lines.
  • it is possible to act on the value of the control voltages Vij . - Cj or over their duration co this duration must remain less than or equal to t lig .
  • control methods are possible. We know for example the control method using electrical charges, more simply called “charge control method” (see document [6]). There is also known a control method using a current, more simply called “current control method” (see document [7]).
  • a current command may seem to solve this problem because we are then required to inject a current and therefore a determined quantity of electrons. Such a principle is effectively valid under static conditions.
  • a column electrode is similar to a capacitor with respect to the lines that this column crosses and the current necessary for the rapid charging of this capacitor proves to be greater, by several orders of magnitude, than the emission current.
  • the capacity of a column relative to the lines C co ⁇ is approximately 400 pF. If we want to "turn on”, that is to say excite a pixel, we pass the current of this pixel from an almost zero value to a value of about 10 ⁇ A and, to do this, we increases the line-column voltage by approximately 40 V. If the switching must be done in 1 ⁇ s (time which is to be compared to a line time of 60 ⁇ s), the capacitive current amounts to:
  • FIG. 5 schematically illustrates a display screen comprising an electron source with a matrix structure using a charge command.
  • the known screen of FIG. 5 differs from that of FIG. 4 only by the means for applying the control voltages to the columns of the source of the screen.
  • the means 42 for applying a control voltage to a column for example column C j , comprise a logic block 44, which receives as input a line sync signal El, and a comparator 46, which receives as input a value setpoint A1 and which is connected to logic block 44 as seen in FIG. 5.
  • the voltage application means 42 also include a three-state output stage 48 which is also connected to logic block 44 and receives voltages respectively denoted V c _ on and V c _ of f by unrepresented voltage sources.
  • the three-state output stage and the comparator are connected to the corresponding column of the electron source (Cj in the example considered)
  • the column conductor considered is preloaded to ensure the emission of the sources (V c _ on ). Then the circuit is opened to let the column capacitor discharge on its internal impedance, until the floating potential V C j reaches the set value Al corresponding to the quantity of electrons desired. The column is then brought back to the extinction potential (V c -. Off ).
  • V c -. Off the extinction potential
  • I f If (ls) + 1f (lns) (V ⁇ s -V cj (t)) / R lc + (n-1). (V lns -V cj (t)) / R lc
  • I f Leakage current of a column with respect to all rows
  • I f ( i s ) Leakage current of a column with respect to the selected row
  • I f (i ns ) Leakage current of a column compared to the lines not selected
  • V ⁇ s Potential applied to the selected line
  • V ⁇ ns Potential applied to the lines not selected
  • v Cj (t) Floating potential of column j during transmission time
  • n Number of lines.
  • V lns OV and, knowing that V c j (t) is much less than V ⁇ s , we then have:
  • the object of the present invention is to remedy the various preceding drawbacks. It relates to a method for controlling a source of electrons with a matrix structure, this source comprising at least one line and at least one addressing column, the intersection of which defines one or more emissive zones called pixels and where the electrons are supplied by the column, this process being a sequential process characterized in that:
  • the emission of electrons is triggered by application of potentials on the selected line and the column (s) with a vapor capable of allowing this emission, then the potential of the column (s) is maintained at this value throughout the duration of the emission while, simultaneously, the measurement of the quantity of charges emitted by the pixel or pixels respectively of said column or columns is ensured in the column or columns, and
  • the value capable of allowing transmission is equal to the potential of the unaddressed line or lines.
  • the invention also relates to a device for controlling a source of electrons with a matrix structure, this source comprising at least one line and at least one column of a-dressage, each intersection of which defines an area called a pixel and where the electrons are supplied by the column, this device being characterized in that it comprises:
  • the quantity of charge already emitted is converted into a voltage level.
  • the device which is the subject of the invention may further comprise means for compensating for residual leakage currents. This device can also include means for compensating intercolumn capacitive couplings.
  • FIG. 1 schematically illustrates the operating principle of a display screen using a field emission device and has already been described
  • FIG. 2 schematically illustrates the structure of a microtip screen and has already been described
  • FIG. 4 schematically illustrates a display screen using a device for transmitting field with a matrix structure and has already been described
  • Figure 5 is a schematic view of a known device for controlling an electron source with a matrix structure and has already been described
  • »Figure 6 is a schematic view d '' a particular embodiment of the device object of
  • Figure 7 illustrates schematically an example of a column control device in a device according to the invention
  • Figure 8 is a timing diagram of various voltages used in the device of Figure 7, has the FIG. 9 schematically illustrates a variant of FIG. 7,
  • FIG. 10 schematically illustrates an example of a device for controlling a column with compensation for the leakage current, in a device according to the invention
  • FIG. 11 schematically illustrates an exemplary embodiment of a device for controlling a column with filtering by diodes of the parasitic loads due to the inter-column capacities, in accordance with the invention
  • FIG. 12 diagrammatically illustrates an exemplary embodiment of a device for controlling a column with filtering by parasitic loads due to the inter-column capacities, in accordance with the invention
  • FIG. 13 schematically illustrates an exemplary embodiment of a device for controlling a column with analog compensation for parasitic loads due to the inter-column capacities, in accordance with the invention.
  • the present invention provides a control circuit which operates under these conditions.
  • FIG. 6 the reference 50 represents the means for controlling a column of the screen (Cj).
  • These control means 50 comprise, as can be seen, a control logic 52, a comparator 54, a current integrator with control of V co ⁇ and an output stage 58.
  • V cj - on (t) and V c _ or ⁇ are both equal to the same constant value.
  • V c _ on equal to V ⁇ ns .
  • the invention therefore relates to a sequential control process for an electron source which allows':
  • This control device 60 comprises an output stage 62 of the push-pull type, a current integrator assembly 64 and a comparator 66.
  • the output stage 62 makes it possible to switch, on the column electrode (C j ), either the supply voltage V c _ 0 f f corresponding to the pixel extinction level or the input- of the integrator circuit 64 which imposes by its virtual mass the level V c _ 0n (putting it at the potential of the lines not selected).
  • the output stage 62 comprises in known manner means 68 of logic level translation and two MOSFET transistors 70 and 72, the transistor 70 being of type P and the transistor 72 of type N, these means 68 and these transistors being arranged as seen in Figure 7.
  • the integrator assembly 64 comprises an amplifier 74 which is looped over a capacitor 76 of capacity Ci nt which is itself mounted in parallel with a controlled switch SW1, the output A2 of this amplifier being connected to the input (-) of the comparator 66.
  • the controlled switch enables the potential A2 to be brought to zero at the start of each line.
  • the comparator input (+) is connected to a reference voltage Al corresponding to the quantity of charges to be emitted.
  • this voltage setpoint can be provided by various means which depend on the desired application of the invention.
  • a digital analog converter CDA is used which receives as input a digital datum DN of setpoint voltage and whose output provides the setpoint potential Al.
  • the output S2 of the comparator assembly constitutes the control of the push-pull output stage thus allowing the device to be looped.
  • FIG. 8 represents the time diagram of the different voltages within the device, during a line addressing cycle.
  • the cycle starts at time t 0 , by the signal start signal SI (see figure 8 part B) triggering the rise of S2 (see figure 8 part C) which, by output stage, changes column V c j to V c - on (virtual mass).
  • V Li goes from its potential V ⁇ n ⁇ (defined as the mass of the assembly) to the selection potential V ⁇ s , the set Ul and C int then loads into A2 (see Figure 8 part D ) , according to the law :
  • the device described makes it possible to deliver to the pixel considered a charge controlled by the setpoint supplied A1, " and this without variation of the voltage applied to the column, during the transmission time.
  • V L ⁇ increases before t on , the emission current is established before the start of integration (and the corresponding charges are therefore not measured). If V L i rises during or after the start of integration (t on ), the charges corresponding to the capacitive pixel current are measured and result in an initial voltage offset on A2. A slight difference in phase, between the rise of V Li and the falling edge of Si, can therefore be adjusted to adopt the best compromise according to the application.
  • this level can be managed directly by the control unit while keeping the signal SI in the corresponding column low.
  • FIG. 9 Another embodiment of a column control device according to the invention is shown diagrammatically in FIG. 9. It is a variant of FIG. 7.
  • the previous system converts the quantity of charge already emitted into a voltage level, which makes it possible to switch the piloting of the column control stage at time 0 f when the quantity of charge ( Q re f) the setpoint is reached.
  • the CCT converter comprises the amplifier 74 already used in the example of FIG. 7 but associated, in the case of FIG. 9, at a resistor R mounted between the input (-) and the output of the amplifier 74.
  • the CCN circuit receives digital or analog data from appropriate DNA means.
  • a compensation current of sign opposite to I fU i te i it suffices to connect a current source to the measurement input of the integrator (see figures 6 and 7).
  • This may for example consist of a transistor mounted as a current generator or of a resistance R Comp controlled by an adjustable voltage generator GT, as seen in FIG. 10.
  • Figure 11 presents an example of diode filtering parasitic loads due to the inter-column capacities. This solution is an asynchronous solution, which is based on fast switching diodes, responding much faster than the integrator. In other words, we play on the fact that the variations of the capacitive currents are rapid compared to those of the emission current, practically zero variations in steady state during the line time. In the same state of mind, we could try to implement analog or logic filters, filters used to discriminate the emission currents from the parasitic capacitive currents.
  • two filter diodes DF1 and DF2 are used to filter the parasitic loads due to the inter-column capacities.
  • FIG. 12 provides another exemplary embodiment of a device for controlling a column with filtering, this time by transistors, parasitic loads due to the inter-column capacities.
  • This solution is of the synchronous type.
  • the comparator output is this time revalidated by logic to supply S2 at specific times.
  • the switching times of the columns from V c _ on to V c _ of ⁇ are now fixed. It is therefore possible, synchronously, to prevent the capacitive currents associated with this consumption from being integrated into the measurement of loads.
  • FIG. 13 shows an exemplary embodiment of a device for controlling a column with analog compensation for parasitic loads due to the inter-column capacities of the neighboring columns.
  • the adder has the reference ADD.
  • the switching signals of columns j-1 and j + 1 have the references S2 j _ ⁇ and S2j + ⁇ respectively.
  • the control method proposed in this invention consists in summary of a command at constant column voltage, of the Pulse Width Modulation (PWM) type, width controlled by the load emitted.
  • PWM Pulse Width Modulation
  • Such a column control circuit provides various advantages: - a limitation of the leakage currents of the columns, to those of the single row addressed, which, for the same screen, makes it possible to obtain a better image quality in terms of uniformity,
  • this command mode maintains a constant column voltage during transmission, which makes it possible to stay at the maximum of the emission of the pixel considered, and therefore for a given line time , maximum shine,
  • the proposed control circuit is "independent" of the technological and dimensional characteristics of the screen - the control circuit fully decouples, with regard to the voltages, the functions for measuring the charge emitted (integrator plus comparator), from those of the output stage.
  • the functions for measuring the charge emitted integrated plus comparator
  • Load control circuits for operating electron sources are known from documents WO 96 05589 and US 6020804. These circuits make it possible to apply voltages to the rows and columns of a matrix source in order to allow the 'emission of electrons and measure the quantity of charge emitted to compare it with a set value.
  • the measurement of the load is generally made on a resistor and causes a voltage variation of the order of IV taking into account the other quantities involved.
  • This measurement voltage comes disturb the supply circuit: in the prior art, the variation of 1 volt with respect to the applied kV causes a negligible error. In the invention, the error would become very large (one volt relative to a few tens of volts) and absolutely unacceptable.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

Process and device for control of an electron source with matrix structure, regulated by the emitted charge. The invention is applicable to an electron source comprising addressing rows and columns which intersect to define emission areas, the electrons being supplied by the columns. According to this invention, the emission of electrons is triggered by increasing the potential of the columns to a value that will enable preferential emission of unaddressed rows. Then, throughout the emission duration, the potential of columns will be kept equal to this value, while simultaneously making measurements in the columns of the quantity of charges emitted by the pixels in the said columns. Secondly, when the quantity of charges measured on a column reaches a required charge quantity, the potential of this column is switched to a value that will block the emission of electrons. The invention is particularly applicable to flat field emission displays.

Description

PROCÉDÉ ET DISPOSITIF DE COMMANDE D'UNE SOURCE D'ÉLECTRONS À STRUCTURE MATRICIELLE, AVEC RÉGULATION METHOD AND DEVICE FOR CONTROLLING A MATRIX-STRUCTURED ELECTRON SOURCE WITH REGULATION
PAR LA CHARGE ÉMISEBY THE LOAD ISSUED
DESCRIPTIONDESCRIPTION
DOMAINE TECHNIQUETECHNICAL AREA
La présente invention concerne un procédé et un dispositif de commande d'une source d'électrons à structure matricielle.The present invention relates to a method and a device for controlling an electron source with a matrix structure.
On connaît diverses sources d'électrons ou dispositifs émetteurs d'électrons. Ces dispositifs connus reposent sur des principes physiques qui peuvent être très différents les uns des autres.Various sources of electrons or electron emitting devices are known. These known devices are based on physical principles which can be very different from each other.
On connaît par exemple les cathodes chaudes, les cathodes photoémissives et les cathodes à micropointes à effet de champ (voir le document [1] qui, comme les autres documents cités par la suite, est mentionné à la fin de la présente description) , les dispositifs à nanofissures à effet de champ (voir le document [2]) les sources planes d'électrons du type graphite ou carbone diamant (voir le document [3]) et les dispositifs appelés LED.Hot cathodes, photoemissive cathodes and microdots with field effect microdots are known for example (see document [1] which, like the other documents cited below, is mentioned at the end of this description), nanofissures with field effect (see document [2]) flat electron sources of the graphite or carbon diamond type (see document [3]) and devices called LEDs.
De telles sources d'électrons trouvent des applications principalement dans le domaine de la visualisation avec les écrans plats mais aussi dans d'autres domaines, par exemple l'instrumentation physique, les lasers et les sources d'émission de rayon X (voir le document [4]). Les exemples de l'invention qui seront donnés dans la suite sont limités au domaine de la visualisation, domaine qui est le plus vaste (il comprend les écrans plats) .Such electron sources find applications mainly in the field of visualization with flat screens but also in other fields, for example physical instrumentation, lasers and X-ray emission sources (see the document [4]). Examples of the invention which will be given in the following are limited to the field of visualization, which is the largest (it includes flat screens).
Cependant, la présente invention n'est pas limitée à ce domaine et s'applique à tout dispositif utilisant une ou des sources d'électrons (et incluant le cas d'une matrice 1 ligne x 1 colonne) c'est le cas par exemple d'un écran monopixel en fonctionnement puisé . La figure 1 illustre schematiquement le principe de fonctionnement d'un écran de visualisation qui utilise une source d'électrons à émission de champ 2.However, the present invention is not limited to this field and applies to any device using one or more sources of electrons (and including the case of a 1 row x 1 column matrix) this is the case for example of a monopixel screen in pulsed operation. FIG. 1 schematically illustrates the operating principle of a display screen which uses a field emission electron source 2.
L'écran de la figure 1 comprend aussi une anode 4 comprenant un conducteur d'anode 6.The screen of FIG. 1 also includes an anode 4 comprising an anode conductor 6.
La cathode, qui constitue la source d'électrons 2 est généralement commandée en tension. Sous l'influence de cette tension, elle émet un flux d'électrons 8. Considérons le cas particulier d'un écran à micropointes qui est schematiquement et partiellement représenté en perspective sur la figure 2. Cet écran comprend une cathode comprenant un substrat 10, muni de conducteurs cathodiques 12 sur lesquels sont formées des micropointes 14, et des grilles 16 formées au- dessus des conducteurs cathodiques et pourvues de trous 18 en regard des micropointes. L'écran comprend aussi une anode comprenant un substrat 20 et un conducteur d'anode 22 qui se trouve en regard des grilles 16. Revenons à la figure 1. On voit la source de tension 24 permettant d'appliquer la haute tension Va au conducteur d'anode 6. On voit aussi des moyens 26 de polarisation destinés à appliquer la tension Vg à la grille de la source d'électrons 2 et la tension Vc à la cathode de cette source. On note Vgc la tension de commande qui est égale à Vg-Vc. Des caractéristiques de cathode sont représentées sur la figure 3 (courbes I et II) . On note Vtll la tension de seuil. Pour une tension de commande Vo supérieure à Vth, la courbe I correspond à un courant de cathode lo tandis que la courbe II correspond à un courant Io-Δl . ' The cathode, which constitutes the electron source 2, is generally voltage-controlled. Under the influence of this voltage, it emits a flow of electrons 8. Let us consider the particular case of a microtip screen which is schematically and partially shown in perspective in FIG. 2. This screen comprises a cathode comprising a substrate 10, provided with cathode conductors 12 on which microtips 14 are formed, and grids 16 formed above the cathode conductors and provided with holes 18 opposite the microtips. The screen also includes an anode comprising a substrate 20 and an anode conductor 22 which is located opposite the grids 16. Let us return to FIG. 1. We see the voltage source 24 making it possible to apply the high voltage V a to the anode conductor 6. We also see polarization means 26 intended to apply the voltage V g to the gate of the electron source 2 and the voltage V c to the cathode of this source. We denote V gc the control voltage which is equal to V g -V c . Cathode characteristics are shown in Figure 3 (curves I and II). We denote V tll the threshold voltage. For a control voltage Vo greater than Vth, the curve I corresponds to a cathode current lo while the curve II corresponds to a current Io-Δl. '
Les électrons émis par la source d'électrons sont accélérés et collectés par l'anode soumise à la haute tension Va. Si l'on dépose une couche de matériau luminophore (en anglais "phosphor") 28 sur le conducteur d'anode 6 alors l'énergie cinétique des électrons est convertie en lumière.The electrons emitted by the electron source are accelerated and collected by the anode subjected to the high voltage V a . If a layer of phosphor material (in English "phosphor") 28 is deposited on the anode conductor 6 then the kinetic energy of the electrons is converted into light.
Il est possible d'obtenir un écran d'affichage en organisant la structure de base de la figure 1 sous la forme d'une structure matricielle. Cette dernière doit permettre l'adressage de chaque pixel de 1 ' écran et donc la commande de la luminance du pixel considéré (voir le document [5] ) .It is possible to obtain a display screen by organizing the basic structure of FIG. 1 in the form of a matrix structure. The latter must allow the addressing of each pixel of the screen and therefore the control of the luminance of the pixel considered (see document [5]).
Un écran à structure matricielle utilisant une source d'électrons à structure matricielle 30 est schematiquement représenté sur la figure 4. Chaque pixel de la source d'électrons 30 est défini par l'intersection d'une électrode de ligne et d'une électrode de colonne de cette source. On note Lx, L2 ... Lj. ... Ln les électrodes de ligne de cette source et les électrodes de colonne de la source sont notées Cx ,A screen with a matrix structure using an electron source with a matrix structure 30 is schematically represented in FIG. 4. Each pixel of the electron source 30 is defined by the intersection of a line electrode and a storage electrode. column from this source. We note L x , L 2 ... Lj . ... L n the line electrodes of this source and the column electrodes of the source are denoted C x ,
C2 ... Cj ... Cm. L'écran de la figure 4 comprend un générateur 34 de balayage des lignes. Ce générateur est muni d'une source 36 de tension Vιns et d'une source 38 de tension Vχs . On note Vxi la tension de commande de la ligne Lj.. L'écran comprend aussi des moyens 40 de génération des tensions de commande des colonnes. On note VCj la tension de commande de la colonne Cj .C 2 ... C j ... C m . The screen in Figure 4 includes a line scan generator 34. This generator is provided with a source 36 of voltage Vι ns and a source 38 of voltage Vχ s . We denote by V xi the control voltage of the line Lj . . The screen also includes means 40 for generating the column control voltages. V Cj denotes the control voltage of column C j .
Plus précisément on affecte un circuit de commande à chaque ligne et à chaque colonne de l'écran et on effectue un adressage une ligne à la fois pendant un temps tιig. Les lignes sont donc portées séquentiellement à un potentiel Vls appelé potentiel de sélection de ligne tandis que les colonnes sont portées à un potentiel correspondant à l'information à afficher. Pendant ce temps tiig les lignes non sélectionnées sont portées à un potentiel Vχns tel que les tensions présentes sur les colonnes n'affectent pas l'affichage sur ces lignes. Pour obtenir des niveaux de gris, on peut agir sur la valeur des tensions de commande Vij.- Cj ou sur leur durée co cette durée devant rester inférieure ou égale à tlig.More precisely, a control circuit is assigned to each line and to each column of the screen and addressing is carried out one line at a time for a time tι ig . The rows are therefore brought sequentially to a potential V ls called row selection potential while the columns are brought to a potential corresponding to the information to be displayed. During this time t iig the non-selected lines are brought to a potential Vχ ns such that the voltages present on the columns do not affect the display on these lines. To obtain gray levels, it is possible to act on the value of the control voltages Vij . - Cj or over their duration co this duration must remain less than or equal to t lig .
D'autres procédés de commande sont possibles. On connaît par exemple le procédé de commande utilisant des charges électriques, plus simplement appelé "procédé de commande en charge" (voir le document [6]). On connaît aussi un procédé de commande utilisant un courant, plus simplement appelé "procédé de commande en courant" (voir le document [7]) .Other control methods are possible. We know for example the control method using electrical charges, more simply called "charge control method" (see document [6]). There is also known a control method using a current, more simply called "current control method" (see document [7]).
On s'intéresse dans ce qui suit aux différents procédés de commande et, plus particulièrement, au procédé de commande en charge. ETAT DE LA TECHNIQUE ANTERIEUREWe are interested in what follows in the various control methods and, more particularly, in the load control method. STATE OF THE PRIOR ART
Les trois procédés de commande mentionnés ci-dessus n'apportent pas de solution totalement satisfaisante pour la commande de source d'électrons à structure matricielle. On a généralement besoin d'obtenir une émission électronique uniforme et quantifiée qui soit en même temps réalisable sans contrainte technique majeure.The three control methods mentioned above do not provide a completely satisfactory solution for controlling an electron source with a matrix structure. There is generally a need to obtain a uniform and quantified electronic emission which is at the same time achievable without major technical constraint.
La commande en tension dans ces différents procédés d'obtention de niveau de gris est largement utilisée car elle est facile à mettre en œuvre. Cela suppose toutefois que la réponse électrique de la source d'électrons soit à la fois stable et uniforme. Mais ces conditions de stabilité et d'uniformité sont difficiles à atteindre dans les sources d'électrons à structure matricielle connues. En effet, une exigence élevée d'uniformité pour un écran conduit à des taux de rejet qui peuvent être importants. De même, on est confronté à des problèmes de vieillissement différentiel qui, en détruisant l'uniformité des sources en fonction de l'usage plus ou moins répété de telle ou telle zone de la source, nuisent à leur durée de vie réelle.The voltage control in these different gray level obtaining methods is widely used because it is easy to implement. This assumes, however, that the electrical response of the electron source is both stable and uniform. However, these conditions of stability and uniformity are difficult to achieve in electron sources with known matrix structure. Indeed, a high requirement of uniformity for a screen leads to rejection rates which can be high. Likewise, we are faced with problems of differential aging which, by destroying the uniformity of the sources as a function of the more or less repeated use of such or such zone of the source, harm their real lifespan.
Une commande en courant peut sembler résoudre ce problème car on est alors amené à injecter un courant et donc une quantité déterminée d'électrons. Un tel principe est effectivement valable en régime statique. En revanche, dès que l'on veut faire varier rapidement le courant de la source d'électron, on est confronté à un problème de charge capacitive. En effet, une électrode de colonne s'apparente à un condensateur par rapport aux lignes que cette colonne croise et le courant nécessaire à la charge rapide de ce condensateur s'avère supérieur, de plusieurs ordres de grandeur, au courant d'émission.A current command may seem to solve this problem because we are then required to inject a current and therefore a determined quantity of electrons. Such a principle is effectively valid under static conditions. On the other hand, as soon as one wants to quickly vary the current of the electron source, one is confronted with a problem of capacitive load. Indeed, a column electrode is similar to a capacitor with respect to the lines that this column crosses and the current necessary for the rapid charging of this capacitor proves to be greater, by several orders of magnitude, than the emission current.
A titre d'exemple, dans un écran à micropointes ayant une définition de 1/4 VGA et une surface valant environ 1 dm2, la capacité d'une colonne par rapport aux lignes Ccoι vaut environ 400 pF. Si l'on veut "allumer" c'est-à-dire exciter un pixel, on fait passer le courant de ce pixel d'une valeur quasiment nulle jusqu'à une valeur d'environ 10 μA et, pour ce faire, on augmente la tension ligne-colonne d'environ 40 V. Si la commutation doit se faire en 1 μs (temps qui est à comparer à un temps de ligne de 60 μs) , le courant capacitif s'élève à :By way of example, in a microtip screen having a definition of 1/4 VGA and an area equal to approximately 1 dm 2 , the capacity of a column relative to the lines C co ι is approximately 400 pF. If we want to "turn on", that is to say excite a pixel, we pass the current of this pixel from an almost zero value to a value of about 10 μA and, to do this, we increases the line-column voltage by approximately 40 V. If the switching must be done in 1 μs (time which is to be compared to a line time of 60 μs), the capacitive current amounts to:
I=Ccoι-dV/dt c'est-à-dire environ à 16 mA. Le courant capacitif est ainsi 1000 fois plus grand que le courant d'émission que l'on veut régler. On comprend qu'une telle méthode ne soit pas adaptée à la commande rapide d'une source à structure matricielle .I = C co ι-dV / dt i.e. around 16 mA. The capacitive current is thus 1000 times greater than the emission current that we want to adjust. It is understood that such a method is not suitable for the rapid control of a source with a matrix structure.
Pour résoudre le problème précédent, une commande en charge a déjà été proposée (voir le document [6] ) . La figure 5 illustre schematiquement un écran de visualisation comprenant une source d'électrons à structure matricielle utilisant une commande en charge. L'écran connu de la figure 5 ne diffère de celui de la figure 4 que par les moyens d'application des tensions de commande aux colonnes de la source de l'écran. Dans le cas de la figure 5, les moyens 42 d'application d'une tension de commande à une colonne, par exemple la colonne Cj , comprennent un bloc logique 44, qui reçoit en entrée un signal de synchro ligne El, et un comparateur 46, qui reçoit en entrée une valeur de consigne Al et qui est relié au bloc logique 44 comme on le voit sur la figure 5. Les moyens d'application de tension 42 comprennent aussi un étage de sortie à trois états 48 qui est également relié au bloc logique 44 et reçoit des tensions respectivement notées Vc_on et Vc_off de la part de sources de tension non représentées. L'étage de sortie à trois états et le comparateur sont reliés à la colonne correspondante de la source d'électrons (Cj dans l'exemple considéré)To solve the previous problem, a load command has already been proposed (see document [6]). FIG. 5 schematically illustrates a display screen comprising an electron source with a matrix structure using a charge command. The known screen of FIG. 5 differs from that of FIG. 4 only by the means for applying the control voltages to the columns of the source of the screen. In the case of Figure 5, the means 42 for applying a control voltage to a column, for example column C j , comprise a logic block 44, which receives as input a line sync signal El, and a comparator 46, which receives as input a value setpoint A1 and which is connected to logic block 44 as seen in FIG. 5. The voltage application means 42 also include a three-state output stage 48 which is also connected to logic block 44 and receives voltages respectively denoted V c _ on and V c _ of f by unrepresented voltage sources. The three-state output stage and the comparator are connected to the corresponding column of the electron source (Cj in the example considered)
Dans le cas de la commande en charge, on pré-charge le conducteur de colonne considéré pour assurer l'émission des sources (Vc_on) . Puis on ouvre le circuit pour laisser le condensateur de la colonne se décharger sur son impédance interne, jusqu'à ce que le potentiel flottant VCj atteigne la valeur Al de consigne correspondant à la quantité d'électrons souhaitée. On ramène alors la colonne au potentiel d'extinction (Vc-.off) . Une telle façon de faire semble parfaite mais suppose l'utilisation de composants également parfaits et la mise en œuvre d'une telle méthode s'avère difficile.In the case of the command in charge, the column conductor considered is preloaded to ensure the emission of the sources (V c _ on ). Then the circuit is opened to let the column capacitor discharge on its internal impedance, until the floating potential V C j reaches the set value Al corresponding to the quantity of electrons desired. The column is then brought back to the extinction potential (V c -. Off ). Such a way of doing things seems perfect but supposes the use of equally perfect components and the implementation of such a method proves difficult.
En effet on a vu plus haut qu'une électrode de colonne s'apparentait à un condensateur par rapport aux lignes de la source à structure matricielle mais il existe également des courants de fuite qui circulent entre la colonne considérée et les lignes et ces courants varient avec la différence de potentiel entre ces électrodes. De ce fait, lorsqu'on ouvre le circuit, la chute de tension ne dépend pas du seul courant d'émission mais également de courants de fuite qui varient eux-mêmes en fonction de cette chute. Plus précisément, cette évolution du potentiel est requise pour mesurer la charge prélevée dans la capacité propre de la colonne mais cette variation pose un problème. En effet, pendant le temps tϋg chacune des colonnes va fuir par rapport à la ligne sélectionnée mais aussi par rapport à l'ensemble des lignes non sélectionnées. Pour simplifier, on suppose que ce défaut s'apparente à une résistance de fuite Ric identique pour tous les pixels. Cette valeur représente l'impédance de fuite ligne/colonne pour une ligne et une colonne quelconques. Pour une colonne et pendant le temps d'émission, ce courant de fuite If s'exprime de la façon suivante :In fact, we saw above that a column electrode was similar to a capacitor with respect to the lines of the source with matrix structure, but there are also leakage currents which circulate between the column considered and the lines and these currents vary. with the potential difference between these electrodes. Therefore, when the circuit is opened, the voltage drop does not depend only on the emission current but also on leakage currents which themselves vary as a function of this drop. More precisely, this change in potential is required to measure the charge taken from the column's own capacity, but this variation poses a problem. Indeed, during the time t ϋg each of the columns will leak with respect to the selected row but also with respect to all of the non-selected rows. For simplicity, it is assumed that this defect is similar to a leakage resistance R ic identical for all the pixels. This value represents the row / column leakage impedance for any row and column. For a column and during the emission time, this leakage current I f is expressed as follows:
If=If (ls) +1f (lns) (Vιs-Vcj (t) ) /Rlc+ (n-1) . (Vlns-Vcj (t) ) /Rlc I f = If (ls) + 1f (lns) (Vι s -V cj (t)) / R lc + (n-1). (V lns -V cj (t)) / R lc
Avec :With:
If≈ Courant de fuite d'une colonne par rapport à toutes les lignes If(is)= Courant de fuite d'une colonne par rapport à la ligne sélectionnéeI f ≈ Leakage current of a column with respect to all rows I f ( i s ) = Leakage current of a column with respect to the selected row
I f(ins)= Courant de fuite d'une colonne par rapport aux lignes non sélectionnées Vιs= Potentiel appliqué à la ligne sélectionnée Vιns= Potentiel appliqué aux lignes non sélectionnées vCj(t)= Potentiel flottant de la colonne j pendant le temps d'émission n= Nombre de lignes . I f (i ns ) = Leakage current of a column compared to the lines not selected Vι s = Potential applied to the selected line Vι ns = Potential applied to the lines not selected v Cj (t) = Floating potential of column j during transmission time n = Number of lines.
Pour simplifier, on peut prendre Vlns égal à OV et, sachant que Vcj(t) est très inférieur à Vιs, on a alors :To simplify, we can take V lns equal to OV and, knowing that V c j (t) is much less than Vι s , we then have:
différent de (V/Rlc) - (n-1) . (Vcj ( t) /Rlc) different from (V / R lc ) - (n-1). (V cj (t) / R lc )
Cela impose de sévères contraintes sur les valeurs Rlc des différentes colonnes de 'l'écran. Soit les courants de fuite sont négligeables (ce qui correspond à des valeurs Rj_c élevées) soit ils ne le sont pas complètement et il faut alors assurer au minimum une très bonne homogénéité de ces résistances Rlc.This imposes severe constraints on the R lc values of the different columns of the screen. Either the leakage currents are negligible (which corresponds to high Rj_ c values) or they are not completely so and it is then necessary to ensure at least very good homogeneity of these resistors R lc .
On voit aussi qu'un seul pixel défectueux du point de vue de Rχc impose sa fuite à l'ensemble de la colonne considérée, par l'intermédiaire du terme (n- 1) de la formule donnée ci-dessus. Dans l'exemple considéré, la chute de tension de colonne due à l'émission vaut :We also see that a single defective pixel from the point of view of Rχ c imposes its leakage on the whole of the column considered, via the term (n- 1) of the formula given above. In the example considered, the drop in column voltage due to the emission is worth:
ΔVcj = I • tig/Ccoι, de sorte que, avec 1=10 μA, tug=50 μs et Ccoι=400pF, on obtient ΔVcj=l,25V. On rappelle que cette variation ΔVCj doit être comparée à la valeur de consigne Al. Cette variation de la tension ΔVCj dépend de la valeur de la capacité de la colonne, ce qui ramène des variables technologiques de l'écran (liées aux dimensions de cet écran) dans les paramètres de conception du circuit de commande. Pour sa mise en œuvre, on voit aussi que le comparateur 46 se trouve au niveau de l'étage de sortie de l'ensemble formant les moyens de génération des tensions de commande des colonnes. Cela signifie que ce comparateur doit soit supporter la dynamique de tension nécessaire à la commande des colonnes (environ 40 V) soit pouvoir s'isoler de cette sortie par un étage supplémentaire .ΔV cj = I • ti g / C co ι, so that, with 1 = 10 μA, tu g = 50 μs and C co ι = 400pF, we obtain ΔV cj = 1.25V. It is recalled that this variation ΔV Cj must be compared with the set value Al. This variation of the voltage ΔV C j depends on the value of the capacity of the column, which brings back technological variables of the screen (related to the dimensions from this screen) in the control circuit design parameters. For its implementation, we also see that the comparator 46 is located at the output stage of the assembly forming the means for generating the column control voltages. This means that this comparator must either support the voltage dynamic range necessary for controlling the columns (approximately 40 V) or be able to isolate itself from this output by an additional stage.
EXPOSÉ DE L'INVENTIONSTATEMENT OF THE INVENTION
La présente invention a pour but de remédier aux divers inconvénients précédents . Elle a pour objet un procédé de commande d'une source d'électrons à structure matricielle, cette source comprenant au moins une ligne et au moins une colonne d'adressage, dont l'intersection définit une ou des zones émissives appelées pixels et où les électrons sont fournis par la colonne, ce procédé étant un procédé séquentiel caractérisé en ce que :The object of the present invention is to remedy the various preceding drawbacks. It relates to a method for controlling a source of electrons with a matrix structure, this source comprising at least one line and at least one addressing column, the intersection of which defines one or more emissive zones called pixels and where the electrons are supplied by the column, this process being a sequential process characterized in that:
- dans un premier temps , on déclenche l'émission des électrons par application de potentiels sur la ligne sélectionnée et la ou les colonnes à une vapeur apte à permettre cette émission puis on maintient le potentiel de la ou des colonnes à cette valeur pendant toute la durée de l'émission alors que, simultanément, la mesure de la quantité de charges émises par le ou les pixels respectivement de ladite ou desdites colonnes est assurée dans la ou les colonnes, et- firstly, the emission of electrons is triggered by application of potentials on the selected line and the column (s) with a vapor capable of allowing this emission, then the potential of the column (s) is maintained at this value throughout the duration of the emission while, simultaneously, the measurement of the quantity of charges emitted by the pixel or pixels respectively of said column or columns is ensured in the column or columns, and
- dans un deuxième temps , lorsque la quantité de charges mesurée sur une colonne atteint une quantité de charges requise, on commute le potentiel de cette colonne à une valeur qui assure le blocage de l'émission des électrons.- secondly, when the quantity of charges measured on a column reaches a required quantity of charges, the potential of this column has a value which blocks the emission of electrons.
Selon un mode de mise en oeuvre préféré du procédé objet de l'invention, la valeur apte à permettre l'émission, est égale au potentiel de la ou des lignes non adressées .According to a preferred embodiment of the method which is the subject of the invention, the value capable of allowing transmission is equal to the potential of the unaddressed line or lines.
L'invention a également pour objet un dispositif de commande d'une source d'électrons à structure matricielle, cette source comprenant au moins une ligne et au moins une colonne d' a-dressage dont chaque intersection définit une zone appelée pixel et où les électrons sont fournis par la colonne, ce dispositif étant caractérisé en ce qu'il comprend :The invention also relates to a device for controlling a source of electrons with a matrix structure, this source comprising at least one line and at least one column of a-dressage, each intersection of which defines an area called a pixel and where the electrons are supplied by the column, this device being characterized in that it comprises:
- des moyens de commande de la ou des lignes d'adressage par application sur la ligne sélectionnée d'un potentiel de sélection, alors qu'hors temps de sélection la ou les lignes restent à un potentiel assurant le blocage de l'émission des pixels correspondants , - des moyens de commande de la ou des colonnes, ces moyens de commande comprenant, pour chaque colonne, des moyens d'application, lors d'une sélection ligne, soit d'une première tension assurant l'émission soit d'une deuxième tension assurant le blocage sur ladite colonne,means for controlling the address line or lines by applying a selection potential to the selected line, while outside the selection time the line or lines remain at a potential ensuring the blocking of the emission of the pixels corresponding, - means for controlling the column or columns, these control means comprising, for each column, means of application, during a line selection, either of a first voltage ensuring the emission of either a second tension ensuring blocking on said column,
- des moyens permettant à la fois la mesure, dans la ou les colonnes, de la quantité de charges émise durant l'émission et le maintien constant de la tension assurant l'émission sur ladite colonne pendant cette mesure, et - des moyens de comparaison de la quantité de charges mesurée à une quantité de charges de référence, avec rétroaction sur les moyens de commande des colonnes . Selon un mode de réalisation particulier, la quantité de charge déjà émise est convertie en un niveau de tension. Le dispositif objet de l'invention peut comprendre en outre des moyens de compensation de courants de fuites résiduels. Ce dispositif peut aussi comprendre des moyens de compensation de couplages capacitifs intercolonnes .means allowing both the measurement, in the column or columns, of the quantity of charges emitted during the emission and the constant maintenance of the voltage ensuring the emission on the said column during this measurement, and means for comparing the quantity of charges measured with a quantity of reference charges, with feedback on the control means of the columns. According to a particular embodiment, the quantity of charge already emitted is converted into a voltage level. The device which is the subject of the invention may further comprise means for compensating for residual leakage currents. This device can also include means for compensating intercolumn capacitive couplings.
BRÈVE DESCRIPTION DES DESSINS La présente invention sera mieux comprise à la lecture de la description d'exemples de réalisation donnés ci-après, à titre purement indicatif et nullement limitatif, en faisant référence aux dessins annexés sur lesquels : " la figure 1 illustre schematiquement le principe de fonctionnement d'un écran d'affichage utilisant un dispositif à émission de champ et a déjà été décrite, " la figure 2 illustre schematiquement la structure d'un écran à micropointes et a déjà été décrite,BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given below, by way of purely indicative and in no way limiting, with reference to the appended drawings in which: "Figure 1 schematically illustrates the operating principle of a display screen using a field emission device and has already been described, "FIG. 2 schematically illustrates the structure of a microtip screen and has already been described,
" la figure 3 montre les caractéristiques Icat = f(VgC) dans le cas d'un écran à micropointes du genre triode et a déjà été décrite,"FIG. 3 shows the characteristics I cat = f (V gC ) in the case of a microdot screen of the triode type and has already been described,
" la figure 4 illustre schematiquement un écran d'affichage utilisant un dispositif à émission de champ à structure matricielle et a déjà été décrite, • la figure 5 est une vue schématique d'un dispositif connu de commande d'une source d'électrons à structure matricielle et a déjà été décrite, » la figure 6 est une vue schématique d'un mode de réalisation particulier du dispositif objet de"FIG. 4 schematically illustrates a display screen using a device for transmitting field with a matrix structure and has already been described, • Figure 5 is a schematic view of a known device for controlling an electron source with a matrix structure and has already been described, »Figure 6 is a schematic view d '' a particular embodiment of the device object of
1 ' invention, " la figure 7 illustre schematiquement un exemple de dispositif de commande d'une colonne dans un dispositif conforme à l'invention, " la figure 8 est un chronogramme des différentes tensions utilisées dans le dispositif de la figure 7, a la figure 9 illustre schematiquement une variante de la figure 7, " la figure 10 illustre schematiquement un exemple d'un dispositif de commande d'une colonne avec compensation du courant de fuite, dans un dispositif conforme à l'invention,1 invention "Figure 7 illustrates schematically an example of a column control device in a device according to the invention," Figure 8 is a timing diagram of various voltages used in the device of Figure 7, has the FIG. 9 schematically illustrates a variant of FIG. 7, "FIG. 10 schematically illustrates an example of a device for controlling a column with compensation for the leakage current, in a device according to the invention,
" la figure 11 illustre schematiquement un exemple de réalisation d'un dispositif de commande d'une colonne avec filtrage par diodes des charges parasites dues aux capacités inter-colonnes , conformément à l'invention,"FIG. 11 schematically illustrates an exemplary embodiment of a device for controlling a column with filtering by diodes of the parasitic loads due to the inter-column capacities, in accordance with the invention,
" la figure 12 illustre schematiquement un exemple de réalisation d'un dispositif de commande d'une colonne avec filtrage par transistors des charges parasites dues aux capacités inter-colonnes, conformément à l'invention, et " la figure 13 illustre schematiquement un exemple de réalisation d'un dispositif de commande d'une colonne avec compensation analogique des charges parasites dues aux capacités inter-colonnes, conformément à l'invention."FIG. 12 diagrammatically illustrates an exemplary embodiment of a device for controlling a column with filtering by parasitic loads due to the inter-column capacities, in accordance with the invention, and "FIG. 13 schematically illustrates an exemplary embodiment of a device for controlling a column with analog compensation for parasitic loads due to the inter-column capacities, in accordance with the invention.
EXPOSÉ DÉTAILLÉ DE MODES DE RÉALISATION PARTICULIERSDETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
La technique de commande en charge, qui a été décrite plus haut et qui est également mentionnée dans le document [6] , pose donc le problème principal de l'évolution du potentiel des colonnes commandées.The load control technique, which has been described above and which is also mentioned in document [6], therefore poses the main problem of the evolution of the potential of the columns ordered.
Considérons en effet l'expression du courant de fuite IfUite que 1 ' on a vue précédemment :Consider in fact the expression of the leakage current I fU i te that we have seen previously:
I fui te = 1 fui te ls + T-fuite lns= ( Vιs -Vc -OI1 ( t ) ) /Ric+ ( n-1 ) X ( Vlns- I f ui te = 1 f ui t e ls + T - f ui te lns = (Vι s -V c - OI1 (t)) / R ic + (n-1) X (V lns -
Cette expression met clairement en évidence la composante de courant de fuite par rapport à la ligne sélectionnée et la composante de courant de fuite par rapport aux (n-1) lignes non sélectionnées. La première de ces composantes est inévitable puisqu'elle est liée au principe même de balayage de l'écran. La deuxième de ces composantes peut être annulée à condition que V0j(t) et Vιns soit tous deux égaux à une même constante.This expression clearly highlights the leakage current component with respect to the selected line and the leakage current component with respect to the (n-1) unselected lines. The first of these components is inevitable since it is linked to the very principle of screen scanning. The second of these components can be canceled provided that V 0j (t) and Vι ns are both equal to the same constant.
La présente invention propose un circuit de commande qui fonctionne dans ces conditions.The present invention provides a control circuit which operates under these conditions.
On a vu plus haut les différents blocs fonctionnels nécessaires à la commande en charge dans l'art antérieur (document [6]) en liaison avec la figure 5. Les différents blocs fonctionnels d'un dispositif conforme à l'invention sont schematiquement représentés sur la figure 6. Sur cette figure 6, la référence 50 représente les moyens de commande d'une colonne de l'écran (Cj) . Ces moyens de commande 50 comprennent, comme on le voit, une logique de commande 52, un comparateur 54, un intégrateur de courant avec contrôle de Vcoχ et un étage de sortie 58.We have seen above the different functional blocks necessary for load control in the prior art (document [6]) in conjunction with the FIG. 5. The different functional blocks of a device according to the invention are schematically represented in FIG. 6. In this FIG. 6, the reference 50 represents the means for controlling a column of the screen (Cj). These control means 50 comprise, as can be seen, a control logic 52, a comparator 54, a current integrator with control of V co χ and an output stage 58.
Dans cet exemple de l'invention, on réalise chronologiquement les fonctions suivantes. On initialise le pixel de cette colonne Cj en émissionIn this example of the invention, the following functions are performed chronologically. The pixel of this column C j is initialized in transmission
(VCj = Vc_on) à l'aide de l'étage de sortie 58. On intègre le courant fournit par les émetteurs tout en maintenant le potentiel de colonne stable à la valeur Vc-on. Pour ce faire, on utilise un bloc fonctionnel qui sera décrit dans la suite. On obtient ainsi en A2 (voir figure 6) une tension qui est proportionnelle à la charge émise. On coupe l'émission du pixel (VCj = Vc_0 f) par l'étage de sortie 58 lorsque la charge requise, choisie par une valeur de consigne externe Al, a été fournie. Dans ce mode de fonctionnement et pendant l'émission du pixel considéré l'équation (1) devient l'équation (2) :(V Cj = V c _ on ) using the output stage 58. The current supplied by the emitters is integrated while keeping the column potential stable at the value V c - on . To do this, we use a functional block which will be described below. A voltage is thus obtained in A2 (see FIG. 6) which is proportional to the charge emitted. The emission of the pixel is cut (V Cj = V c _ 0 f ) by the output stage 58 when the required charge, chosen by an external reference value Al, has been supplied. In this operating mode and during the emission of the pixel considered equation (1) becomes equation (2):
Ifuite=Ifuite ls + Ifuite lns = ( Vιs-Vcj _on) /Rχc+ ( n- 1 ) X ( Vlns-Vcj_on ) /Rj.c I f ui t e = I f ui te l s + Ifuite lns = (Vι s -V c j _ on ) / Rχ c + (n- 1) X (V lns -V c j_ on ) / Rj .c
La tension de colonne est devenue fixe etThe column tension has become fixed and
Vcj-on(t) et Vc_orι sont tous deux égaux à une même valeur constante. On peut alors annuler le terme de fuite par rapport aux (n-1) lignes en choisissant Vc_on égal à Vιns. Par souci de simplification, on définit ces deux potentiels comme étant égaux à la référence de masse de l'ensemble du dispositif. On obtient alors :V cj - on (t) and V c _ orι are both equal to the same constant value. We can then cancel the leakage term with respect to (n-1) lines by choosing V c _ on equal to Vι ns . For the sake of simplification, we define these two potentials as being equal to the mass reference of the entire device. We then obtain:
If ite=Ifuite ls =s/Rιc ( 3 )I f i te = I fu i te ls =s / Rι c (3)
On aperçoit immédiatement l'intérêt du procédé de commande utilisé dans cet exemple de l'invention puisque, même s'il reste un courant de fuite, ce dernier ne dépend plus que du pixel adressé et non plus des (n-1) autres pixels non adressés de la même colonne. En d'autres termes, ' le procédé d'adressage utilisé dans cet exemple de l'invention permet, pour un même écran (en termes de résistance Rie), une meilleure qualité d'image.We can immediately see the advantage of the control method used in this example of the invention since, even if there is a leakage current, the latter only depends on the addressed pixel and no longer on the (n-1) other pixels. not addressed in the same column. In other words, 'the method of addressing used in this example of the invention allows, for the same screen (in terms of resistance R e), better image quality.
Dans ces conditions, une compensation de ce courant résiduel est possible car, la tension V étant fixe, ce courant est constant. On peut donc injecter, sur chaque colonne et pendant chaque temps de ligne, le courant de signe opposé.Under these conditions, a compensation of this residual current is possible because, the voltage V being fixed, this current is constant. We can therefore inject, on each column and during each row time, the current of opposite sign.
L'invention concerne donc un procédé séquentiel de commande d'une source d'électrons qui permet' :The invention therefore relates to a sequential control process for an electron source which allows':
- le maintien, pendant toute la durée de l'émission, du potentiel des colonnes égal à celui des lignes non adressées ainsi que la mesure simultanée de la quantité de charges émisses par les pixels de ces colonnes,- maintaining, throughout the duration of the transmission, the potential of the columns equal to that of the unaddressed lines as well as the simultaneous measurement of the quantity of charges emitted by the pixels of these columns,
- le retour de ce potentiel de colonne à un niveau assurant le blocage de l'émission lorsque la quantité de charge mesurée atteint une quantité de charge requise . On considère maintenant un exemple de dispositif de commande d'une colonne, conformément à l'invention, qui est représenté sur la figure 7.the return of this column potential to a level ensuring the blocking of the emission when the quantity of charge measured reaches a quantity of charge required. We now consider an example of a column control device, in accordance with the invention, which is shown in FIG. 7.
Ce dispositif de commande 60 comprend un étage de sortie 62 du genre push-pull, un montage intégrateur de courant 64 et un comparateur 66.This control device 60 comprises an output stage 62 of the push-pull type, a current integrator assembly 64 and a comparator 66.
L'étage de sortie 62 permet de commuter, sur l'électrode de colonne (Cj), soit la tension d'alimentation Vc_0ff correspondant au niveau d'extinction du pixel soit l'entrée- du montage intégrateur 64 qui impose par sa masse virtuelle le niveau Vc_0n (le mettant au potentiel des lignes non sélectionnées). L'étage de sortie 62 comprend de façon connue des moyens 68 de translation de niveau logique et deux transistors MOSFET 70 et 72, le transistor 70 étant de type P et le transistor 72 de type N, ces moyens 68 et ces transistors étant agencés comme on le voit sur la figure 7.The output stage 62 makes it possible to switch, on the column electrode (C j ), either the supply voltage V c _ 0 f f corresponding to the pixel extinction level or the input- of the integrator circuit 64 which imposes by its virtual mass the level V c _ 0n (putting it at the potential of the lines not selected). The output stage 62 comprises in known manner means 68 of logic level translation and two MOSFET transistors 70 and 72, the transistor 70 being of type P and the transistor 72 of type N, these means 68 and these transistors being arranged as seen in Figure 7.
Le montage intégrateur 64 comprend un amplificateur 74 qui est bouclé sur un condensateur 76 de capacité Cint qui est lui-même monté en parallèle avec un interrupteur commandé SW1, la sortie A2 de cet amplificateur étant reliée à l'entrée (-) du comparateur 66. L'interrupteur commandé permet de ramener à zéro le potentiel A2 en début de chaque ligne.The integrator assembly 64 comprises an amplifier 74 which is looped over a capacitor 76 of capacity Ci nt which is itself mounted in parallel with a controlled switch SW1, the output A2 of this amplifier being connected to the input (-) of the comparator 66. The controlled switch enables the potential A2 to be brought to zero at the start of each line.
L'entrée (+)du comparateur est reliée à une tension de consigne Al correspondant à la quantité de charges à émettre. Dans la présente invention, cette consigne de tension peut être fournie par divers moyens qui dépendent de l'application souhaitée de l'invention. Dans l'exemple représenté sur la figure 7, on utilise un convertisseur numérique analogique CDA qui reçoit en entrée une donnée numérique DN de tension de consigne et dont la sortie fournit le potentiel de consigne Al.The comparator input (+) is connected to a reference voltage Al corresponding to the quantity of charges to be emitted. In the present invention, this voltage setpoint can be provided by various means which depend on the desired application of the invention. In the example shown in FIG. 7, a digital analog converter CDA is used which receives as input a digital datum DN of setpoint voltage and whose output provides the setpoint potential Al.
La sortie S2 du montage comparateur constitue la commande de l'étage de sortie push-pull permettant ainsi le bouclage du dispositif.The output S2 of the comparator assembly constitutes the control of the push-pull output stage thus allowing the device to be looped.
Le signal SI (correspondant au début du temps qui est alloué à une ligne) , - suivant une chronologie qui sera décrite dans la suite, commande l'interrupteur SWl . On voit que la logique de commande 52, qui fournit SI, commande aussi un circuit de commande de ligne PL non représenté. La figure 8 représente le diagramme temporel des différentes tensions au sein du dispositif, lors d'un cycle d'adressage ligne. Le cycle (voir la figure 8 partie A) démarre au temps t0, par le top de début du signal SI (voir la figure 8 partie B) déclenchant la montée de S2 (voir la figure 8 partie C) qui, par l'étage de sortie, fait passer la colonne Vcj à Vc-on (masse virtuelle) . Après un temps permettant à Vcj de s'établir à la tension Vc_on(temps ton) , le signal SI passe au niveau bas pour ouvrir l'interrupteur SWl, ce qui débute l'intégration de courant dans Cιnt • Pour déclencher l'émission, VLi passe de son potentiel Vι (défini comme étant la masse du montage) au potentiel de sélection Vιs, l'ensemble Ul et Cint se charge alors en A2 (voir la figure 8 partie D) , selon la loi :The signal SI (corresponding to the start of the time which is allocated to a line), - according to a chronology which will be described below, controls the switch SW1. It can be seen that the control logic 52, which supplies SI, also controls a line control circuit PL, not shown. FIG. 8 represents the time diagram of the different voltages within the device, during a line addressing cycle. The cycle (see figure 8 part A) starts at time t 0 , by the signal start signal SI (see figure 8 part B) triggering the rise of S2 (see figure 8 part C) which, by output stage, changes column V c j to V c - on (virtual mass). After a time allowing V c j to settle at the voltage V c _ on (time t on ), the signal SI goes low to open the switch SWl, which begins the integration of current in Cι nt • To trigger the emission, V Li goes from its potential Vι (defined as the mass of the assembly) to the selection potential Vι s , the set Ul and C int then loads into A2 (see Figure 8 part D ) , according to the law :
A2=-Ixt/Cint. Lorsque le potentiel A2 atteint le potentiel de consigne Al, le comparateur U2 bascule sur sa sortie S2 (descente de S2 ) , ce qui, par l'étage de sortie, impose le retour de VCj à Vc_ofÊ (voir la figure 8 partie E) , à l'instant t=toff tel que :A2 = -I x t / C int . When the potential A2 reaches the set potential Al, the comparator U2 switches to its output S2 (descent of S2), which, through the output stage, requires the return of V C j to V c _ ofÊ (see the Figure 8 part E), at time t = t off such that:
Q=I. (t0ff-ton)=CintxAl.Q = I. (t 0ff -t on ) = C int xAl.
On voit donc que le dispositif décrit permet de délivrer au pixel considéré une charge contrôlée par la consigne fournie Al," et ce sans variation de la tension appliquée sur la colonne, pendant le temps d'émission.It can therefore be seen that the device described makes it possible to deliver to the pixel considered a charge controlled by the setpoint supplied A1, " and this without variation of the voltage applied to the column, during the transmission time.
On notera que l'on fait basculer le potentiel ligne VLi vers le potentiel de sélection Vιs, après l'établissement du potentiel de la colonne (VCj), de manière à réduire la capacité à charger uniquement à celle du pixel considéré. Le courant capacitif dans la colonne sera donc minimisé.It will be noted that the line potential V L i is switched over to the selection potential Vι s , after the column potential has been established (V Cj ), so as to reduce the capacity to charge only to that of the pixel considered. . The capacitive current in the column will therefore be minimized.
Si le potentiel VLι augmente avant ton, le courant d'émission s'établit avant le début de l'intégration (et les charges correspondantes ne sont donc pas mesurées) . Si VLi monte pendant ou après le début de l'intégration (ton) , les charges correspondant au courant capacitif de pixel sont mesurées et se traduisent par un décalage (offset) initial de tension sur A2. Une légère différence de phase, entre la montée de VLi et le front descendant de Si, peut donc être ajustée pour adopter le meilleur compromis selon 1' application.If the potential V L ι increases before t on , the emission current is established before the start of integration (and the corresponding charges are therefore not measured). If V L i rises during or after the start of integration (t on ), the charges corresponding to the capacitive pixel current are measured and result in an initial voltage offset on A2. A slight difference in phase, between the rise of V Li and the falling edge of Si, can therefore be adjusted to adopt the best compromise according to the application.
Pour éviter de commuter inutilement à Vc_on une colonne devant afficher du noir, on notera que ce niveau peut être géré directement par la logique de commande en maintenant au niveau bas le signal SI de la colonne correspondante.To avoid unnecessarily switching to V c _ on a column to display black, it should be noted that this level can be managed directly by the control unit while keeping the signal SI in the corresponding column low.
Un autre exemple de réalisation d'un dispositif de commande d'une colonne conformément à 1 ' invention est schematiquement représenté sur la figure 9. Il s'agit d'une variante de la figure 7.Another embodiment of a column control device according to the invention is shown diagrammatically in FIG. 9. It is a variant of FIG. 7.
En résumé, le système précédent (figure 7) convertit la quantité de charge déjà émise en un niveau de tension, ce qui permet de faire basculer le pilotage de 1 ' étage de commande de la colonne au moment 0 f où la quantité de charge (Qref) âe consigne est atteinte.In summary, the previous system (FIG. 7) converts the quantity of charge already emitted into a voltage level, which makes it possible to switch the piloting of the column control stage at time 0 f when the quantity of charge ( Q re f) the setpoint is reached.
On peut obtenir un résultat similaire en utilisant un montage de type convertisseur courant-tension CC . Le courant (Ij) étant stable pendant le temps ligne, la mesure instantanée de ce courant, associée à un circuit CCN de calcul numérique ou analogique, permet de calculer, dès le début du temps ligne, le temps toff de basculement de la colonne, temps tel que t0£ = Qref/lj-A similar result can be obtained by using a DC current-voltage converter type assembly. The current (I j ) being stable during the line time, the instantaneous measurement of this current, associated with a CCN circuit of digital or analogical calculation, makes it possible to calculate, from the start of the line time, the time t off of switching of the column, time such that t 0 £ = Qref / lj-
Cette solution est représentée en figure 9. Sur cette figure, l'interrupteur SW2 permet d'évacuer directement à la masse les courants hors instant de mesure. En effet, lors des commutations lignes/colonnes, de forts courants capacitifs pourraient perturber le convertisseur courant tension CCT.This solution is shown in FIG. 9. In this figure, the switch SW2 makes it possible to directly discharge the currents outside the measurement instant. Indeed, during row / column switching, high capacitive currents could disturb the CCT voltage current converter.
On voit sur la figure 9 que le convertisseur CCT comprend l'amplificateur 74 déjà utilisé dans- l'exemple de la figure 7 mais associé, dans le cas de la figure 9, à une résistance R montée entre l'entrée (-) et la sortie de l'amplificateur 74.It can be seen in FIG. 9 that the CCT converter comprises the amplifier 74 already used in the example of FIG. 7 but associated, in the case of FIG. 9, at a resistor R mounted between the input (-) and the output of the amplifier 74.
On voit en outre que le circuit CCN reçoit des données numériques ou analogiques de moyens appropriés DNA.It can also be seen that the CCN circuit receives digital or analog data from appropriate DNA means.
On considère maintenant la compensation des courants de fuites résiduels.We now consider the compensation for residual leakage currents.
Pour injecter, sur chaque colonne et pendant chaque temps de ligne, un courant de compensation de signe opposé à IfUite is ' il suffit de connecter une source de courant à l'entrée de mesure de l'intégrateur (voir les figures 6 et 7). Celle-ci peut par exemple être constituée d'un transistor monté en générateur de courant ou d'une résistance RComp commandée par un générateur de tension ajustable GT, comme on le voit sur la figure 10.To inject, on each column and during each row time, a compensation current of sign opposite to I fU i te i s it suffices to connect a current source to the measurement input of the integrator (see figures 6 and 7). This may for example consist of a transistor mounted as a current generator or of a resistance R Comp controlled by an adjustable voltage generator GT, as seen in FIG. 10.
On considère maintenant un autre aspect de l'invention, relatif à la compensation des couplages capacitifs inter-colonnes. Lors de la commutation du potentiel d'une colonne quelconque j de Vc-on à Vc_0ff, on induit sur les colonnes voisines (j-1) et (j+1) une charge parasite Qar=Cpar. (Cpar (Vc-on- o-of ) ; Cpar étant la capacité de couplage intercolonnes. Si les colonnes (j-1) ou j+1) se trouvent à cet instant, être toujours en émission, cette charge Qpar sera alors mesurée par les intégrateurs situés sur ces colonnes, faussant ainsi la mesure de la charge émise par les pixels desdites colonnes. Cette charge Qpar étant constante pour un format d'écran donné, plusieurs solutions sont possibles pour résoudre ce problème. Ces solutions sont combinables entre elles pour atteindre les spécifications de nombre de niveaux de gris que 1 ' on désire. Mises à part les améliorations technologiques visant à diminuer la capacité Cpar, deux grandes classes sont envisageables :We now consider another aspect of the invention, relating to the compensation of inter-column capacitive couplings. When switching the potential of any column j from V c - on to V c _ 0ff , a parasitic charge Qar = C par is induced on the neighboring columns (j-1) and (j + 1). (C by (Vc-on-o-of); C by being the intercolumn coupling capacity. If the columns (j-1) or j + 1) are at this instant, still be in transmission, this charge Q by will then be measured by the integrators located on these columns, thus distorting the measurement of the charge emitted by the pixels of said columns. This charge Q by being constant for a given screen format, several solutions are possible to solve this problem. These solutions are can be combined with one another to achieve the specifications for the number of gray levels desired. Apart from technological improvements aimed at reducing capacity C by , two main classes are possible:
I) Eviter que la charge Qpar ne soit mesurée par l'intégrateur de charge, ce qui requiert des solutions de filtrage analogique, solutions à mettre en oeuvre en amont de ce même intégrateur : La figure 11 présente un- exemple de filtrage par diodes des charges parasites dues aux capacités inter-colonnes. Cette solution est une solution asynchrone, qui se fonde sur des diodes de commutation rapides, répondant beaucoup plus vite que l'intégrateur. En d'autres termes, on joue sur le fait que les variations des courants capacitifs sont rapides par rapport à celles du courant d'émission, variations pratiquement nulles en régime établi pendant le temps ligne. Dans le même état d'esprit, on pourra chercher à mettre en oeuvre des filtres analogiques ou logiques, filtres servant à discriminer les courants d'émission des courants capacitifs parasites.I) Avoid the charge Q by being measured by the charge integrator, which requires analog filtering solutions, solutions to be implemented upstream of this same integrator: Figure 11 presents an example of diode filtering parasitic loads due to the inter-column capacities. This solution is an asynchronous solution, which is based on fast switching diodes, responding much faster than the integrator. In other words, we play on the fact that the variations of the capacitive currents are rapid compared to those of the emission current, practically zero variations in steady state during the line time. In the same state of mind, we could try to implement analog or logic filters, filters used to discriminate the emission currents from the parasitic capacitive currents.
Dans l'exemple de la figure 11, on utilise deux diodes de filtrage DF1 et DF2 pour filtrer les charges parasites dues aux capacités inter-colonnes.In the example of FIG. 11, two filter diodes DF1 and DF2 are used to filter the parasitic loads due to the inter-column capacities.
La figure 12 fournit un autre exemple de réalisation d'un dispositif de commande d'une colonne avec filtrage, cette fois par transistors, des charges parasites dues aux capacités inter-colonnes. Cette solution est de type synchrone. La sortie du comparateur est cette fois revalidée par la logique pour fournir S2 à des instants précis. Les instants de commutation des colonnes de Vc_on à Vc_ofÊ, sont désormais fixés. On peut donc de manière synchrone, éviter que les courants capacitifs associés à cette consommation ne soient intégrés dans la mesure de charges . Dans l'exemple de la figure 12, il suffit de fermer SW2 et d'ouvrir SW3 en synchronisme avec S2 , et ce pour 1 ' ensemble des colonnes . Après un temps minimum nécessaire à "l'évacuation" des courants capacitifs (si la ou les colonnes voisines ont commuté) , on retourne au mode de mesure standard en commutant à SW2 ouvert et SW3 fermé. La fréquence (Fsw) de fonctionnement des interrupteurs SW2 , SW3 , devra être suffisamment rapide pour être compatible avec le nombre de niveaux de gris désirés (Ngris) . On devra respecter la condition suivante : Fsw>Ngrαs . Fιιgne, Figne étant la fréquence d'adressage des lignes de l'écran.FIG. 12 provides another exemplary embodiment of a device for controlling a column with filtering, this time by transistors, parasitic loads due to the inter-column capacities. This solution is of the synchronous type. The comparator output is this time revalidated by logic to supply S2 at specific times. The switching times of the columns from V c _ on to V c _ ofÊ are now fixed. It is therefore possible, synchronously, to prevent the capacitive currents associated with this consumption from being integrated into the measurement of loads. In the example of FIG. 12, it suffices to close SW2 and to open SW3 in synchronism with S2, and this for all the columns. After a minimum time necessary for the "evacuation" of the capacitive currents (if the neighboring column or columns have switched), one returns to the standard measurement mode by switching to SW2 open and SW3 closed. The operating frequency (F sw ) of switches SW2, SW3, must be fast enough to be compatible with the number of gray levels desired (N gr i s ). We must respect the following condition: F sw > N grαs . Fι ιgne, gne Fi being the frequency of addressing lines of the screen.
II) Compenser cette charge Qpar (puisque c'est une charge fixe), ce qui permet de mettre en oeuvre des solutions de type analogique ou numérique en aval de 1 ' intégrateur :II) Compensate this charge Q by (since it is a fixed charge), which makes it possible to implement solutions of analog or digital type downstream of the integrator:
La figure 13 présente un exemple de réalisation d'un dispositif de commande d'une colonne avec compensation analogique des charges parasites dues aux capacités inter-colonnes des colonnes voisines. On voit que, pour une colonne quelconque j, les signaux de commutation, à Vc_0ff/ des colonnes j-1 et j+1 permettent de réajuster, à l'aide d'un additionneur, le niveau de consigne Al d'une quantité Vpar= (Qpar) /Cιnt • De manière évidente, on peut effectuer cette addition de façon numérique en amont du convertisseur numérique analogique CDA.FIG. 13 shows an exemplary embodiment of a device for controlling a column with analog compensation for parasitic loads due to the inter-column capacities of the neighboring columns. It can be seen that, for any column j, the switching signals, at V c _ 0ff / of columns j-1 and j + 1 make it possible to readjust, using an adder, the setpoint level Al d ' a quantity V par = (Q par ) / C ιn t • Obviously, this addition can be carried out digital upstream of the digital to analog converter CDA.
Dans l'exemple de la figure 13, l'additionneur a la référence ADD. Les signaux de commutation des colonnes j-1 et j+1 ont respectivement les références S2j_ι et S2j+ι.In the example in Figure 13, the adder has the reference ADD. The switching signals of columns j-1 and j + 1 have the references S2 j _ι and S2j + ι respectively.
On voit que ces signaux commandent des commutateurs respectifs SWj et SWj+1 qui sont reliés à l'additionneur ADD comme on l'a représenté sur la figure 13.It can be seen that these signals control respective switches SWj and SWj +1 which are connected to the adder ADD as shown in FIG. 13.
On donne ci-après divers avantages apportés par l'invention.Various advantages provided by the invention are given below.
La méthode de commande proposée dans cette invention consiste en résumé en une commande à tension de colonne constante, de type modulation de largeur d'impulsion (PWM pour Puise Width Modulation), largeur contrôlée par la charge émise. Un tel circuit de commande de colonne, dont on vient de donner un exemple de réalisation apporte divers avantages : - une limitation des courants de fuites des colonnes, à ceux de la seule ligne adressée, ce qui, pour un même écran, permet d'obtenir une meilleure qualité d'image en terme d'uniformité,The control method proposed in this invention consists in summary of a command at constant column voltage, of the Pulse Width Modulation (PWM) type, width controlled by the load emitted. Such a column control circuit, an embodiment of which has just been given provides various advantages: - a limitation of the leakage currents of the columns, to those of the single row addressed, which, for the same screen, makes it possible to obtain a better image quality in terms of uniformity,
- une stabilisation sur le temps ligne de ce courant de fuite résiduelle, courant qui devient indépendant de la quantité de charges que l'on veut faire émettre par le pixel considéré,a stabilization over the line time of this residual leakage current, a current which becomes independent of the quantity of charges which it is desired to have emitted by the pixel considered,
- toujours pour ce courant de fuite, son effet dans le circuit intégrateur de courant devient linéaire avec le temps, ce qui pourra simplifier d'éventuelles compensations de ce courant de fuite, - contrairement à la commande en charge de 1 ' art antérieur, ce mode de commande maintient une tension de colonne constante pendant l'émission, ce qui permet de rester au maximum de l'émission du pixel considéré, et donc pour un temps ligne donné, au maximum de brillance,- always for this leakage current, its effect in the current integrator circuit becomes linear over time, which could simplify any compensation for this leakage current, - unlike the command in charge of the prior art, this command mode maintains a constant column voltage during transmission, which makes it possible to stay at the maximum of the emission of the pixel considered, and therefore for a given line time , maximum shine,
- le circuit de commande proposé est « indépendant » des caractéristiques technologiques et dimensionnelles de l'écran - le circuit de commande découple totalement, en ce qui concerne les tensions, les fonctions de mesure de la charge émise (intégrateur plus comparateur) , de celles de l'étage de sortie. On peut par exemple imaginer des fonctions de mesure fonctionnant sous 5 volts, pendant que les potentiels des colonnes commutés par l'étage de sortie valent plusieurs dizaines de volts.- the proposed control circuit is "independent" of the technological and dimensional characteristics of the screen - the control circuit fully decouples, with regard to the voltages, the functions for measuring the charge emitted (integrator plus comparator), from those of the output stage. One can for example imagine measurement functions operating at 5 volts, while the potentials of the columns switched by the output stage are worth several tens of volts.
Les documents qui sont mentionnés dans la présente description sont les suivants :The documents which are mentioned in the present description are the following:
[1] Ecrans fluorescents à micropointes, R. Baptist,[1] Fluorescent microtip screens, R. Baptist,
L'onde électrique, Novembre-décembre 1991, vol.71, n°6, pp 36-42 [2] Fiat panel displays based on surface-conduction électron emitters, K. Sa ai et al., Proceedings of the 16th. international display research conférence, ref.18.3L., pp 569-572 [3] Carbon nanotube FED éléments, S. Uemura et al.,L'onde électrique, November-December 1991, vol.71, n ° 6, pp 36-42 [2] Fiat panel displays based on surface-conduction electron emitters, K. Sa ai et al., Proceedings of the 16th. international display research conference, ref.18.3L., pp 569-572 [3] Carbon nanotube FED elements, S. Uemura et al.,
SID 1998 Digest, pp 1052-1055 [4] Récent progress in field emitter array development for high performance applications, Dorota Temple, Materials science & engineering, vol.R24, n°5, Janvier 1999, pp 185-239 [5] Microtips displays adressing, T. Leroux et al., SID 91 Digest, pp 437-439 [6] FR 2632436 A, Procédé d'adressage d'un écran matriciel fluorescent à micropointes, Invention de J-F Clerc et A. Ghis, correspondant à EP 0345148 A et aussi à US 5138308 A [7] US 5359256 A, Regulatable field emitter device and method of production thereof, H. F. Gray.SID 1998 Digest, pp 1052-1055 [4] Recent progress in field emitter array development for high performance applications, Dorota Temple, Materials science & engineering, vol.R24, n ° 5, January 1999, pp 185-239 [5] Microtips displays addressinging, T. Leroux et al., SID 91 Digest, pp 437-439 [6] FR 2632436 A, Process for addressing a fluorescent microtip matrix screen, Invention of JF Clerc and A. Ghis, corresponding to EP 0345148 A and also to US 5138308 A [7] US 5359256 A, Regulatable field emitter device and method of production thereof, HF Gray.
Revenons sur la présente invention. On connaît des circuits de commande en charge pour faire fonctionner des sources d'électrons, par les documents WO 96 05589 et US 6020804. Ces circuits permettent d'appliquer des tensions sur les lignes et les colonnes d'une source matricielle afin de permettre l'émission des électrons et de mesurer la quantité de charge émise pour la comparer à une valeur de consigne .Let us return to the present invention. Load control circuits for operating electron sources are known from documents WO 96 05589 and US 6020804. These circuits make it possible to apply voltages to the rows and columns of a matrix source in order to allow the 'emission of electrons and measure the quantity of charge emitted to compare it with a set value.
La différence fondamentale entre ces techniques connues et la présente invention tient au fait que, dans ces techniques connues, la mesure de la charge a lieu "côté anode" où s'établit la haute tension (quelques kV) alors que dans l'invention elle est réalisée "côté cathode" c'est-à-dire du côté de la basse tension (quelques dizaines de volts) et, de plus, simultanément avec l'émission.The fundamental difference between these known techniques and the present invention lies in the fact that, in these known techniques, the measurement of the charge takes place "on the anode side" where the high voltage (a few kV) is established, whereas in the invention it is carried out "cathode side", that is to say on the low voltage side (a few tens of volts) and, moreover, simultaneously with the emission.
Or, la mesure de la charge se fait en général sur une résistance et provoque une variation de tension de l'ordre de IV compte tenu des autres grandeurs impliquées. Cette tension de mesure vient perturber le circuit d'alimentation : dans l'art antérieur, la variation de 1 volt par rapport aux kV appliqués provoque une erreur négligeable. Dans l'invention, l'erreur deviendrait très grande (un volt par rapport à quelque dizaines de volts) et absolument inacceptable .However, the measurement of the load is generally made on a resistor and causes a voltage variation of the order of IV taking into account the other quantities involved. This measurement voltage comes disturb the supply circuit: in the prior art, the variation of 1 volt with respect to the applied kV causes a negligible error. In the invention, the error would become very large (one volt relative to a few tens of volts) and absolutely unacceptable.
Les techniques de mesure divulguées dans les documents ci-dessus mentionnés sont donc inexploitables "côté cathode" . Le problème ainsi posé est résolu par la présente invention. The measurement techniques disclosed in the above-mentioned documents are therefore unusable "cathode side". The problem thus posed is resolved by the present invention.

Claims

REVENDICATIONS
1. Procédé de commande d'une source d'électrons à structure matricielle, cette source comprenant au moins une ligne et au moins une colonne d'adressage, dont l'intersection définit une ou des zones émissives appelées pixels et où les électrons sont fournis par la colonne, ce procédé étant un procédé séquentiel, caractérisé en ce que : - dans un premier temps, -on déclenche l'émission des électrons par application de potentiels sur la ligne sélectionnée et la ou les colonnes à une valeur apte à permettre cette émission puis on maintient le potentiel de la ou des colonnes à cette valeur pendant toute la durée de l'émission alors que, simultanément, la mesure de la quantité de charges émises par le ou les pixels respectivement de ladite ou desdites colonnes est assurée dans la ou les colonnes, et - dans un deuxième temps, lorsque la quantité de charges mesurées sur une colonne atteint une quantité de charges requise, on commute le potentiel de cette colonne à une valeur qui assure le blocage de l'émission des électrons. 1. Method for controlling an electron source with a matrix structure, this source comprising at least one line and at least one addressing column, the intersection of which defines one or more emissive zones called pixels and where the electrons are supplied by the column, this process being a sequential process, characterized in that: - firstly, -the emission of electrons is triggered by application of potentials on the selected line and the column (s) at a value capable of enabling this emission then the potential of the column or columns is maintained at this value throughout the duration of the emission while, simultaneously, the measurement of the quantity of charges emitted by the pixel or pixels respectively of said column or columns is ensured in the or the columns, and - in a second step, when the quantity of charges measured on a column reaches a required quantity of charges, the potential of this collar is switched onne a value which ensures the blocking of the emission of electrons.
2. Procédé selon la revendication 1, dans lequel ladite valeur est égale au potentiel de la ou des lignes non-adressées .2. Method according to claim 1, in which said value is equal to the potential of the unaddressed line or lines.
3. Dispositif de commande d'une source d'électrons à structure matricielle, cette source comprenant au moins une ligne et au moins une colonne d'adressage dont chaque intersection définit une zone appelée pixel et où les électrons sont fournis par la colonne, ce dispositif étant caractérisé en ce qu'il comprend :3. Device for controlling an electron source with matrix structure, this source comprising at least one row and at least one addressing column, each intersection of which defines an area called pixel and where the electrons are supplied by the column, this device being characterized in that it comprises:
- des moyens de commande de la ou des lignes d'adressage par application sur la ligne sélectionnée d'un potentiel de sélection, alors qu'hors temps de sélection la ou les lignes restent à un potentiel assurant le blocage de 1 ' émission des pixels correspondants , - des moyens de commande de la ou des colonnes, ces moyens de commande comprenant, pour chaque colonne, des moyens d'application, lors d'une sélection ligne, soit d'une première tension assurant l'émission soit d'une deuxième tension assurant le blocage sur ladite colonne,means for controlling the address line or lines by applying a selection potential to the selected line, while outside the selection time the line or lines remain at a potential ensuring blocking of the emission of the pixels corresponding, - means for controlling the column or columns, these control means comprising, for each column, means of application, during a line selection, either of a first voltage ensuring the emission of either a second tension ensuring blocking on said column,
- des moyens permettant à la fois la mesure, dans la ou les colonnes, de la quantité de charges émise durant l'émission et le maintien constant de la tension assurant l'émission sur ladite colonne pendant cette mesure, etmeans allowing both the measurement, in the column or columns, of the quantity of charges emitted during the emission and the constant maintenance of the voltage ensuring the emission on the said column during this measurement, and
- des moyens de comparaison de la quantité de charges mesurée à une quantité de charges de référence, avec rétroaction sur les moyens de commande des colonnes. means for comparing the quantity of charges measured with a quantity of reference charges, with feedback on the control means of the columns.
4. Dispositif selon la revendication 3, dans lequel la quantité de charge déjà émise est convertie en un niveau de tension.4. Device according to claim 3, in which the quantity of charge already emitted is converted into a voltage level.
5. Dispositif selon la revendication 3, comprenant en outre des moyens de compensation de courants de fuites résiduels. 5. Device according to claim 3, further comprising means for compensating for residual leakage currents.
6. Dispositif selon la revendication 3, comprenant en outre des moyens de compensation de couplages capacitifs inter-colonnes. 6. Device according to claim 3, further comprising means for compensating for inter-column capacitive couplings.
EP01954091A 2000-07-13 2001-07-12 Method and device for controlling a matrix electron source, with regulation by the emitted charge Expired - Lifetime EP1299876B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0009194A FR2811799B1 (en) 2000-07-13 2000-07-13 METHOD AND DEVICE FOR CONTROL OF A SOURCE OF ELECTRONS WITH A MATRIX STRUCTURE, WITH REGULATION BY THE EMITTED CHARGE
FR0009194 2000-07-13
PCT/FR2001/002276 WO2002007139A1 (en) 2000-07-13 2001-07-12 Method and device for controlling a matrix electron source, with regulation by the emitted charge

Publications (2)

Publication Number Publication Date
EP1299876A1 true EP1299876A1 (en) 2003-04-09
EP1299876B1 EP1299876B1 (en) 2009-01-14

Family

ID=8852466

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01954091A Expired - Lifetime EP1299876B1 (en) 2000-07-13 2001-07-12 Method and device for controlling a matrix electron source, with regulation by the emitted charge

Country Status (7)

Country Link
US (1) US7280088B2 (en)
EP (1) EP1299876B1 (en)
JP (1) JP4874500B2 (en)
AT (1) ATE421134T1 (en)
DE (1) DE60137425D1 (en)
FR (1) FR2811799B1 (en)
WO (1) WO2002007139A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002328645A (en) * 2001-05-01 2002-11-15 Canon Inc Image display device and its drive method and circuit
GB0525593D0 (en) 2005-12-16 2006-01-25 Cxr Ltd X-ray tomography inspection systems
US10483077B2 (en) 2003-04-25 2019-11-19 Rapiscan Systems, Inc. X-ray sources having reduced electron scattering
US8243876B2 (en) 2003-04-25 2012-08-14 Rapiscan Systems, Inc. X-ray scanners
JP4504655B2 (en) * 2003-10-15 2010-07-14 日本放送協会 Electron emission device, drive device and display
DE102004003258A1 (en) * 2004-01-21 2005-08-18 GEKKO Gesellschaft für Printrealisierung und Farbstandardisierung mbH Printed matter and process for its production
FR2881270B1 (en) * 2005-01-27 2007-04-20 Commissariat Energie Atomique MICROELECTRONIC DEVICE TRANSMITTING ELECTRONS WITH MULTIPLE BEAMS
US9046465B2 (en) 2011-02-24 2015-06-02 Rapiscan Systems, Inc. Optimization of the source firing pattern for X-ray scanning systems
GB0901338D0 (en) * 2009-01-28 2009-03-11 Cxr Ltd X-Ray tube electron sources
WO2017053958A1 (en) * 2015-09-25 2017-03-30 Tactual Labs Co. Tool to measure the latency of touchscreen devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2632436B1 (en) * 1988-06-01 1991-02-15 Commissariat Energie Atomique METHOD FOR ADDRESSING A MICROPOINT FLUORESCENT MATRIX SCREEN
US5359256A (en) * 1992-07-30 1994-10-25 The United States Of America As Represented By The Secretary Of The Navy Regulatable field emitter device and method of production thereof
JP3251466B2 (en) * 1994-06-13 2002-01-28 キヤノン株式会社 Electron beam generator having a plurality of cold cathode elements, driving method thereof, and image forming apparatus using the same
US6204834B1 (en) * 1994-08-17 2001-03-20 Si Diamond Technology, Inc. System and method for achieving uniform screen brightness within a matrix display
FR2730843B1 (en) * 1995-02-17 1997-05-09 Pixtech Sa ADDRESSING DEVICE OF A MICROPOINT FLAT DISPLAY ELECTRODE
JP3311246B2 (en) * 1995-08-23 2002-08-05 キヤノン株式会社 Electron generating device, image display device, their driving circuit, and driving method
US5867136A (en) * 1995-10-02 1999-02-02 Micron Display Technology, Inc. Column charge coupling method and device
US5952789A (en) * 1997-04-14 1999-09-14 Sarnoff Corporation Active matrix organic light emitting diode (amoled) display pixel structure and data load/illuminate circuit therefor
JP2001209352A (en) * 2000-01-24 2001-08-03 Nec Corp Electrostatic electron emission type display device and its driving method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0207139A1 *

Also Published As

Publication number Publication date
FR2811799B1 (en) 2003-06-13
JP4874500B2 (en) 2012-02-15
US7280088B2 (en) 2007-10-09
FR2811799A1 (en) 2002-01-18
US20040021623A1 (en) 2004-02-05
JP2004504639A (en) 2004-02-12
DE60137425D1 (en) 2009-03-05
EP1299876B1 (en) 2009-01-14
ATE421134T1 (en) 2009-01-15
WO2002007139A1 (en) 2002-01-24

Similar Documents

Publication Publication Date Title
EP0345148B1 (en) Addressing process for a microtip fluorescent display
EP0635819B1 (en) Driving method and apparatus for a microtip display
EP1299876B1 (en) Method and device for controlling a matrix electron source, with regulation by the emitted charge
EP1719102A1 (en) Device for improving pixel addressing
EP1313088A1 (en) Voltage driving method and apparatus for a source of electrons having matrix structure, with regulation of the emitted charge
EP1964094B1 (en) Method for controlling a display panel by capacitive coupling
EP1964095B1 (en) Display panel and control method using transient capacitive coupling
EP0965224B1 (en) Method for controlling a photosensitive device with low image retention, and photosensitive device implementing same
EP1700290B1 (en) Image display screen and method of addressing said screen
EP1771838B1 (en) Image display device and display device control method
EP1697920B1 (en) Device for displaying images on an oled active matrix
CA2539506C (en) Control method for a photosensitive device
EP2372917A1 (en) Device for parallel analogue-to-digital conversion and imaging detector comprising such a device
EP2084698B1 (en) Method of driving a matrix display device having an electron source with reduced capacitive consumption
EP2567245B1 (en) Device for measuring the local electrical resistance of a surface
EP1473755B1 (en) Device and method for controlling a dose of electrons emitted from a microemitter
FR2899991A1 (en) METHOD FOR CONTROLLING A MATRIX VIEWING DEVICE WITH ELECTRON SOURCE
FR3058526A1 (en) DEVICE FOR CHARACTERIZING A POWER DIODE
FR2744275A1 (en) METHOD FOR CONTROLLING A VIEWING PANEL AND VIEWING DEVICE USING THE SAME
EP1147538A1 (en) Method for controlling a structure comprising a source of field emitting electrons
FR2701184A1 (en) First gate blocking circuit.
EP1847979A2 (en) Method of controlling a screen, in particular a plasma screen, and corresponding device.

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20021231

AK Designated contracting states

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17Q First examination report despatched

Effective date: 20040226

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: FRENCH

REF Corresponds to:

Ref document number: 60137425

Country of ref document: DE

Date of ref document: 20090305

Kind code of ref document: P

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090114

NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090425

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090114

REG Reference to a national code

Ref country code: IE

Ref legal event code: FD4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090114

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090615

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090414

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090114

Ref country code: IE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090114

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20091015

BERE Be: lapsed

Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE

Effective date: 20090731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090731

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090731

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090415

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090114

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20090114

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20130709

Year of fee payment: 13

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20130731

Year of fee payment: 13

Ref country code: GB

Payment date: 20130719

Year of fee payment: 13

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20130711

Year of fee payment: 13

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 60137425

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20140712

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20150331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140712

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20150203

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 60137425

Country of ref document: DE

Effective date: 20150203

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140731

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140712