EP1277234A2 - Schaltungsanordnung - Google Patents

Schaltungsanordnung

Info

Publication number
EP1277234A2
EP1277234A2 EP01940172A EP01940172A EP1277234A2 EP 1277234 A2 EP1277234 A2 EP 1277234A2 EP 01940172 A EP01940172 A EP 01940172A EP 01940172 A EP01940172 A EP 01940172A EP 1277234 A2 EP1277234 A2 EP 1277234A2
Authority
EP
European Patent Office
Prior art keywords
circuit arrangement
arrangement according
electronic components
connection
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01940172A
Other languages
German (de)
English (en)
French (fr)
Inventor
Manfred Loddenkoetter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Eupeceuropaeische Gesellschaft Fuerleistungshalbleiter Mbh & Co KG
EUPEC GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eupeceuropaeische Gesellschaft Fuerleistungshalbleiter Mbh & Co KG, EUPEC GmbH filed Critical Eupeceuropaeische Gesellschaft Fuerleistungshalbleiter Mbh & Co KG
Publication of EP1277234A2 publication Critical patent/EP1277234A2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
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    • H01L2924/01005Boron [B]
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    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
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    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01068Erbium [Er]
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    • H01L2924/01074Tungsten [W]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
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    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • H01L2924/13033TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
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    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Definitions

  • the invention relates to a circuit arrangement according to the preamble of claim 1.
  • the electronic components are arranged on a common base substrate and at least partially z. B. connected in pairs and, if necessary, additionally supplied or disposed of with corresponding signals by corresponding further power devices which are designed to supply input signals and / or control signals or to discharge output signals.
  • a possibly multi-component input signal is fed to the circuit arrangement, which input signal is then connected via the interconnection of the electronic components to an output signal to be dissipated via a further line device, optionally also multi-component, is converted.
  • the transformation is based on the one hand on the character of the electronic components, but also through
  • connection device for at least partially pairing contacting of the electronic components is carried out via separate line devices, preferably via wire bonds.
  • This contacting via wire bonds or explicitly provided individual connection devices allows only a limited compact integration of the circuitry of the. electronic components in the circuit arrangement and also prevents a clear tapping of the different electrical potentials occurring within the circuit arrangement for further processing, for example on the outside of a corresponding module housing.
  • the invention has for its object to provide a circuit arrangement of electronic components, in particular a semiconductor module, a power semiconductor module, a matrix converter or the like, in which the arrangement of the circuit is realized in a particularly space-saving and yet reliable and clear manner.
  • a circuit arrangement of electronic components in particular a semiconductor module, power semiconductor module or the like, has a common base substrate on which the electronic components are arranged, a first, second and / or third line device which is used to supply an input signal, to supply a control signal or to
  • the circuit arrangement according to the invention is characterized in that the line devices and / or the connecting device are at least partially provided in each case and / or together as a bus structure on the base substrate.
  • the line devices and / or the connecting device which are necessary for the interconnection of the electronic components and which may consist of several individual lines in each case, are formed in the region of the base substrate, for example a circuit board or printed circuit board, which gives them the corresponding, for example planar, structure of the base substrate is imprinted and they are accordingly compact and space-saving adapted to the structure of the base substrate.
  • the bus structure may have at least some of a plurality of individual line components. This is the form suitable for a plurality of electronic components for interconnection with one another and / or with one another and with further line devices provided.
  • an electrically essentially conductive substrate in particular in the form of surface areas, is formed on the base substrate and if the bus structure is at least partially in each case is designed as a conductive substrate, in particular as surface areas. Electrically conductive surface areas are usually provided on the base substrate in order to Contact tronic components and other electronic components on the surface or the lower surface of the base substrate and / or mechanically position and fasten. According to
  • the bus structure is also designed in the form of conductive surface areas.
  • lines which are provided are at least partially explicit and under certain circumstances also provided if the bus structure is structured in the context of the conductive surface areas on the base substrate.
  • contact devices are provided through which at least some of the electronic components can be contacted with the bus structure and / or with one another or with one another. This ensures that individual line components of the bus structure can also be achieved in any combination of the electronic components. This is all the more important and necessary if one takes into account that unbundling of the circuit is not possible and / or necessary for all circuit combinations.
  • the contact devices can each be designed as an additional line, for example bonded wires.
  • At least some of the electronic components are each designed as, in particular externally controllable, switching devices, in particular with an input connection, an output connection and a control connection. It is advantageous that at least some of the electronic components are designed as a parallel connection of an electronic switch and a diode device.
  • Some of the electronic switches can each be designed as a transistor, as a triac, as a thyristor, namely preferably as an IGBT, or the like.
  • At least some of the electronic switches advantageously have a collector or drain area and an emitter or source area, the collector or
  • Drain area is contacted with a cathode area of the .diode device and the emitter or source area is in each case contacted with anode area of the diode device. In this way, an effective electronic switching element is obtained in a particularly simple manner.
  • At least some of the electronic switches have a base or gate area and that the base or gate area in each case serves as a control connection and can be connected to the second line device, in particular via contact devices. This ensures that the control signals running on the second line device actually control the gate or base area of the electronic switch accordingly.
  • circuit arrangement in a particular embodiment, it is designed as an, in particular externally controllable, matrix converter for converting a plurality of components of the input signal on the first line device into a plurality of components of the output signal on the third line device.
  • matrix converter for converting a plurality of components of the input signal on the first line device into a plurality of components of the output signal on the third line device.
  • the A plurality of switching devices in a predetermined number of pairs are assigned to one another, in particular permanently, and that
  • Switching devices in pairs For example, in the three phases of the input signal and the output signal of a three-phase arrangement, a total of eighteen switching devices are provided, which are arranged in nine predetermined pairs in order to combine each of the three input phases with each of the three output phases.
  • either the emitter or source region or the collector or drain region of the components of a pair of electronic switching devices can be connected to one another via contact devices and / or the connecting device.
  • the individual pairs of switching devices are kept at a common emitter or source potential or at a common collector or drain potential.
  • FIG. 1 shows a schematic block diagram of a first exemplary embodiment of the circuit arrangement according to the invention
  • FIG. 2 shows the implementation of a matrix converter by using a second exemplary embodiment of the circuit arrangement according to the invention
  • FIG. 3A-E in a schematic top view and in sectional side views of an electronic switching device as used in a matrix converter according to the embodiment of FIG. 2;
  • FIG. 4 shows a schematic plan view of a further exemplary embodiment of the circuit arrangement according to the invention.
  • Fig. 5 shows another embodiment of the circuit arrangement according to the invention.
  • FIG. 1 shows in the form of a schematic block diagram a first exemplary embodiment of the circuit arrangement 1 according to the invention, from which the basic bus structure of the arrangement according to the invention emerges.
  • Electronic components 2a and 2b are arranged and fixed on regions 4a of a conductive substrate on a base substrate 3 of the circuit arrangement 1. These electronic components 2a and 2b each have an input connection i, an output connection o and a control connection c.
  • the entirety of the electronic components 2a and 2b is divided into a first subset of components 2a and a second subset of components 2b, which with their output connections o
  • connection device 8 provided on the base substrate 3, for example in the form of a connection bus with several individual line components.
  • the electronic components 2a of the first subset and the electronic components 2b of the second subset are each arranged in a row one after the other, spatially separated by the connecting device 8 and oppose each other in pairs; In this exemplary embodiment, however, this is not intended to imply that the pairs of electronic components 2a and 2b which are in opposition to one another are also connected directly to one another via their output connections o or input connections i. This can be so, but is not absolutely necessary and depends on the respective application.
  • a first line device 5 namely an input bus, is also provided, which carries a possibly multi-component input signal I, which, via the input connections i, via the corresponding contact devices 9, for example in the form of bonding wires, is fed to the electronic components 2a of the first subset.
  • Different electronic components 2a of the first subset can also be supplied with different signal components of the input signal I.
  • This output signal 0 is composed of the contributions to the output 0, of the electronic components 2b of the second sub-assembly whose 'output terminals exceeds o by means of corresponding connecting devices 9, for example in the form of bonding wires, the output bus will be supplied.
  • a second line device 6 is provided for controlling the electronic components 2a and 2b, namely the so-called control bus, which in the exemplary embodiment shown in FIG. 1 is a control bus 6a for the electronic components 2a of the first subset and spatially separated therefrom into one second control bus ⁇ b for the electronic components 2b of the second subset.
  • the control bus 6 or 6a, 6b carries the possibly multi-component control signal C.
  • the bus structure provided in the circuit arrangement 1 according to the invention is thus formed in this case by the parallel individual line devices and connecting devices, namely the individual bus elements 5, 6a, 6b and 7, which are on the base substrate 3 of the circuit arrangement according to the invention as surface areas 4a of the on the base sub - Strat 3 arranged conductive substrate 4 are formed.
  • FIG. 2 shows in the form of a circuit diagram a further exemplary embodiment of the circuit arrangement 1 according to the invention, namely in the form of a so-called matrix converter, in which the input signal I is formed by the individual phases R, S and T, which is then switched off by the corresponding circuit arrangement the phases U, V and W existing output signal 0 is converted.
  • FIG. 2 eighteen identical electronic components 2a and 2b are provided, which are interconnected with nine individual components via a connecting bus 8.
  • the 2 x 9 18 individual electronic components 2a and 2b on the connecting bus 8 just represent the matrix connection of the three input phases R, S and T into the three output phases U, V and W.
  • the eighteen electronic components 2a and 2b are constructed essentially identically, each individual electronic component 2a and 2b being formed from a parallel connection of an IGET 10 with a corresponding diode 12.
  • the anode A of the respective diode 12 is connected to the emitter E of the IGBT 10, whereas the cathode K of the diode 12 is connected to the collector C of the IGBT 10.
  • an electronic component 2a of the first subset namely the upper row of components
  • the connecting device 8 namely the connecting bus
  • control connections of the IGBTs 10 designated here for the sake of simplicity are in principle contacted with a control bus which carries the corresponding control signals.
  • This control bus is not shown graphically in FIG. 2.
  • 3A to 3E show a schematic plan view or partially sectioned side views of an electronic component 2a or 2b arranged on a base substrate 3 and consisting of an IGBT 10 and a diode 12.
  • 3A shows that the IGBT 10 and the diode 12 each have a lower metallization layer 30 and 31, which are each connected to an inner connection of the respective component, on a common surface area 4a of the conductive substrate 4 the base substrate 3 are applied.
  • the metallization region 30 of the IGBT 10 is either conductively connected to the emitter E or to the collector C of the IGBT 10.
  • the metallization region 31 of the diode 12 is connected to either the cathode K or the anode A of the diode 12.
  • the metallization regions 30 of the IGBTs 10 and 31 of the diode 12 are therefore at the same electrical potential.
  • the metallization regions 33 and 34 of the IGBT 10 and the diode 12 are at the same potential, which is conveyed via the first line device 5, namely the input bus, which is also formed as a surface region 4a of the conductive substrate 4 on the base substrate 3 , namely via a corresponding contact device 9, for example a bonding wire.
  • the metallization region 33 of the IGBT 10 is connected to the collector C or to the emitter E of the IGBT 10, while the metallization region 34 of the diode 12 is connected to the cathode K or anode A of the diode 12.
  • the IGBT 10 is controlled via the gate, which is likewise connected to a metallization area 32 and via a corresponding contact device 9 to the control bus 6, which is also designed as a surface area 4a of the conductive substrate 4 on the base substrate 3.
  • 3B to 3E show corresponding cross-sectional side views along the lines BB, CC, DD and EE from Fig. 3A, each in the direction of the arrows. From these cross-sectional views, the layered structure of both the
  • FIGS. 3A to 3E are plan views of two further embodiments of the circuit arrangement 1 according to the invention, specifically with the realization of the matrix converter shown in FIG. 2.
  • the entirety of the eighteen necessary electronic switching devices 2a and 2b is realized by connecting eighteen arrangements, as is essentially shown in FIGS. 3A to 3E.
  • connections for the input phases R, S and T are formed in the upper edge region of the housing 40, where the connections GR1 to GT3 are also provided for the control signals.
  • Components 2a and 2b are arranged in two rows one above the other in the housing 40, the upper row of components 2a representing the first subset and the lower row of components 2b representing the second subset.
  • the input bus 5 that is to say the first line device, is formed piece by piece for each of the phases R, S and T as the surface area 4a of the conductive substrate 4 on the base substrate 3.
  • the piecewise arrangement of the input bus 5 for each of the phases R, S and T namely only where an interconnection and contact with the electronic components 2a is necessary, a considerable space saving and compact design is achieved.
  • control bus 6a is also designed as an arrangement of surface areas 4a of the conductive substrate 4 on the base substrate 3, specifically again in sections for each of the control signals only in the spatial area which is necessary for contacting the respective electronic component 2a.
  • the arrangement of the connecting bus 8 for the respective electronic components 2a and 2b can be seen between the two rows of electronic components 2a of the first subset and electronic components 2b of the second subset.
  • the connecting bus 8 is also designed as an arrangement of surface regions 4a of the conductive substrate 4 on the base substrate 3, the bus 8 in its entirety likewise again being formed only in sections, which results in considerable space savings.
  • control bus 6b likewise in the form of surface regions 4a of the conductive substrate 4 on the base substrate 3, can be seen below the row of electronic components 2b of the second subset.
  • output bus 7, which is also formed in sections and is contacted with corresponding connections for the phases U, V and W in the housing 40.
  • connection bus 8 All individual line components of the bus system formed by the input bus 5, the control bus 6a and 6b and the output bus 7 as well as the connection bus 8 are designed in sections only in the areas as surface areas 4a of the conductive substrate 4 on the base substrate 3, where contact is made with a corresponding connection one electronic component, another bus or a housing connection is necessary.
  • the respective connections are optionally implemented by means of appropriate contacting device 9, in particular in the form of bond wires.
  • FIG. 5 also shows a corresponding circuit for a matrix converter with input phases R, S and T and output phases U, V and W, these phases being able to be supplied or tapped on the left edge or on the right edge of the housing 40 of the matrix converter.
  • the control signals GR1 to GT3 and the control signals GUI to GW3 are fed to the upper and lower edge of the housing.
  • the bus system of the exemplary embodiment of the circuit arrangement according to the invention in FIG. 5 consists exclusively of the combination of input bus 5 and output bus 7.
  • the control signals GR1 to GW3 are supplied by direct contact devices 9, namely bond wires.
  • the connecting bus 8 is formed piece by piece and connects the electronic components 2a and 2b of the first sub-assembly or the second sub-assembly arranged one above the other in pairs via their emitters or collectors, so that the respective opposing electronic components 2a and 2b are electrically connected directly to one another.
  • connections are provided for supplying and / or removing control and / or useful signals. These connections preferably form groups which are geometrically and potentially separated from one another in the circuit arrangement.
  • this preferred embodiment is realized in that the respective connections of the input phases of the matrix converter, namely R, S and T, and the output phases, namely U, V and W, with regard to the input / output Connections and with respect to the control connections are arranged separately in a housing and the corresponding circuit units generating or supplying the potentials are also formed on separate potential islands on the circuit board, namely the carrier 3. So z. B.
  • the input phase connection R and the .Gate control connections GR1, GR2 and GR3 and the emitter control connection E R are a connection group which is separate from the other groups and which can be tapped on the outside of the housing 40.
  • the situation is similar with the connection group GS1, GS2, GS3, E s and S of the second input phase S. The same applies accordingly to the last input phase T and also to the output phases U, V and W of the matrix converter according to the invention.
  • the circuit arrangement of the exemplary embodiment is Fig. 4 is constructed essentially symmetrically or identically.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)
  • Inverter Devices (AREA)
  • Combinations Of Printed Boards (AREA)
EP01940172A 2000-04-20 2001-04-18 Schaltungsanordnung Withdrawn EP1277234A2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10019812A DE10019812B4 (de) 2000-04-20 2000-04-20 Schaltungsanordnung
DE10019812 2000-04-20
PCT/DE2001/001504 WO2001082377A2 (de) 2000-04-20 2001-04-18 Schaltungsanordnung

Publications (1)

Publication Number Publication Date
EP1277234A2 true EP1277234A2 (de) 2003-01-22

Family

ID=7639598

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01940172A Withdrawn EP1277234A2 (de) 2000-04-20 2001-04-18 Schaltungsanordnung

Country Status (5)

Country Link
US (1) US6861741B2 (ja)
EP (1) EP1277234A2 (ja)
JP (1) JP4004796B2 (ja)
DE (1) DE10019812B4 (ja)
WO (1) WO2001082377A2 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004013919A1 (de) * 2004-03-22 2005-10-20 Siemens Ag Elektromotor
WO2011048719A1 (ja) 2009-10-22 2011-04-28 パナソニック株式会社 パワー半導体モジュール
JP6573890B2 (ja) * 2014-01-30 2019-09-11 クリー ファイエットヴィル インコーポレイテッド 薄型で高度に構成可能な電流共有並列化広バンドギャップ電力デバイス電力モジュール
US10553633B2 (en) * 2014-05-30 2020-02-04 Klaus Y.J. Hsu Phototransistor with body-strapped base

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
EP0064856B1 (en) * 1981-05-12 1986-12-30 LUCAS INDUSTRIES public limited company A multi-phase bridge arrangement
US4816984A (en) * 1987-02-06 1989-03-28 Siemens Aktiengesellschaft Bridge arm with transistors and recovery diodes
US5579217A (en) * 1991-07-10 1996-11-26 Kenetech Windpower, Inc. Laminated bus assembly and coupling apparatus for a high power electrical switching converter
EP0584668B1 (de) * 1992-08-26 1996-12-18 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG Leistungshalbleiter-Modul
DE59304797D1 (de) * 1992-08-26 1997-01-30 Eupec Gmbh & Co Kg Leistungshalbleiter-Modul
US5325268A (en) * 1993-01-28 1994-06-28 National Semiconductor Corporation Interconnector for a multi-chip module or package
JP3157362B2 (ja) * 1993-09-03 2001-04-16 株式会社東芝 半導体装置
DE19522173C1 (de) 1995-06-19 1996-10-17 Eupec Gmbh & Co Kg Leistungs-Halbleitermodul
US6281590B1 (en) * 1997-04-09 2001-08-28 Agere Systems Guardian Corp. Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module

Non-Patent Citations (1)

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Title
See references of WO0182377A2 *

Also Published As

Publication number Publication date
DE10019812A1 (de) 2002-01-24
US20030102506A1 (en) 2003-06-05
WO2001082377A3 (de) 2002-05-10
JP4004796B2 (ja) 2007-11-07
WO2001082377A2 (de) 2001-11-01
US6861741B2 (en) 2005-03-01
DE10019812B4 (de) 2008-01-17
JP2003532295A (ja) 2003-10-28

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