Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0202—Addressing of scan or signal lines
  • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
  • G09G2330/02—Details of power systems and of start or stop of display operation
  • G09G2330/021—Power management, e.g. power saving
  • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2360/00—Aspects of the architecture of display systems
  • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

• This invention generally relates to methods of displaying information on liquid crystal display devices.
• the invention further relates to a method of adaptively selecting scanning sequences to reduce the power requirements of passive liquid crystal display devices.
• Liquid crystal displays are used in a variety of devices such as cell phones, pagers, and personal digital assistant devices. Since many of the uses of these displays are in portable, battery operated devices, low power consumption is an important display attribute.
• Many prior art systems, such as LCD displays include circuitry to provide power to the display through row and column electrodes whose overlapping regions form pixels. Information to be displayed is converted into row addressing and column data signals according to one of a variety of techniques. These techniques work within the physical limitations and specifications of the LCD material by providing the appropriate signals to the display electrodes.
• Typical for use in passive LCD displays are multiplexing techniques that are based on the principle that the optical properties of the display respond to average, or R.M.S. signals.
• Common implementations of this technique such as the Alto-Pleshko Technique, use rows signals to select rows for receiving information and the column signals as data signals to carry information to be presented. Variations of this technique have been developed to drive displays using AC to limit DC damage to liquid crystals, and to keep the applied voltages within certain ranges.
• This variation of display technology is exemplified by the Improved Alt and Pleshko Technique (I APT).
• the present invention is directed to lowering the power requirement for driving an LCD display by providing a method and apparatus for scanning the display.
• Prior art display driving techniques have been developed in which the display is scanned row-by-row with fixed, progressive row scanning patterns that do not take advantage of other possible scanning patterns that may have lower power requirements.
• This invention by changing the scanning order to seek out lower power requirements, can decrease the power requirements over those obtained using prior art scanning techniques.
• the display responds to input data by selecting or calculating scanning sequences that have lower power requirements.
• the scanning sequence is fixed in a non-sequential order to provide lower overall power requirements.
• display logic drives the display using a plurality of scan sequences, measures an indication of display power, and selects a best sequence, and drives the display with the best sequence.
• Alternative embodiments include triggering the display logic based on measured power changes, measured changes in display input, or at fixed time intervals or other indications so that the display logic constantly seeks a lower power requirement.
• the present invention allows for providing scanning sequences that are not used in the prior art to lower the display power requirement. This allows for a power reduction by the addition of some circuitry or programming of components, and is compatible with current liquid crystal displays. It is an advantage of the present invention to provide a novel method and apparatus for use with liquid crystal displays such that the displays can be constructed to operate longer on a given amount of energy.
• the present invention provides a novel method and apparatus that provide row scan sequences that scans the display while skipping one or more rows of pixels. It is. an advantage that the present invention provides a novel method and apparatus for providing multiple row scan sequences for driving a display.
• the present invention provides a novel method and apparatus for selecting row scan sequences for driving a display based on the display input. It is an advantage that the present invention provides a novel method and apparatus for controlling the display power of a display by measuring a figure-of-merit indicative of the power required to drive the display.
• the present invention provides a novel method and apparatus that is simple and inexpensive to manufacture and be easy to use.
• FIG. 1 is a top view of a prior art liquid crystal display, defining the pixel geometry and including a schematic of some of the prior art display driving circuitry.
• FIG. 2 shows prior art waveforms used to drive passive liquid crystal display.
• FIG. 3 shows display driving waveforms of the present invention.
• FIG. 4 is block diagram of the display driving hardware illustrating figure-of-merit measurement techniques of the present invention.
• FIG. 5 is a block diagram hardware layout of a first embodiment of the present invention, in which the display input is used to determine the best row scan sequence.
• FIG. 6 is a flowchart of the first embodiment of the present invention, in which the display input is used to determine the best row scan sequence.
• FIG. 7. is a flowchart of the second embodiment of the present invention, in which the row scan sequence is determined before generating the image.
• FIG. 8 is a block diagram combining a hardware layout and a flowchart of a second embodiment of the present invention, in which the row scan sequence is determined before generating the image.
• FIG. 9 is a block diagram combining a hardware layout and a flowchart of the third embodiment of the present invention, in which the selection of the row scan sequence triggered a period counter.
• FIG. 10 is a block diagram combining a hardware layout and a flowchart of the fourth embodiment of the present invention, in which the selection of the row scan sequence triggered by the display input.
• FIG. 11 is a block diagram combining a hardware layout and a flowchart of the fifth embodiment of the present invention, in which the selection of the row scan sequence triggered by changes in the figure-of-merit.
• This invention provides an improved method and apparatus for driving and providing driving signals to liquid crystal displays.
• Display technologies to which this invention pertains include but are not limited to passive LCD, active LCD, electroluminescence, and plasma displays.
• the display power requirements can be reduced over prior art techniques. The power requirements may either be the lowest possible, or as a compromise to other design considerations, the invention may be configured to display information with power requirements that are significantly lower than prior art systems, though not necessarily at the absolutely lowest power.
• FIG. 1 shows a conventional art physical layout of passive liquid crystal displays, and is generally indicative of the type of display to which this invention is directed, particularly in regard to the physical layout and response of the display to input signals.
• the discussion of FIG. 1, while directed to prior art display technology, is not intended to limit the scope of this invention, but provides a description of the configuration and operation of prior art LCDs that are relevant to this invention.
• FIG. 1 is a top view of a liquid crystal display 101 along with display control circuitry comprising a column driver 103, and a row driver 105.
• Display 101 includes a set of M column electrodes 111 and a set of N row electrodes 109 located on opposite sides of the thickness of the display.
• Row electrodes 109 are numbered from 1 to N consecutively from one side of the display to the opposite side, and column electrodes 111 are numbered from 1 to M in a like manner.
• Column electrodes 111 receive M column data signals 115 from column driver 103, while row electrodes 109 receive N row addressing signals 107 from row driver 105.
• Display 101 comprises material that, in conjunction with ancillary components not illustrated, responds in an optically detectable way to potential differences across the display.
• the application of voltages to electrodes 109 and 111 on opposite sides of display 101 produces an image by optically actuating the array of N x M individual pixels 113 formed by the overlapping electrodes.
• Electrodes 109 and 111 are configured so that each pixel 113 is associated with the combination of two electrodes.
• Passive LCD are adapted to respond to time averaged, or R.M.S. signals applied across individual pixels.
• the image is generated on the display by "scanning" across the image by sending appropriate signals to the display.
• the image is scanned by applying row and column signals that produce the optical response necessary to generate the image by optically manipulating individual pixels.
• Each row addressing signal 107 and column data signal 115 varies with time while the display is being scanned to generate with the time varying signal
• These two sets of varying signals will then create the desired voltage differences at intersecting pixel across electrode plates. This pixel voltage difference will modulate the liquid crystal molecule orientation which in turn modulate the incident light and create different shades of reflection or transmission for each pixel.
• These pixels are then resynthesized by the viewers' vision to generate an image.
• one common method for generating the required R.M.S. voltage difference at each pixel is by sequentially applying row addressing signals whose magnitude is used to "select" individual rows, while simultaneously applying column data signals whose magnitude is used to indicate which of the pixels in the selected rows is "on” or “off,” based on the appropriate optical response to the applied voltage.
• the row signals contain scanning order information
• the column signals contain data information regarding the row which is selected.
• Each of the row and column signals vary with time, each row is usually selected once every time the display is scanned, and the R.M.S. voltage across each pixel is driven to some value necessary to produce an optical response to generate an image according to a display technique.
• Information is thus transmitted to the display by scanning the display according to a time sequence of selected rows.
• Column data signals are timed to correspond to the row time sequence, producing the required voltage differences at the intersection of the row and column electrodes. It is useful, particularly for the present invention, to consider the time sequence of selected rows as given by a row scan sequence that can be selected, changed or controlled. It will be shown subsequently that driving a display according to different row scan sequences affects the display power, and that selecting, changing, or controlling the row scan sequence can be used to reduce display power.
• the power required to drive the LCD display is the sum of the power required to drive the row and column electrodes using the row addressing and column data signals. It is typical of many prior art techniques to provide information to the display one or more rows at a time. Row address signals send signals to one or more individual rows, while column data signals supply data pertinent to the pixels corresponding to the selected rows.
• the power consumed in driving the row or column LCD electrodes is directly related to CfV , where C is the load capacitance, /is the toggle count, and P " is the swing voltage, where the swing voltage for any particular electrode is the maximum minus minimum voltage applied to that electrode while displaying an image.
• both C and V will be constant, and therefore a indication of the power to drive any particular row or column will be related to the number of times the voltage on that line changes polarity ("toggles"). Since each of the rows will be scanned exactly once per frame, the row power requirement for row scanning is constant. Since the rate of column toggles depends on the row scan sequence, changing the row scan sequence will be shown subsequently to provide a way of reducing power consumption. More concisely, the column driver power requirement, P co ⁇ , is proportional to the pixel charge, Q, capacitance, C, voltage, V, and average column toggle frequency, f, through:
• Typical values for pixel capacitance and voltage are 2 to 4 pF and 2 to 3 V, respectively, and number of pixels (N x M) are fixed for a given display, with N and M ranging from 30 to 500, and so the total power consumption for a given display unit is proportional to the average column toggle rate/
• the toggle rate is determined by both the image being displayed and by the sequence by which the rows of the LCD display are being scanned. In effect, the image pattern and the row scan sequence will control the column toggle frequency, which is directly proportional to the display power. As described previously, the row scan sequence can thus provide a way to reduce display power.
• FIG. 2 shows a checkerboard pattern displayed using conventional progressive row scanning pattern, having a particularly large power requirement due to the alternating column signals required to generate the pattern with a sequential row scan sequence.
• Row addressing signals 107 are labeled VRj, where i specifies the row number
• the column data signals 115 are labeled VCj, where j specifies the column number.
• Row addressing signals 107 and column data signals 115 vary with time and are synchronized to send display information to each pixel in the display, which in the example shown in FIG. 2 is a constant checkerboard pattern.
• Display information is thus sent to each pixel in this scanning technique by selecting one row at a time while sending display signals to all columns to each pixel in that row.
• IAPT scans the display with two fields per frame, using signals with alternating polarities for alternate fields.
• the row address signals 107 address rows sequentially (in this case from rows 1 to 4), as seen in FIG. 2, while the column data signals 115 includes information on the row being addressed and the display image.
• a row addressing signal of S volts indicates that a row is selected and a signal of 0 volts indicates that the row is not selected, while column data signals of D volts indicate an "off pixel and -D an "on" pixel.
• Frame 2 voltages are inverted from those of Frame 1 so that the average voltage over the two frames will be approximately zero.
• the voltages differences produced by the row and column signals are shown as time varying signals for a representative "on" pixel 201 (Nj 4 ) and "off pixel 203 (N 24 ) on the right side of FIG. 2.
• the on state average voltage is greater that the off state average voltage.
• the checkerboard pattern is among the highest power consuming patterns for a progressive row scan sequence that scans from one end of the display to the other.
• improvements in the display power of a checkerboard pattern is a good indication of the magnitude of power savings that can be gained using this invention.
• the power requirement per frame is given by the 4 row toggles and 16 column toggles.
• FIG. 3 shows the display signals for the present invention when practices on the same physical display 101 and using the same pixel layout and checkerboard pattern as in prior art FIG. 2.
• the FIG. 3 row addressing signals 303 scan the image according to the order row 1, 3, 2, 4.
• Representative "on” pixel 305 and "off pixel 307 signals are also shown on that figure.
• the average voltages in each case are the same as for representative prior art pixels of FIG. 2.
• the checkerboard pattern requires that each frame has 4 row toggles and 4 column toggles.
• the present invention generates the same pattern as the prior art technique with the same number of row toggles but only one quarter of the number of column toggles.
• the present invention reduces the power consumed by column drivers to one quarter of the prior art power consumption.
• the power savings illustrated here are not limited to the addressing scheme illustrated in FIG. 3.
• Other schemes including multiple line addressing scheme (MLA), will also benefit from this invention in which the scanning sequence is examined and selected to minimize power consumed by the display.
• MLA multiple line addressing scheme
• Another application of this invention is the gray shade modulation systems involving the use of frame rate modulation, in which each frame is comprised of an integer number of fields, is scanned to produce gray levels at each pixel location.
• an implementation similar to that described here would be used, with each row scan sequence held long enough to scan through each of field of frames at least twice, allowing all frames to be scanned with both polarities.
• the row scan sequence described in conjunction with FIG. 3 is just one of many row scan sequences that may result in display power savings.
• sequences of interest include, but are not limited to, row scan sequences that scan the display rows by combining sequences that skip multiple numbers of rows, and pseudorandom row progressions. Methods and apparatus for generating these and other progressions, for adaptively changing the row scan sequence to reduce power, and other issues related to implementation of the invention are discussed subsequently.
• similar power savings may be realized with other flat panel display technology where the pixel array is scanned to produce images, and where column drivers experience significant power loss due to the capacitive load present on the column electrode of that particular display architecture. Examples of such displays include AC plasma display panels, and thin film EL based display panels.
• the methods described herein are generally applicable to driving a wide variety of displays.
• pre-determined information is incorporated in a look-up table to generate the best sequence for a given display input.
• an estimate is produced within the display driver indicating which of several available row scan sequences is best, and then using the best sequence.
• Both the first and second embodiments generate images with known or estimated best sequences, and thus realize great display power savings.
• Alternative embodiments cycle through several row scan sequences, generating images with each of the sequences, measuring an indication of the display power, and selecting a sequence that will operate at a lower power. In particular, several row scan sequences are examined as possible lower power consuming sequences, and then the display is driven using a "best" sequence.
• the display circuitry can generate, either through hardware or software, a variety of row scan sequences.
• a figure- of-merit (FOM) indicative of the display power is measured or calculated. Changes in the row scan sequence result in changes in the display power, as described previously, and thus result in a change in the FOM.
• the figure-of-merits are compared, and the row scan sequence corresponding to figure-of-merits meeting a criteria is chosen to drive the display.
• the figure-of-merit may either be a measurement taken off of the display, the display drivers, or may result from calculations based on image pattern properties before the image display is generated.
• each row scan sequence is preferably held long enough for the image to be scanned two or more time, thus enabling a accurate figure-of-merit measurement to be made.
• a third embodiment allows for cycle triggering at set time intervals.
• a fourth embodiment is triggered by changes in display input, and a fifth embodiment is triggered by changes in the indicator of display power.
• a sixth embodiment use a predetermined row scan sequence that is determined to have advantageously low power consumption and is selected a priori for certain intended display applications.
• FIG. 4 represents one such embodiment.
• display 101 receives a display input 431, which is stored in a display data RAM 403. It is understood that all references to display 101 include those display types discussed elsewhere in the specification, claims and figures, as well as any other display type that would operate
• Display input 431 may consist of bit map information to be displayed, or may consist of a string of characters or some other higher level indication to be transformed into bit-mapped display data, including multiple layers of information for color displays.
• Display data 431 is stored in display data RAM 403 and held there for eventually generating column data signals 413.
• a scan sequence generator 437 controls the order in which the rows are to be scanned by generating a row scan sequence 433.
• Row scan sequence 433 is used to provide row 'addressing signals 411 by a decoder 407 that produces a plurality of signals corresponding to each row which is amplified by row driver 409 to produce row addressing signals.
• Row scan sequence 433 also corresponds to the sequence in which display information is read from display data RAM 403, and is used to produce the corresponding column data signals 413. Specifically, row scan sequence 433 is converted to display data RAM , addresses by the RAM address generator 401. These addresses correspond to each of the row and column addresses for display information stored in display data RAM 403.
• row scan sequence 433 is simultaneously used to generate row address signals 411 and to instruct display RAM address generator 401 to generate appropriate address signals to read from data RAM 403.
• Typical CMOS implementation of row and column drivers 409 and 413 comprise of typical CMOS logic, multiplexer, demultiplexer, counter, level shifters, and output driver stages, all of which are well known to those who are skilled in the art of mixed mode CMOS circuit design.
• sequence generator 437 By instructing sequence generator 437, through an input, to generate one of a plurality of row scan sequences 433, display input 431 can be displayed on LCD 101 using the specified row scan sequence. Since display power has been shown to depend on row scan sequence 433, the input to sequence generator 437 can be used to modify or change the display power.
• Prior art scan sequences sequentially scan the pixel rows of display 101, and thus can be represented by the sequence ⁇ 1, 2, ..., N ⁇ , wherein each row is scanned from row 1 to N progressively across the display.
• the sequence ⁇ 1, 3, 5, ... ⁇ followed by ⁇ 2, 4, 6, ... ⁇ can reduce power consumed by column driver by orders of magnitude for displays as small as 100 lines of pixels.
• Other important sequences are those that skip two rows, indicated by ⁇ 1, 4, 7,... ⁇ followed by ⁇ 2, 5, 8, ... ⁇ followed by ⁇ 3, 6, 9, ... ⁇ , pseudorandom sequences, and other sequences that skip rows or are otherwise nonsequential. All of these sequences, are included within the scope of this invention.
• Other important aspects of this invention are the ability to change between row scan sequences, and the ability to power a display with just one of the sequences.
• Some of the many methods and techniques for generating these sequences include: an adder with selectable pre-load and a programmable increment, bit-swapping counter bit order to produce a pseudorandom sequence, and other pseudo random sequence generator techniques commonly known to those skilled in the art of logic circuit design.
• Some embodiments of the present invention use indications of the power consumed by the display in conjunction with control logic to determine optimal row scan sequences.
• the indication of the power consumed by the display is the figure-of-merit 435, which is determined by a figure-of-merit measurement 415.
• the various figure-of-merit measurement techniques are not meant to be limiting to the scope or intent of this invention, and there are other techniques for measuring or obtaining an approximate indication of the power consumed by display 101.
• the row driver power consumption is essentially constant between different row scan sequence since each row is powered the same number of times.
• FIG. 4 Several ways of determining the figure-of-merit based on the column driver 413 power requirement is shown in FIG. 4. In alternative embodiments, some combination of row power and column power could be useful indicators of the power consumption.
• a direct way to generate a figure-of-merit measurement of column power is by monitoring the power or current requirement of column driver 405 directly with meter 417 and then producing a signal proportional to that power or current with column, power or current measurement 423.
• column driver 405 power is controlled through a charge pump 421 and regulator 419.
• a charge pump counter 425 provides another method of measuring the figure-of-merit.
• Yet another way of measuring the figure-of-merit is by monitoring the column signals via a toggle counter 427, which produces an indication of the frequency at which the column data signals 413 are toggled.
• FIGs. 5 and 6 are a first embodiment of a look-up embodiment of the present invention.
• the apparatus of FIG. 5 comprises display logic to drive display 101 with a plurality of row addressing signals 411 and column data signals 413 generated from the display input 431.
• the display logic of this embodiment comprises a look-up table 501, scan sequence generator 437, a RAM address generator 401, a display data RAM 403, a decoder 407, a row driver 409 and a column driver 405.
• Display input 415 may consist of bit map information to be displayed, or may consist of a string of characters or some other higher level symbol to be transformed into bit-mapped display data, possibly including multiple layers of information for color displays.
• Display input 431 is stored in display data RAM 403 and held for eventual use in generating column data signals 413.
• Display input 431 is also provided to a look-up table 501 that determines the lowest power or some other optimal, "best" sequence to use in generating the display input image on display 101.
• the specifics of look-up table 501 depend on the type and number of different displays that are to be generated. Thus, for example, the optimal select row scan sequences may differ between alpha-numeric patterns, graphics pattern, blank displays, or display patterns for games.
• Look-up table 501 may also contain more specific information, for example, which row scan sequences are best for given menus to be displayed, or which are best for combinations of letter and numbers.
• the information in look-up table 501 can either be determined by measurements on similar display units, based on calculated estimates using certain algorithm, or based on statistical analyses which determined a best row scan sequences for a class of display input, or the information may be determined by some other technique.
• Look-up table 501 communicates with scan sequence generator 437 by indicating which sequence is to be generated.
• look-up table 501 and scan sequence generator 437 communicate using a shorthand comprising an index indicating which of several prearranged sequences should be generated by scan sequence generator 437. For example, if it is determined a priori that just three scan sequences will be used for all of the images to be displayed, then the three sequences may be represented by an index that can take values of 1, 2, or 3.
• Look-up table 501 would then analyze the display input 431, lookup the index that corresponds to the best sequence (the best sequence index), pass the index onto sequence generator 437, which would then generate the best sequence corresponding to the best sequence index.
• Alternative embodiments may include the look-up table and the scan sequence generator into a single unit which generates sequences directly in response to the input, eliminating the use of an index.
• Decoder 407 uses the row scan sequence to produce row addressing signals 411. Synchronous with and in accordance with row addressing signals 411 several other components act to produce the appropriate column data signals 413 as was, for example, described previously with respect to the signal scheme of FIG. 3. Specifically, the row scan sequence is used by RAM address generator 401 to produce display RAM addresses corresponding to each addressed row, which is used in turn to produce the appropriate bit- , mapped information to be displayed. This information is transmitted to the column driver 405, which generates column data signals 413. In this way display input 431 is interpreted to produce the best row scan sequence, which is used to drive the rows and columns to generate, the image with a low power requirement.
• FIG. 6 presents a flowchart of the first embodiment.
• the functions of decoder 407, row driver 409, RAM address generator 401, display data RAM 403 and column driver 405 are represented by a decoder/driver function block 605 in FIG. 6.
• the function of look-up table 501 and scan sequence generator 437 are represented by blocks 601 and 603, respectively.
• the flowchart of FIG. 6 highlights the flow of information from the display input 431 to display 101, and in particular points out the use of the display- input to generate sequences for driving the display.
• Second Embodiment Estimating Power Requirements Before Displaying Image Using Available Row Scan Sequences
• FIGs. 7 and 8 show a second embodiment which generates displays with row scan sequences that are determined to provide a low power display operation.
• changes in the row scan sequence change the display power and thus the FOM.
• the second embodiment of the present invention includes a determination of the best row scan sequence by cycling through available sequences, estimating the power requirements through a figure-of-merit of display power, selecting a sequence based on the estimated power, and driving the display only with the selected sequence.
• the row scan sequence is thus chosen from among multiple row scan sequences using circuitry that estimates the power requirement while driving the display with a selected sequence. Similarities. between the second and first embodiments will facilitate this discussion.
• FIGs. 6 and 7 show flowcharts for the first and second embodiments.
• look-up table 601 of the first embodiment is replaced with a series of steps that cycle through a set of S row scan sequences by passing a row sequence identifier or index to sequence generator 603.
• the look-up table 601 of the first embodiment is replaced with a decoder 701, a figure-of-merit estimator 703, a trigger circuit 705, a sequence selector 707, and a sequence generator 709.
• decoder 701 Upon receiving information from display input 431 and the current selected row scan sequence from sequence generator 709, decoder 701 reproduces, approximates, or otherwise generates signals proportional to column address signals that are indicative of what would be sent to the column electrodes of a display.
• Decoder 701 output is used by figure-of-merit estimator 703 to estimate the figure-of-merit by a technique that includes but is not limited to any of the techniques discussed previously. If there is an appreciable change in the figure- of-merit, determined either by changes in value or changes relative to a preset trigger level, a signal is sent to sequence selector 707. Sequence selector 707 then cycles through each of the S row scan sequences, accumulating both sequence index and the corresponding figure- of-merit. After cycling through the sequences, the sequence selector 707 selects the one that has a figure-of-merit corresponding to the lowest power consumption, and this becomes the selected sequence.
• FIG. 8 is a block diagram combining a hardware layout and a flowchart of a second embodiment of the present invention, in which the row scan sequence is determined before generating the image.
• display 101 is driven using display input 431 and the selected row scan sequence.
• the selected row scan sequence is determined by a display data RAM 801, a column driver 803, a figure-of-merit estimator 805, a figure-of- merit driven trigger 807, a row scan sequence generator 809, a scan sequence generator 811, and a RAM address generator 813.
• each of the components 801 - 813 reproduce the functions of their counterparts that generate display signals, they may be different circuits since they are not used to generate display images and thus operate at lower current levels. Alternatively, since there is an overlap of functions, some of the components with similar functions may be combined together and serve dual purposes.
• display data RAM 801 receives information to be displayed and' through the circuitry described in the discussion of FIG. 4, and uses column driver 803 and a figure-of- merit measurement technique in figure-of-merit estimator 805 to determine an estimated figure-of-merit. If the estimated figure-of-merit is deemed by figure-of-merit driven trigger 807 to exceed some pre-established threshold or change, then sequence selector 809 is triggered to cycle through the available row scan sequence. Sequence selector 809 also keeps track of estimated figures-of-merit for each of the row scan sequences, and selects a row scan sequence, passing the appropriate sequence identifier to scan sequence generator 437.
• this embodiment can select a row scan sequence prior to image display.
• One useful figure-of- merit estimator for this embodiment is the average column toggle frequency determined by analyzing the column data signals prior to display of the image.
• function of blocks 811,813, 801, 803 can be served by their corresponding counterpart circuits 437, 401, 403, 405 to reduce the complexity of the circuit, with the penalty of increased power due to the cycling through non-optimized row scan sequences.
• the next three embodiments determine selected row scan sequences by cycling through several row scan sequences, measuring the figure-of-merit, selecting a row scan sequence that fits some criteria, and then driving the display with that sequence.
• cycling occurs while holding the image for two or more frames, enabling a accurate figure-of-merit measurement to be made. Since each row scan sequence may have different power requirements, and some of these power requirements may be greater than the power required by the pre-trigger sequence, cycling through the sequences may draw more power than would have been drawn using the pre-trigger sequence.
• FIG. 9 is a block diagram combining a hardware layout and a flowchart of the third embodiment of the present invention, in which the selection of the row scan sequence triggered a perio counter.
• This implementation incorporates a sequence selector 903 and a period counter 901 into the FIG. 4 display driver.
• Sequence selector 903 passes an index or some other indication of the selected row scan sequence onto scan sequence generator 437. The operation of the display based on the sequence generator output is discussed in detail previously.
• period counter 901 triggers sequence selector 903 to cycle through all row scan sequences of the generator. For most STN LCD displays, a time interval of approximately five seconds between consecutive triggers will produce good results, though the period may differ between display technology and the information which is displayed.
• sequence selector 903 proceeds to instruct the display to generate images with each of the several scan sequences in turn.
• Figure-of-merit measurement 415 is generated for each of the row scan sequences by any appropriate technique.
• the figure-of-merit measurement output is stored in the sequence selector along with the associated indication of the scan sequence (this is shown schematically in FIG. 9 by the circled block labeled "A").
• the sequence selector 903 selects one of the row scan sequences based on the figure-of-merit, thus driving the display with a row scan sequence that is the best among those available to sequence generator 437. As discussed previously, each scan sequence is held long enough to obtain an accurate figure-of-merit determination.
• Fig. 10 is a block diagram combining a hardware layout and a flowchart of the fourth embodiment of the present invention, in which the selection of the row scan sequence triggered by the display input. Specifically, the fourth embodiment responds to changes in the input display to cycle through several row scan sequences while measuring the figure-of- merit for each sequence. A row scan sequence is selected based on predetermined criteria, and the display is driven with the selected row scan sequence.
• sequence selector 903 and an input-driven trigger generator 1001 into the FIG. 4 display driver.
• Sequence selector 903 passes an index or some other indication of the selected row scan sequence onto scan sequence generator 437.
• Input-driven trigger generator 1001 monitors display input 431, and based on changes in the input, triggers sequence selector 903 (through the circled block labeled "E") to cycle through all or some of the available row scan sequences.
• sequence selector 903 once triggered, cycles through row scan sequences, stores measured figures-of-merit, and determines a selected row scan sequence for driving the display until further triggered.
• FIG. 11 is a block diagram combining a hardware layout and a flowchart of the fifth embodiment of the present invention, in which the selection of the row scan sequence triggered by changes in the figure-of-merit. Specifically, the fifth embodiment responds to changes in the measured figure-of-merit to cycle through several row scan sequences while measuring the figure-of-merit for each sequence. A row scan sequence is selected based on predetermined criteria, and the display is driven with the selected row scan sequence.
• FIG. 11 incorporates sequence selector 903 and an figure-of- merit-driven trigger generator 1101 into the FIG. 4 display driver.
• Sequence selector 903 passes an index or some other indication of the selected row scan sequence onto scan sequence generator 701. The operation of the display from based on the sequence generator output is discussed in detail in conjunction with FIG. 4, and in use in a triggered circuit in the discussion of the third embodiment.
• Figure-of-merit-driven trigger generator 1101 monitors the output of figure-of-merit measurement 415, and based on changes in the figure-of-merit, triggers sequence selector 903 to cycle through all or some of the available row scan sequences.
• sequence selector 903 once triggered, cycles through row scan sequences, stores measured figures-of-merit, and determines a selected row scan sequence for driving the display until further triggered.
• a sequence may be pre-selected for the display needs of an entire class of applications.
• This embodiment may be particularly useful for devices such as mobile messaging cell phones, personal digital assistants or pagers.
• the sequence ⁇ 1,3,5, .... ⁇ followed by the sequence ⁇ 2,4,6, .... ⁇ is known, to sharply reduce column driver power consumption for checkerboard pattern (which is often used to simulate gray in 1-bit-per-pixel displays such as STN LCD) and ON-OFF stripes (which is often used to produce on-screen GUI menus) while producing moderate reduction in power consumption for all other display patterns.
• checkerboard pattern which is often used to simulate gray in 1-bit-per-pixel displays such as STN LCD
• ON-OFF stripes which is often used to produce on-screen GUI menus
• Such an embodiment could be incorporated by using a scan sequence generator, such as in FIG.
• nonsequential row scan sequence such as the sequence ⁇ 1,3,5, ... ⁇ followed by the sequence ⁇ 2,4,6, ... ⁇ .
• a series of sequences can be generated by swapping the LSB and MSB of the digital counter .
• a 7-bit counter is used to control a 128-row LCD. Then swapping bit-7 and bit-0 of the counter, a sequence of ⁇ 0,2,4,6, 8, ... ⁇ + ⁇ l,3,5,7,... ⁇ is generated.
• the nonsequential row scan sequence could be built into the decoder and RAM address generator produce the same effect.

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