EP1262997A1 - Löschverfahren einer FAMOS-Speicherzelle und dementsprechende Speicherzelle - Google Patents

Löschverfahren einer FAMOS-Speicherzelle und dementsprechende Speicherzelle Download PDF

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Publication number
EP1262997A1
EP1262997A1 EP02290765A EP02290765A EP1262997A1 EP 1262997 A1 EP1262997 A1 EP 1262997A1 EP 02290765 A EP02290765 A EP 02290765A EP 02290765 A EP02290765 A EP 02290765A EP 1262997 A1 EP1262997 A1 EP 1262997A1
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EP
European Patent Office
Prior art keywords
voltage
source
drain
memory cell
volts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02290765A
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English (en)
French (fr)
Inventor
Richard Fournel
Cirille Dray
Daniel Caspar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
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STMicroelectronics SA
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Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1262997A1 publication Critical patent/EP1262997A1/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors

Definitions

  • the invention relates to integrated circuits, and more particularly memory cells or memory points of the type FAMOS, that is to say based on a FAMOS type transistor.
  • FAMOS technology uses the memory point obtained with a P-type MOS transistor whose single gate is isolated (i.e. not electrically connected).
  • This single grid is therefore floating.
  • This memory point can be obtained without adding steps additional to the basic technological process of manufacturing a P-type MOS transistor Unlike other memory points, by example of FLASH, EPROM or EEPROM type, which include a floating grid and a control grid, the type memory cell FAMOS only has one floating grid.
  • the invention aims to overcome an erasure by UV rays of so that you can program and erase several times and at will a FAMOS type memory cell, i.e. a memory cell comprising a PMOS transistor with a single floating gate, integrated within of an integrated circuit.
  • the invention proposes an erasure electric of a FAMOS type memory cell.
  • the invention therefore goes against the technical prejudices in the domain and thus allows the use of a FAMOS type memory cell as an EEPROM or FLASH type non-volatile memory cell.
  • the memory cell whatever the values of the voltages on the source and on the drain of the PMOS transistor, provided that a voltage on the substrate having a value at least 4 volts higher than the lower the voltage values applied to the source and to the drain.
  • this substrate voltage must remain below a voltage predetermined cell destruction limit.
  • the predetermined limit voltage is the voltage of breakdown of the substrate / source and substrate / drain diodes.
  • this predetermined limit voltage of destruction depends on the technology used. Currently, we set this voltage predetermined limit at approximately 10 volts.
  • a voltage can advantageously be applied to the substrate, the value is at least 6 volts higher than the lowest of voltage applied to the source and the drain.
  • the same voltage can be applied to the source and to the drain.
  • another possibility to reduce the erasure time consists in applying a non-zero and positive voltage difference between the source and the drain.
  • the value of this difference between the source voltage and the drain voltage remains below a predetermined threshold value, so as not to position the memory cell in an intermediate electrical state.
  • variable voltage difference between the source and the drain we could apply at the start of the erasure phase, a positive voltage difference between the source and the drain, so that trigger erasure faster, then we would apply a zero voltage difference between the source and the drain so as to avoid to reach an intermediate electrical state of the memory cell.
  • the electrical erasure of the memory cell according to the invention is achievable whatever the configuration of the PMOS transistor of the memory cell. It is thus possible to provide a PMOS transistor having a classical linear configuration or an annular configuration comprising an electrode in the center, surrounded by the grid, and an electrode peripheral.
  • annular configuration allows, for certain types of process, to make erasing more efficient by reducing time necessary for erasure compared to a linear configuration.
  • the invention also relates to a memory device, comprising a FAMOS type memory cell.
  • the memory cell is electrically erasable.
  • the cell comprises a PMOS transistor made in a semiconductor substrate and the device comprises erasing means capable of applying a voltage on the substrate having a value at least 4 volts higher than the lower of the voltage values applied to the source and to the drain, and lower than a predetermined limit voltage for destruction of the cell.
  • the erasing means are capable of applying a voltage to the substrate whose value is at least 6 volts higher than the lowest of the values of voltage applied to the source and to the drain.
  • the means are advantageously able to apply a difference of non-zero and positive voltage between the source and the drain, while remaining preferably less than a predetermined threshold value, e.g. around 1 volt.
  • the memory device also comprises programming means able to write data in the memory cell, reading means capable of reading the content of the memory cell, and control means able to selectively connect the means of programming, reading and erasing in the memory cell, depending on the operating mode used.
  • the device can include several memory cells of the type Electrically erasable FAMOS, for example a formed memory plane of a matrix of memory cells organized in rows and columns.
  • the invention also relates to an integrated circuit comprising a memory device as defined above.
  • the reference CM designates a memory cell or memory point of the FAMOS type according to the invention.
  • this memory cell comprises a P-type MOS transistor comprising a gate G, a drain region D doped with P + , a source region S also doped with P + .
  • the MOS transistor is produced in an N type CS well, within a P type SB substrate.
  • the transistor of the memory cell CM also includes a socket for substrate B (Bulk in language English) doped N + , which is here a socket outlet.
  • a difference between a FAMOS memory point and a transistor MOS type P classic, is that the only gate of the MOS transistor is in the CM cell not electrically connected. In other words, this grid G is floating. On the other hand, the thickness of gate oxide and the locations can be adjusted to optimize performance of the cell.
  • MPR programming means including a voltage source, apply a voltage of programming VS on the source S and apply a voltage VD on the drain, for example mass.
  • the programming voltage applied to the source is for example equal to 5 volts.
  • the FAMOS transistor When the cell is programmed, the FAMOS transistor is depleted (depleted) and the source-drain current is around 50 to 250 ⁇ A.
  • the source / drain current is of the order of a few nA.
  • MLC reading means deliver the voltage supply VS on the source (for example 3.3 volts) and a voltage VD on the drain, for example equal to 2.3 volts, such that VS-VD is less or equal to 1 volt.
  • the erasure of a FAMOS memory cell is done electrically. More specifically, as illustrated more particularly in FIG. 2, erasing means are provided MEF, also comprising one or more voltage sources, and suitable applying selected voltages to the source, the drain and taking the box. In this regard, in erasure mode, the box socket is no longer connected to the source of the memory cell. In practice, it is provided for example a switch allowing depending on the mode of used operation (programming or erasing) to connect or not together the source and the socket.
  • the MEF erasing means will apply a voltage to the source VS and a voltage on the drain VD.
  • the electrical erasure of the cell is obtained whatever the values of VS and VD, provided that moreover, the MEF means apply a voltage VB to the substrate (socket B) having a value at least 4 higher volts at the lower of the voltage values applied to the source and to the drain.
  • the voltage VB will be chosen at least equal to 4 volts. That said, it would be also possible to apply negative voltages on the source and / or the drain. But in this case, the voltage VB would remain chosen so as to always be greater than the lowest of the applied voltage values on the source and on the drain.
  • the voltage VB to be applied to the socket outlet B must remain however, less than a limit value for destruction of the memory cell. More specifically, here, destruction is synonymous with breakdown of the box / source and / or box / drain diode.
  • this tension of breakdown is of the order of 10 volts and therefore will not exceed hardly 9 volts for the voltage VB.
  • the value of the voltage VB also plays on time erase the memory cell. So the higher this voltage, the shorter the erasing time. As an indication, in the technologies used, we will obtain erasure times of the order of the minute for voltages VB of the order of 7 to 8 volts.
  • Another parameter which acts on the duration of the erasure time is precisely the value of the difference between the voltage VS and the voltage VD. The higher this value, the shorter the erase time.
  • a voltage difference source / drain greater than a predetermined threshold value may lead to positioning the cell at an intermediate electrical state which that is its initial state before the erasure (leading for example to a source / drain current of the order of a few ⁇ A against a few nA for a blank cell).
  • the control device surrounding this memory cell comprises the MEF erasing means, the MPR programming means, MLC reading means and also MCM control means, comprising for example a logic switching, capable of selectively connecting each of these means to the memory cell according to the operating mode used.
  • a diffusion zone is created central 10 and a peripheral diffusion zone 30.
  • the grid 20 in polysilicon is found in the volume delimited by the two diffusions.
  • Field oxide 40 surrounds the peripheral diffusion zone.
  • Ring configuration provides better performance of the memory point according to the invention, as well as concerns data retention only with regard to time erasure.
  • the interfaces 1 and 2 of the field oxide with the grid G in a linear configuration are areas of fragility of the structure due to differences in height between the elements. This will affect the data retention time and the duration erasure.
  • the floating grid 20 (not connected) is confined in a volume inside the area of peripheral diffusion.
  • the grid being confined inside the structure of the FAMOS memory point, there is no longer any interface between the grid and the field oxide.
  • the coupling is then favored gate-source capacitive to the detriment of the gate-drain capacitive coupling, this which allows to obtain a higher gate potential in the phase of programming.
  • programming is faster and the amount of charge injected into the larger grid.
  • the annular configuration reduces the time necessary for erasure.
  • the invention also applies to a configuration annular in which the central electrode is the source and the electrode the drain.
  • the integrated circuit according to the invention can incorporate one or more FAMOS memory cell arrays according to the invention, individually electrically erasable, so as to constitute one or more several memory maps conventionally addressable by lines and by columns and forming electrically non-volatile memories programmable and erasable (FLASH, EEPROM).
  • FAMOS memory cell arrays according to the invention individually electrically erasable, so as to constitute one or more several memory maps conventionally addressable by lines and by columns and forming electrically non-volatile memories programmable and erasable (FLASH, EEPROM).

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
EP02290765A 2001-04-05 2002-03-27 Löschverfahren einer FAMOS-Speicherzelle und dementsprechende Speicherzelle Withdrawn EP1262997A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0104621 2001-04-05
FR0104621A FR2823363B1 (fr) 2001-04-05 2001-04-05 Procede d'effacement d'une cellule-memoire de type famos, et cellule-memoire correspondante

Publications (1)

Publication Number Publication Date
EP1262997A1 true EP1262997A1 (de) 2002-12-04

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EP02290765A Withdrawn EP1262997A1 (de) 2001-04-05 2002-03-27 Löschverfahren einer FAMOS-Speicherzelle und dementsprechende Speicherzelle

Country Status (5)

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US (1) US6667909B2 (de)
EP (1) EP1262997A1 (de)
JP (1) JP2003007877A (de)
CN (1) CN1263117C (de)
FR (1) FR2823363B1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402874B2 (en) * 2005-04-29 2008-07-22 Texas Instruments Incorporated One time programmable EPROM fabrication in STI CMOS technology
US10528769B2 (en) * 2017-07-23 2020-01-07 Albert C. Abnett Method and apparatus for destroying nonvolatile computer memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4185319A (en) * 1978-10-04 1980-01-22 Rca Corp. Non-volatile memory device
EP0778623A2 (de) * 1995-11-14 1997-06-11 Programmable Microelectronics Corporation Durch heisse Elektroneninjektion programmierbare und durch Tunneleffekt löschbare PMOS-Speicherzelle
US6130840A (en) * 1998-04-01 2000-10-10 National Semiconductor Corporation Memory cell having an erasable Frohmann-Bentchkowsky memory transistor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63249375A (ja) * 1987-04-06 1988-10-17 Oki Electric Ind Co Ltd 半導体記憶装置のデ−タ消去方法
US5706227A (en) * 1995-12-07 1998-01-06 Programmable Microelectronics Corporation Double poly split gate PMOS flash memory cell
US6125053A (en) * 1996-07-24 2000-09-26 California Institute Of Technology Semiconductor structure for long-term learning

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4185319A (en) * 1978-10-04 1980-01-22 Rca Corp. Non-volatile memory device
EP0778623A2 (de) * 1995-11-14 1997-06-11 Programmable Microelectronics Corporation Durch heisse Elektroneninjektion programmierbare und durch Tunneleffekt löschbare PMOS-Speicherzelle
US6130840A (en) * 1998-04-01 2000-10-10 National Semiconductor Corporation Memory cell having an erasable Frohmann-Bentchkowsky memory transistor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GIORA YARON ET AL: "E2FAMOS - An electrically erasable reprogrammable charge storage device", IEEE TRANSACTIONS ON ELECTRON DEVICES., vol. 26, no. 11, November 1979 (1979-11-01), IEEE INC. NEW YORK., US, pages 1754 - 1759, XP002187412, ISSN: 0018-9383 *
T-L CHIU ET AL: "Floating gate field effect transistor memory", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 16, no. 2, July 1973 (1973-07-01), IBM CORP. NEW YORK., US, pages 619 - 620, XP002187411, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
FR2823363B1 (fr) 2003-12-12
JP2003007877A (ja) 2003-01-10
FR2823363A1 (fr) 2002-10-11
US6667909B2 (en) 2003-12-23
US20020176289A1 (en) 2002-11-28
CN1388575A (zh) 2003-01-01
CN1263117C (zh) 2006-07-05

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