EP1250638B1 - System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen - Google Patents

System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen Download PDF

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Publication number
EP1250638B1
EP1250638B1 EP01905106A EP01905106A EP1250638B1 EP 1250638 B1 EP1250638 B1 EP 1250638B1 EP 01905106 A EP01905106 A EP 01905106A EP 01905106 A EP01905106 A EP 01905106A EP 1250638 B1 EP1250638 B1 EP 1250638B1
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Prior art keywords
clock signal
signal
clock
delay
rising edge
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English (en)
French (fr)
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EP1250638A2 (de
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Christian A. J. Lutkemeyer
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Broadcom Corp
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Broadcom Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/002—Specific input/output arrangements not covered by G06F3/01 - G06F3/16
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Definitions

  • the present invention relates generally to electronic circuits and, more particularly, to efficient clock domain partitioning and clock delay matching.
  • circuit designers are continually developing communication circuits and microprocessors that can send and process data, respectively, at faster and faster rates.
  • signals will be sent between these high-power and low-power circuits.
  • the two circuits will be driven by clock signals derived from the common system clock signal.
  • These derived clock signals are generated by circuit components that operate at the respective supply voltage. That is, clock signals for the high-power circuits (the high power domain) are generated by circuit components that operate at the high supply voltage.
  • Clock signals for the low-power circuits are generated by circuit components that operate at the low supply voltage.
  • the circuit components that generate the clock signals induce a delay in signals that pass through them.
  • the delay of a given circuit component depends, in general, on the supply voltage.
  • supply voltages may deviate from their nominal values by certain tolerances, for example, +/-10%.
  • the clocks that drive the circuit components that operate at different supply voltages may be delayed in time relative to one another.
  • this delay in time may vary over time as the supply voltages deviate within their operating tolerances.
  • the misalignment of the clock signals in the different domains due to this delay may result in clock uncertainty. This, in turn, may reduce the available cycle time of the circuit because the clock uncertainty has to be compensated by asynchronous delays when a signal is exchanged between the two domains within one clock cycle. As a result, it may be impossible to double latch the signals. In sum, this misalignment of the clock signals may corrupt data being processed by the circuit.
  • US-A-5 572 557 is directed to the problem that the data signal transfers in conventional digital signal processing systems cannot be carried out correctly because of clock skew due to variation in wiring length, circuit load and/or dispersion in electrical characteristics of different chips.
  • the chips fluctuate in delay time from the input of a clock signal to the output of their data signal and fluctuate in set up hold time from the input of a data signal, and as a result, the data signal transfers between two chips tends to be carried out incorrectly.
  • said data signal transfers are difficult to carry out when the clock signal is high in frequency.
  • US-A-5 572 557 discloses a semiconductor integrated circuit device which can transfer its data signal correctly to another device in response to a clock signal even if the clock signal is high in frequency, by providing the semiconductor integrated circuit device including a phase locked loop (PLL) circuit.
  • the PLL circuit receives an input clock signal and produces an output clock signal having a constant phase shift or change relative to the input clock signal.
  • the PLL circuit according to US-A-5 572 557 has phase-shifting means for providing a phase shift or change to the input clock signal to make the output clock signal, and a phase comparator for comparing in phase the input clock signal and the output clock signal and for supplying a control signal to the phase comparator based on the result of comparison.
  • the phase-shifting means is controlled so that the phase shift is kept constant by the control signal.
  • the PLL circuit provides the output clock signal having a constant phase shift or change relative to the input clock signal.
  • the data signal stored in one of the registers can be correctly transferred to another register even if the clock skew arises and the input clock signal has a high frequency.
  • US-A-5 900 752 discloses a circuit and method for deskewing signals by using cross power supply logic paths to compensate for delays created by power supplies operating at different voltages.
  • a first replica circuit operating at a first supply voltage is placed in series with a first signal operating at a second supply voltage.
  • a second replica circuit operating at the second supply voltage is placed in series with a second signal having a skew difference from the first signal and operating at the first supply voltage.
  • the replica circuits generally have a scale factor which is generally a fraction of the equivalent driver circuits associated with the particular output signals, and as a result, arbitrary power supply differences are deskewed.
  • the replica and true circuits provide the same delay. Thereby, the sum of the delays for all the blocks in each path will be constant which maintains a desired skew difference between the output signals.
  • the invention is directed to systems and methods for providing signals (e.g., clock signals) to circuits driven by different supply voltages.
  • signals e.g., clock signals
  • the signals for the circuits driven by the different supply voltages are delayed, as necessary, to reduce the phase difference (i.e., delay) between the signals.
  • One embodiment of a system constructed according to the invention incorporates a buffer with an adjustable delay to reduce the delay mismatch between clock signals driven by clock trees associated with each supply voltage.
  • a phase detector circuit compares the clock phases for rising and falling edges of the clock signals for each supply voltage.
  • the phase detector circuit controls bias voltages that, in turn, control the delay of the adjustable-delay buffer. Thus, one of the signals is delayed until its delay effectively matches the delay of the other signal.
  • the circuits in this embodiment may directly compare signals that have different signal levels (e.g., voltage level and voltage swing).
  • signal levels e.g., voltage level and voltage swing.
  • teachings of the invention may be incorporated to provide very effective circuits for compensating for delay mismatches between different signals.
  • Figure 18 is a simplified block diagram of one embodiment of a trellis decoder circuit incorporated in the integrated circuit of Figure 17 .
  • FIG. 1 is a block diagram of one embodiment of a system S utilizing clock delay compensation in accordance with the present invention.
  • the system S incorporates a timing circuit 20 that includes a signal comparator 22 (e.g., a phase comparator)and a delay adjuster circuit 24 for reducing phase mismatches between clocks 26 and 28 that drive circuit A 30 and circuit B 32, respectively.
  • a signal comparator 22 e.g., a phase comparator
  • a delay adjuster circuit 24 for reducing phase mismatches between clocks 26 and 28 that drive circuit A 30 and circuit B 32, respectively.
  • the system of Figure 1 typically is implemented in an integrated circuit where multiple supply voltages are used to reduce the power dissipation of the integrated circuit. In this case, less timing-critical parts operate on a lower supply voltage than timing-critical parts of the circuit
  • each of the circuits 30 and 32 is powered by a different supply voltage (V DDH 34 and V DDL 36).
  • V DDH 34 and V DDL 36 a different supply voltage
  • a single power supply or more than one power supply 38 may be used to generate supply voltages 34 and 36.
  • the circuits 30 and 32 may be driven by different clock signals 26 and 28.
  • clock trees are used to buffer a master clock signal to provide clock signals with sufficient current drive to the circuits.
  • the master clock signal drives two clock trees, one buffer tree in the high voltage domain, and the other buffer tree in the low voltage domain.
  • a clock tree 40 generates the clock signals 26. As shown in Figure 1 , the clock tree 40 is powered by supply voltage V DDH 34 so that the clock signals 26 have the appropriate signal level (e.g., voltage level and swing) for circuit A 30. In this embodiment, the clock signal is generated by a master clock 44 that is powered by supply voltage V DDH 34.
  • a clock tree 42 generates the clock signals 28.
  • the clock tree 42 is powered by supply voltage V DDL 36 so that the clock signals 28 have the appropriate signal level (e.g., voltage level and swing) for circuit B 32.
  • a level adjuster 46 is provided to shift the level of the clock signal generated by the master clock 44 to a level compatible with circuits powered by supply voltage V DDL 36.
  • FIG. 2 illustrates one implementation of the clock trees 40 and 42. As represented in Figure 2 , both clock trees are driven by a common clock signal designated phi. Clock tree 40 generates a set of clock signals designated phi H . Clock tree 42 generates a set of clock signals designated phi L . Clock tree 40 has a supply voltage V DDH of 2.5 volts. Clock tree 42 has a supply voltage V DDL of 1.8 volts. Either of these supply voltages may vary by +/-10% due to temperature and other variants.
  • Figure 3 illustrates how the clock signal phi may be delayed as it passes through each of the components in a clock tree.
  • the schematic at the top of Figure 3 represents one embodiment of a branch of the clock tree 42 along with the level adjuster 46.
  • Each branch of the clock tree includes several buffers, the number of which will depend, in part, on the number of branches required for the clock tree and the current drive capability of the buffers.
  • the level adjuster 46 converts the signal level of the clock signal from the 2.5 volt range to the 1.8 volt range.
  • the chart immediately below the schematic in Figure 3 illustrates delay characteristics of the clock tree 42 and the level adjuster 46.
  • the symbols SS, TT and FF represent simulations at the slow slow, typical typical and fast fast corners, respectively (e.g., worst case, typical case and best case scenarios).
  • Each row in the chart sets forth the delays (in nanoseconds, nS)for a given part of the branch.
  • nS the delays (in nanoseconds, nS)for a given part of the branch.
  • the dispersed buffer cell 50 has a delay of 0.26 nS.
  • the level adjuster 46, nor gate 52, inverter 54 and buffer 56 have a total delay of 1.02 nS.
  • the nor gate 58, inverter 60 and buffer 62 have a total delay of 0.72 nS.
  • the total delay for the branch is 2.00 nS.
  • the delay of these buffers is supply voltage dependent.
  • the delays of the buffers may change.
  • Figure 4 depicts exemplary timing diagrams for the three clock signals, phi, phi H and phi L .
  • the circuit may be designed so that phi H and phi L are delayed by approximately the same amount of time, ⁇ Ht and ⁇ Lt , respectively.
  • one of the supply voltages changes (e.g., V DDH decreases by 10%)
  • the delay though the corresponding buffer tree e.g., buffer tree 40
  • This situation is indicated graphically in Figure 4 as edges of the clock signal moving in time either to the left or right.
  • the supply voltages may change independently of each other.
  • the clock trees are nominally designed to have the same delay, under normal operating conditions the actual delay of the clock trees may be mismatched by several hundred picoseconds. This may occur, for example, when one supply voltage is at its maximum value and the other is at its minimum value. Under these worst case conditions the edges of the clock signal might move in time either to the left or right by the maximum amounts indicated in Figure 4 (e.g.,, ⁇ Ht +12%/-8%; ⁇ Lt +21%/-14%). In the example of Figure 4 , this may cause ⁇ 800 picoseconds of phase shift between phi H and phi L as indicated by the filled portions 70 of the timing diagrams.
  • circuits 30 and 32 typically send signals to one another (e.g., when a register in circuit A 30 sends a signal to a register in circuit B 32). Depending upon the particular application, these signals may be referenced to the master clock 44. Given that the amount of the delay through the clock trees 40 and 42 may be dependent on supply voltage, it is possible that there will be a phase difference (mismatch) between these clock signals.
  • phase difference could have an adverse effect on data transfers between the two circuits.
  • the phase difference typically would reduce the cycle time for circuit operations. That is, the circuits will have to be designed to provide more delay in the system timing between operations than would otherwise be required. This in turn would decrease the speed at which the circuits could operate.
  • this mismatch may lead to race conditions between registers that are clocked by clock signals 26 and 28.
  • this phase mismatch may be corrected by varying the delay of one of the clock signals (e.g., phi H ) to compensate for the phase mismatch between the clock signals.
  • This delay is regulated to keep the phase difference between the two clock signals as close to zero as possible.
  • Figure 1 describes one embodiment of such a circuit.
  • a signal comparator 22 e.g., a phase detector
  • the signal comparator 22 sends compensation signals to the delay adjuster 24 to increase or decrease the delay of clock signal to clock tree 40.
  • a reference clock signal phi 76 is used to generate clock signals phi H 78 and phi L 80.
  • the clock signal phi L 80 is generated from phi 76 via a level shift and via buffers that comprise the phi L clock tree (not shown).
  • the clock signal phi H 78 is generated from phi 76 via an adjustable delay buffer 82 and via buffers 84 and 86 that comprise the phi H clock tree.
  • Phase detectors 88 and 90 compare phi H 78 and phi L 80 and generate signals that control the delay of adjustable delay buffer 82.
  • FIG. 6 is a schematic diagram of one embodiment of the adjustable delay buffer 82 implemented in CMOS circuitry.
  • the adjustable delay buffer has input “i” and output “o” and is controlled by bias voltages V BIaSP and V BIASN that affect the charging and discharging current to an intermediate node of the adjustable delay buffer 82.
  • MOS transistors P4104 and N 1 106 form a basic inverter for buffering and inverting input 'i' 108 to generate 'ob' 110.
  • Signal 'ob' 110 is inverted to produce the non-inverted output 'o' of the adjustable delay buffer.
  • PMOS transistors P 1112, P2114 and P3116 control current flow for the rise time of the basic inverter.
  • P2114 supplies a constant current because it is always ON with a grounded gate, thus defining the maximum rise time for 'ob' 110 when P 1 112 and P3 116 are both off.
  • P 1 112 is either OFF or ON depending on the state of the "resetb" signal and, when ON, provides an intermediate supply current to the inverter.
  • the circuit is designed so that the current supplied when P1 112 and P2 114 are both on is in the middle of the regulation window that is covered by the adjustable delay buffer 82.
  • P3 116 provides an adjustable current to the inverter depending on the value of V BIASP .
  • the ON and OFF states of P1112 and P3 116 are mutually exclusive.
  • Transistors N2 118, N3 120 and N4 122 operate in a similar way for controlling current flow for the falling edge of 'ob' 110.
  • N3 120 sinks a constant current because it is always ON with its gate tied to a high voltage thereby defining the maximum fall time for 'ob' 110 when N2 118 and N4122 are both off.
  • N2 118 is either OFF or ON depending on the state of the "reset" signal (the compliment of resetb) and, when ON, provides an intermediate sinking current for the inverter.
  • the circuit is designed so that the current sunk when N2118 and N3 120 are both ON is in the middle of the regulation window that is covered by the adjustable delay buffer 82.
  • N4 122 sinks an adjustable current to the inverter depending on the value of V BIASN .
  • the ON and OFF states of N2 118 and N4 122 are mutually exclusive.
  • the adjustable delay buffer may be set to a maximum delay state or to a fixed intermediate delay state.
  • the transistors P 1 112 and N2 118 are dimensioned so that under typical operating conditions, the buffer provides enough delay so that the output of the two clock trees are aligned in phase.
  • Adjustable delay is provided by varying V BIASP and V BIASN . As these signals are varied, the rise time and fall time of the inverter is varied resulting in a variable delay between 'i' 108 and 'ob' 110.
  • Figure 7 is a graph representative of delay adjustments for the adjustable delay buffer 82 of Figure 6 .
  • the vertical axis represents the rise times and fall times at "ob" 110.
  • the horizontal axis represents the bias voltages V BIASP and V BIASN .
  • V TN is the threshold voltage of an NFET.
  • V TP is the threshold voltage of a PFET. In this example, the reset signals are inactive.
  • Curve tf(ob) 126 corresponds to V BIASN .
  • V BIASN is below V TN then the buffer 82 provides a constant delay for the falling edge because transistor N4 122 is off.
  • V BIASN increases to values above V TN N4122 turns on thereby providing more sink current for N 1106. As a result, the fall time of node "ob" 110 decreases.
  • Curve tr(ob) 128 corresponds to V BIASP .
  • V BIASP When V BIASP is above V DD - V TP then the buffer 82 provides a constant delay for the rising edge because transistor P3 116 is off. As V BIASP decreases to values below V DD - V TP P3 116 turns on thereby providing more source current for P4 104. As a result, the rise time of node "ob" 110 decreases.
  • Figures 8A - 8D depict simulation results for the delays under typical conditions.
  • Figure 8A illustrates the delay for the rising edge.
  • Figure 8B illustrates the delay sensitivity (i.e., the gradient of the delay curve: gradient delay over gradient bias voltage) for the rising edge.
  • Figure 8C illustrates the delay for the falling edge.
  • Figure 8D illustrates the delay sensitivity for the falling edge.
  • the phi signal 76 is fed through the adjustable delay buffer 82 and then through buffers 84 and 86 to generate phi H 78.
  • the signal phi H 78 is used to clock the two phase detectors PDTF1 88 (clocked on the falling edge of phi H ) and PDTR2 90 (clocked on the rising edge of phi H ).
  • the signal phi L 80 is used as the data signal to both of the phase detectors PDTF 1 88 and PDTR2 90.
  • the phase detector for the falling edge, PDTF 188 generates a control signal (early) which is one of two inputs to a nand gate 140.
  • the resetb signal is the other input to the nand gate 140.
  • the digital output of nand gate 140 is fed to a low pass filter (consisting of R1 142 and C 1 144) to generate the V BIASP signal as an analog value.
  • the output of the nand gate 140 may remain high for a few clock cycles. This will cause V BIASP to rise slowly.
  • the phase detector 88 detects that the falling edge of clock signal phi H is no longer earlier than the input signal phi L the phase detector 88 switches the early signal to its opposite value. At this point, the output of the nand gate 140 will go low. When this happens, V BIASP will fall slowly. Thus, the value of V BIASP will vary back and forth in relatively small intervals.
  • the nand gate 140 functions to keep the ON and OFF state of the transistors P112 and P3 116 in Figure 6 mutually exclusive.
  • V BIASN is generated in a similar fashion using the rising edge phase detector PDTR2 90 to control a nor gate 146 and the low pass filter consisting of resistor R2148 and capacitor C2150.
  • the phase detector for the rising edge, PDTR2 90 generates a control signal (late) which is one of two inputs to nor gate 146.
  • the resetb signal is the other input to the nor gate 146.
  • the digital output of NOR gate 146 is fed to a low pass filter (consisting of R2 148 and C2150) to generate the V BIASN signal as an analog value.
  • the output of the nor gate 146 may remain high for a few clock cycles. This will cause V BIASN to rise slowly.
  • the phase detector 90 detects that the rising edge clock signal phi H is no longer later than the input signal phi L the phase detector 90 switches the late signal to its opposite value. At this point, the output of the nor gate 146 will go low. When this happens, V BIASN will fall slowly. Thus, the value of V BIASN will vary back and forth in relatively small intervals.
  • the nor gate 146 functions to keep the ON and OFF state of the transistors N2118 and N4 122 in Figure 6 mutually exclusive.
  • FIGS 9 and 10 are circuit diagrams of one embodiment of the phase detectors 90 and 88 for the rising edge and the falling edge, respectively.
  • this register circuit generates the late signal when phi H rises before phi L .
  • Transistors P2 154 and N1 156 and transistors P3 158 and N2160 form the sampling latch in the register.
  • Transistor N3 163 is used to latch the state of the clock signal phi L when phi H is rising.
  • the complementary latch outputs q 164 and qn 166 will be at a 1 or a 0 state, respectively.
  • Switch transistors 168 and 170 and the two inverters 172 and 174 form the output latch in the register. Because the latch is pre-charged, the pre-charge state could potentially become the output. To avoid this, the output (qn) 166 is latched into the output latch to generate the "late" signal. When the latch is precharging, the connection through the output latch is, in effect, broken so that the output latch stores the value of the previous evaluation by the sampling latch, not the precharge value.
  • the inverter 176 is used to provide the same load on output q 164 as is present on output qn 166.
  • this register circuit generates the early signal when phi L falls before phi H .
  • Transistors P2180 and N2182 and transistors P3184 and N3 186 form the sampling latch in the register.
  • Transistor P1 189 is used to latch the state of phi L when phi H is falling.
  • the complementary latch outputs q 192 and qn 194 will be at a 1 or a 0 state, respectively.
  • Switch transistors 196 and 198 and the two inverters 200 and 202 form the output latch in the register for reasons similar to those discussed above in conjunction with Figure 9 .
  • inverter 204 is used to provide the same load on output q 192 as is present on output qn 194.
  • Figure 11 shows an exemplary implementation for the low pass filters R1 142 and C 1 144 and R2148 and C2150, using CMOS technology. That is, the circuits on the right side of Figure 11 are the CMOS implementations of the RC circuits depicted on the left side of Figure 11 .
  • Figure 12 depicts a delay measurement ( ⁇ H ) for an exemplary analog DLL where there is a mismatch between the delay for phi H and phi L .
  • the accuracy with which the analog DLL can match ⁇ H to ⁇ L depends on a variety of factors including, for example, circuit characteristics, operating condition and manufacturing tolerances. In general, while the goal is to obtain a perfect match at all times between ⁇ H and ⁇ L , in practice this match will be somewhat less than exact.
  • Figures 13A - 13E show simulation results for different states of an exemplary analog DLL.
  • Figure 13A depicts a buffer mismatch (the values of ⁇ H for several corner conditions) when reset is set to a "1.”
  • Figure 13B depicts a buffer mismatch when reset is set to a "0.”
  • Figure 13C depicts buffer mismatch hysteresis for several corner conditions when reset is set to a "0.”
  • FIG 14 this figure describes an example useful to understand embodiments of the invention wherein a digital delay locked loop (“DLL”) is used to compensate for the phase variations of two clocks, phi H and phi L .
  • DLL digital delay locked loop
  • several delay elements e.g., buffers 210, 212, 2.14, 216 and 218, are used to generate delayed versions of the input clock signal phi.
  • a delay selector comprising selector switch 222 and counter 1 230 selects the one delayed clock signal that provides the best match to the desired phase of the output clock.
  • selector switch 222 controls the delay of phi H to match the phase of phi L by selecting a version of the clock signal phi that has passed through as few as none (switch 222 connects output lead 234 to input lead 236) and as many as five (switch 222 connects output lead 234 to input lead 238) of the buffers 210 - 218.
  • Flip-flop DFF 1 224 performs the function of a phase detector.
  • Flop-flops DFF2 226 and DFF3 228 are signal stabilizers that help resolve meta stability conditions that exist due to the circuit driving DFF1 224 so that phi H clocks the DFF1 224 when phi L is in transition.
  • Counter1 230 controls the position of the selector switch 222 based on the phase difference between phi H and phi L .
  • Counter2 232 is, in effect, a low pass filter that reduces jitter in the circuit so that the jitter does not effect the position of the selector switch 222.
  • each transition of the clock signal output is a phase measurement and this results in a high or low output by DFF3 228 that feeds to counter1 230 through the low pass filter (counter2 232).
  • the output of DFF3 228 will toggle thereby setting counter2 232 to alternate between counting up and counting down.
  • the output of counter2 will not saturate in either the high or low direction.
  • counter1 230 will not change the position of the selector switch 222.
  • counter2 232 may eventually saturate (high or low) at some defined value which will cause counter1 230 to change the position of the selector switch 222.
  • the minimum resolution of this digital delay lock loop is limited to the delay of one buffer. In practice, this resolution may be too large to provide adequate delay compensation in certain circuits.
  • FIG. 15 is a block diagram of an example of a circuit for implementing a variable delay in a digital scheme.
  • the circuit of Figure 15 could replace the buffers 210 - 218 and the selector switch 222 of Figure 14 .
  • the delay in this circuit is controlled by selecting the path of the input signal phi though delay elements consisting of multiplexors ("Muxs") 240, 242, 244 and 246 and inverters 248, 250,252, 254 and 256.
  • Muxs 240, 242, 244 and 246 may, in general, be selected by the output of counter1 in Figure 14 (e.g., using a thermometer code).
  • the next shortest signal path through this structure is through Mux0 240.
  • the next selection has a delay that results from propagation through inverter 248, Mux1 242 and Mux0 240. Therefore, incremental delays can be added by going one step to the right through an additional inverter and the corresponding Mux delay.
  • the advantage of this structure is that the select switch does not have to be balanced as it typically would be in the embodiment of Figure 14 . When the signal is switched from one path to the next path, only an inverter and a Mux delay are added.
  • the digital delay locked loop has several advantages over the analog delay locked loop.
  • the digital circuits may be easier to implement than the analog circuits because a digital circuit may be constructed using gates from a standard cell library.
  • the parameters of the digital circuit are relatively stable; whereas the parameters of, for example, the low pass filter in the analog circuit may change depending on the process corner of the chip, the particular lot of the chip and operating conditions such as temperature and supply voltage.
  • the minimum resolution of the digital circuit typically is limited to the delay of a Mux plus an inverter.
  • the delay is quantized to approximately 0.35 nS.
  • the delay is slightly longer than the one buffer delay described in conjunction with Figure 14 .
  • the phase error between phi H and phi L is approximately +/-400 picoseconds ("pS") with changes in VDD of +/-10%.
  • the phase error is approximately +/-200 pS with changes in VDD of +/-5%.
  • the resolution of the embodiments of the digital DLL described above is not small enough to provide effective delay compensation in this case.
  • it is important to select delay components that have sufficiently small delay e.g., appreciably smaller than the maximum phase error between phi H and phi L .
  • a comparison of the analog DLL and the digital DLLs described above illustrate that the analog DLL may be preferable to the digital DLL in many circumstances.
  • an analog DLL that aligns the rising and falling edges is preferable to a digital design that aligns only one edge (e.g., the rising edge).
  • Clock jitter e.g., ⁇ hyst
  • the clock jitter was approximately 0.35 nS.
  • delay is quantized (e.g., 0.35 nS) while the analog DLL can, in effect, continuously track changes in the delay.
  • the digital DLL may consume more power than the analog DLL due to switching activity that may occur in digital DLL implementations. In sum, the analog DLL may provide better performance at a lower cost.
  • a circuit constructed according to the invention is implemented as an integrated circuit-based bidirectional communication system.
  • the present invention may be characterized as a system and method for accommodating efficient, high speed decoding of signal samples encoded according to the trellis code specified in the IEEE 802.3ab standard (also termed 1000BASE-T standard).
  • the physical implementation of this embodiment is a gigabit ethernet transceiver chip 266 that is installed on a transceiver circuit board 268.
  • the decoder circuitry portions of transceiver demodulation blocks require a multiplicity of operational steps to be taken in order to effectively decode each symbol.
  • transceiver chip 266 may use multiple supply voltages to reduce the power dissipation of the integrated circuit.
  • Figure 17 is a simplified block diagram of the functional architecture and internal construction of the transceiver chip 266 and other portions of the transceiver board 268.
  • circuits such as echo canceller 260 and near-end crosstalk ("NEXT") cancellers 262 may be operated at a lower supply voltage than some of the other circuits in the transceiver chip. In this case, a lower supply voltage powers the components that generate the clock signals for clocking the Echo/NEXT cancellers.
  • a clock circuit (not shown) may incorporate phase compensation to reduce phase mismatches between the clocks sent to the echo cancellers 260 and the NEXT cancellers 262 and the clocks sent to other circuits in the transceiver chip 266.
  • FIG 18 is a simplified block diagram of some of the trellis decode functionality from decode block 270 in the transceiver chip 266.
  • the decode functionality includes a decision feedback equalizer 264 ("DFE") that may be operated at a lower supply voltage than some of the other circuits in the transceiver chip 266. In this case, a lower supply voltage powers the components that generate the clock signals for clocking the DFE 264.
  • the timing recovery circuit 258 may incorporate phase compensation to reduce phase mismatches between the clocks sent to the DFE 264 and the clocks sent to other circuits in the transceiver chip 266.
  • the invention described herein provides an effective technique for compensating for phase mismatches that may occur as a result of variations in power supply outputs. While certain exemplary embodiments have been described in detail and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive of the broad invention. It will thus be recognized that various modifications may be made to the illustrated and other embodiments of the invention described above, without departing from the broad inventive scope thereof.
  • circuits may be used to implement analog DLLs in accordance with the invention.
  • the invention may be embodied in many different forms, for example, in virtually any type of integrated circuit. That is, the teachings of the invention are not limited to any particular integrated circuit function or structure. Moreover, such an integrated circuit could be used in a variety of devices such as transceiver boards 268 in personal computers, network interface cards and network infrastructure switches. It should be understood by one skilled in the art, given the teachings of the invention, that the operating characteristics of the analog and digital DLLs will depend, for example, on circuit parameters and operating conditions.
  • circuits that incorporate any number of supply voltages and signals (e.g., clock signals).
  • a third clock tree and level shifter could be used to supply the clock signals to a third circuit (e.g., circuit C, not shown).
  • another delay adjust circuit could be used in circuit B or C.
  • the signal comparator also would compare the output of the third clock tree to control the delay adjust circuits so that the clocks for all three of the circuits are closely synchronized.

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  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
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Claims (15)

  1. System (S) zur Kompensation von Phasendifferenzen zwischen einer Vielzahl von Taktsignalen in einem elektronischen Schaltkreis, wobei die Vielzahl von Taktsignalen mit einer Vielzahl von Signalspannungspegeln (34, 36) assoziiert ist, mit:
    a) wenigstens einem Phasenkomparator (22) zum Vergleichen einer Phase eines ersten Taktsignals (26), das mit einem ersten Signalspannungspegel assoziiert ist, mit einer Phase eines zweiten Taktsignals (28), das mit einem zweiten Signalspannungspegel assoziiert ist, und zum Erzeugen wenigstens eines Kompensationssignals, das eine Phasendifferenz zwischen dem ersten Taktsignal (26) und dem zweiten Taktsignal (28) angibt;
    b) wenigstens einer Verzögerungseinstellvorrichtung (24), die mit dem wenigstens einen Phasenkomparator (22) gekoppelt ist und auf das wenigstens eine Kompensationssignal anspricht, zum Verzögern des ersten Taktsignals (26) zur Kompensation der Phasendifferenz zwischen dem ersten Taktsignal (26) und dem zweiten Taktsignal (28);
    dadurch gekennzeichnet, dass
    c) die wenigstens eine Verzögerungseinstellvorrichtung (24) wenigstens einen einstellbaren Verzögerungspuffer (56) umfasst; und wobei
    d) der wenigstens eine Phasenkomparator Folgendes umfasst:
    e) einen ansteigende Flanke-Phasenkomparator (90) zum Vergleichen einer ansteigenden Flanke des ersten Taktsignals (26) mit einer ansteigenden Flanke des zweiten Taktsignals (28) zum Erzeugen wenigstens eines ansteigende Flanke-Kompensationssignals, das eine Phasendifferenz zwischen der ansteigenden Flanke des ersten Taktsignals (26) und der ansteigenden Flanke des zweiten Taktsignals (28) angibt;
    f) einen abfallende Flanke-Phasenkomparator (88) zum Vergleichen einer abfallenden Flanke des ersten Taktsignals (26) mit einer abfallenden Flanke des zweiten Taktsignals (28) zum Erzeugen wenigstens eines abfallende Flanke-Kompensationssignals, das eine Phasendifferenz zwischen der abfallenden Flanke des ersten Taktsignals (26) und der abfallenden Flanke des zweiten Taktsignals (28) angibt; und
    g) wobei der wenigstens eine einstellbare Verzögerungspuffer (56) : die ansteigende Flanke des ersten Taktsignals (26) im Ansprechen auf das ansteigende Flanke-Kompensationssignal verzögert; und die abfallende Flanke des ersten Taktsignals (26) im Ansprechen auf das abfallende Flanke-Kompensationssignal verzögert.
  2. System nach Anspruch 1, wobei der wenigstens eine einstellbare Verzögerungspuffer (56, 82) Folgendes umfasst:
    wenigstens einen Puffer-Transistor (62) zum Puffern des ersten Taktsignals (26); und
    wenigstens einen Steuer-Transistor, der auf das wenigstens eine Kompensationssignal anspricht, zum Einstellen des Stromflusses durch den wenigstens einen Puffer-Transistor (62), um die Verzögerung des ersten Taktsignals (26) durch den wenigstens einen Puffer-Transistor (62) zu steuern.
  3. System nach Anspruch 1, das des Weiteren eine Vielzahl von Puffern zum Erzeugen des ersten und des zweiten Taktsignals (26, 28) umfasst.
  4. System nach Anspruch 3, wobei die Vielzahl von Puffern eine Vielzahl von Taktbäumen (40, 42) umfasst.
  5. System nach Anspruch 4, das des Weiteren wenigstens eine Stromversorgung für die Bereitstellung einer Vielzahl von Versorgungsspannungen umfasst, die mit der Vielzahl von Signalspannungspegeln assoziiert ist.
  6. System nach Anspruch 1, wobei das erste Taktsignal (26) und das zweite Taktsignal (28) von einem gemeinsamen Taktsignal (76) abgeleitet werden.
  7. System nach Anspruch 1, das des Weiteren eine Pegeleinstellvorrichtung (46) zum Modifizieren eines Signalspannungspegels eines Signals umfasst, um das erste Taktsignal (26) zu erzeugen, das mit dem ersten Signalspannungspegel assoziiert ist, der sich von dem zweiten Signalspannungspegel unterscheidet, der mit dem zweiten Taktsignal (28) assoziiert ist.
  8. System nach Anspruch 7, wobei das System Teil eines integrierten Schaltkreises ist.
  9. System nach Anspruch 8, wobei der integrierte Schaltkreis einen Gigabit Ethernet Transceiver umfasst.
  10. System nach Anspruch 9, wobei das erste Taktsignal (26) mit wenigstens einem von einem Nahnebensprechen-Kompensator, einem Echokompensator und einem entscheidungsrückgekoppelten Entzerrer assoziiert ist.
  11. System nach Anspruch 1, wobei der einstellbare Verzögerungspuffer (82) Folgendes umfasst:
    wenigstens einen ansteigende Flanke-Steuer-Transistor, der auf das ansteigende Flanke-Kompensationssignal anspricht, um den Stromfluss durch den wenigstens einen Puffer-Transistor (62) einzustellen, um die Verzögerung der ansteigenden Flanke des ersten Taktsignals (26) durch den wenigstens einen Puffer-Transistor (62) zu steuern; und
    wenigstens einen abfallende Flanke-Steuer-Transistor, der auf das abfallende Flanke-Kompensationssignal anspricht, um den Stromfluss durch den wenigstens einen Puffer-Transistor (62) einzustellen, um die Verzögerung der abfallenden Flanke des ersten Taktsignals (26) durch den wenigstens einen Puffer-Transistor (62) zu steuern.
  12. System nach Anspruch 11, wobei:
    der ansteigende Flanke-Phasenkomparator ein Register zum Bestimmen umfasst, ob die ansteigende Flanke des ersten Taktsignals (26) der ansteigenden Flanke des zweiten Taktsignals (28) voreilt; und
    der abfallende Flanke-Phasenkomparator ein Register zum Bestimmen umfasst, ob die abfallende Flanke des zweiten Taktsignals (28) der abfallenden Flanke des ersten Taktsignals (26) voreilt.
  13. System nach Anspruch 12, das des Weiteren eine Vielzahl von Tiefpassfiltern (142, 144) zum Filtern des ansteigende Flanke-Kompensationssignals und des abfallende Flanke-Kompensationssignals umfasst.
  14. Verfahren zur Kompensation von Phasendifferenzen zwischen einer Vielzahl von Signalen, die mit einer Vielzahl von Signalspannungspegeln assoziiert ist, wobei das Verfahren die folgenden Schritte umfasst:
    Erzeugen eines ersten Taktsignals (26), das mit einem ersten Signalspannungspegel assoziiert ist;
    Erzeugen eines zweiten Taktsignals (28), das mit einem zweiten Signalspannungspegel assoziiert ist;
    Vergleichen einer Phase des ersten Taktsignals (26) mit einer Phase des zweiten Taktsignals (28), um wenigstens ein Kompensationssignal zu erzeugen, das eine Phasendifferenz zwischen dem ersten Taktsignal (26) und dem zweiten Taktsignal (28) angibt;
    Verzögern des ersten Taktsignals (26), um die Phasendifferenz zwischen dem ersten Taktsignal (26) und dem zweiten Taktsignal (28) zu kompensieren;
    dadurch gekennzeichnet, dass der Vergleichsschritt des Weiteren die folgenden Schritte umfasst:
    Vergleichen einer ansteigenden Flanke des ersten Taktsignals (26) mit einer ansteigenden Flanke des zweiten Taktsignals (28), um wenigstens ein ansteigende Flanke-Kompensationssignal zu erzeugen, das eine Phasendifferenz zwischen der ansteigenden Flanke des ersten Taktsignals (26) und der ansteigenden Flanke des zweiten Taktsignals (28) angibt; und
    Vergleichen einer abfallenden Flanke des ersten Taktsignals (26) mit einer abfallenden Flanke des zweiten Taktsignals (28), um wenigstens ein abfallende Flanke-Kompensationssignal zu erzeugen, das eine Phasendifferenz zwischen der abfallenden Flanke des ersten Taktsignals (26) und der abfallenden Flanke des zweiten Taktsignals (28) angibt; Verzögern der ansteigenden Flanke des ersten Taktsignals (26) im Ansprechen auf das ansteigende Flanke-Kompensationssignal; und
    Verzögern der abfallenden Flanke des ersten Taktsignals (26) im Ansprechen auf das abfallende Flanke-Kompensationssignal.
  15. Verfahren nach Anspruch 14, das des Weiteren die Schritte des Erzeugens des ersten Taktsignals (26) und des zweiten Taktsignals (28) mit einer Vielzahl von Taktbäumen (40, 42) umfasst.
EP01905106A 2000-01-24 2001-01-24 System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen Expired - Lifetime EP1250638B1 (de)

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Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1250638B1 (de) * 2000-01-24 2008-07-16 Broadcom Corporation System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen
US6968026B1 (en) * 2000-06-01 2005-11-22 Micron Technology, Inc. Method and apparatus for output data synchronization with system clock in DDR
US6792582B1 (en) * 2000-11-15 2004-09-14 International Business Machines Corporation Concurrent logical and physical construction of voltage islands for mixed supply voltage designs
JP4717233B2 (ja) * 2001-03-14 2011-07-06 ルネサスエレクトロニクス株式会社 クロック供給バイアス回路及びそれを用いた単相クロック駆動分周回路
CA2383527A1 (en) * 2001-04-25 2002-10-25 Homak Manufacturing Co., Inc. Medical cart with electronically lockable pharmaceutical and narcotic drawers
JP3502618B2 (ja) * 2001-07-19 2004-03-02 松下電器産業株式会社 位相同期ループ回路、及びデータ再生装置
US6618283B2 (en) * 2001-08-29 2003-09-09 Micron Technology, Inc. System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal
US7079615B2 (en) * 2001-11-20 2006-07-18 Hewlett-Packard Development Company, L.P. Expanded comparator for control of digital delay lines in a delay locked loop or phase locked loop
US6934922B1 (en) 2002-02-27 2005-08-23 Xilinx, Inc. Timing performance analysis
US6982500B2 (en) * 2002-03-11 2006-01-03 Intel Corporation Power-down scheme for an on-die voltage differentiator design
US7102402B2 (en) * 2002-05-23 2006-09-05 Intel Corporation Circuit to manage and lower clock inaccuracies of integrated circuits
US6897699B1 (en) * 2002-07-19 2005-05-24 Rambus Inc. Clock distribution network with process, supply-voltage, and temperature compensation
US7136799B2 (en) * 2003-03-21 2006-11-14 Sun Microsystems, Inc. Mixed signal delay locked loop characterization engine
JP4413516B2 (ja) * 2003-03-31 2010-02-10 シャープ株式会社 信号タイミング調整システムおよび信号タイミング調整量設定プログラム
JP4325261B2 (ja) * 2003-04-17 2009-09-02 ソニー株式会社 電子機器および半導体集積回路の制御方法
US20090044357A1 (en) * 2007-08-16 2009-02-19 The Procter & Gamble Company Electric toothbrushes
US7313176B1 (en) * 2003-09-11 2007-12-25 Xilinx, Inc. Programmable on chip regulators with bypass
US7284143B2 (en) * 2003-12-29 2007-10-16 Texas Instruments Incorporated System and method for reducing clock skew
US7075285B2 (en) * 2004-05-12 2006-07-11 Richard Chin Delay locked loop circuit and method for testing the operability of the circuit
US7984398B1 (en) * 2004-07-19 2011-07-19 Synopsys, Inc. Automated multiple voltage/power state design process and chip description system
US7227402B2 (en) * 2004-08-23 2007-06-05 Micron Technology, Inc. System and method for controlling input buffer biasing current
US7518424B2 (en) * 2004-11-08 2009-04-14 Elite Semiconductor Memory Technology Inc. Slew rate controlled output circuit
US7180353B2 (en) * 2005-02-03 2007-02-20 Mediatek Incorporation Apparatus and method for low power clock distribution
US7251798B2 (en) * 2005-02-25 2007-07-31 Verigy (Singapore) Pte. Ltd. Method and apparatus for quantifying the timing error induced by crosstalk between signal paths
US7536663B2 (en) * 2005-02-25 2009-05-19 Verigy (Singapore) Pte. Ltd. Method and apparatus for quantifying the timing error induced by an impedance variation of a signal path
US7581131B1 (en) * 2005-05-09 2009-08-25 National Semiconductor Corporation Method and system for balancing clock trees in a multi-voltage synchronous digital environment
US8258845B1 (en) * 2005-05-20 2012-09-04 Xilinx, Inc. Clock auto-phasing for reduced jitter
US7571406B2 (en) * 2005-08-04 2009-08-04 Freescale Semiconductor, Inc. Clock tree adjustable buffer
US7609799B2 (en) * 2005-09-02 2009-10-27 Cypress Semiconductor Corporation Circuit, system, and method for multiplexing signals with reduced jitter
US7627839B1 (en) * 2005-11-14 2009-12-01 National Semiconductor Corporation Process corner indicator and estimation circuit
KR100763843B1 (ko) * 2005-11-23 2007-10-05 삼성전자주식회사 소스 드라이버 및 상기 소스 드라이버를 구비하는디스플레이 장치
US7486130B2 (en) * 2005-12-14 2009-02-03 Ember Corporation Clock skew compensation
US20080174353A1 (en) * 2007-01-18 2008-07-24 John Thomas Badar Path delay adjustment circuitry using programmable driver
WO2008114416A1 (ja) * 2007-03-20 2008-09-25 Fujitsu Limited 電源電圧調整装置、記録媒体および電源電圧調整方法
JP4861256B2 (ja) * 2007-06-15 2012-01-25 株式会社東芝 Ｄｌｌ回路
WO2009001652A1 (ja) * 2007-06-18 2008-12-31 Nagasaki University, National University Corporation タイミング発生回路および位相シフト回路
US8205182B1 (en) 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
EP2193604A1 (de) * 2007-09-28 2010-06-09 Agere Systems, Inc. Phasenregelkreis (pll) mit vergrössertem tracking-bereich
US8032778B2 (en) * 2008-03-19 2011-10-04 Micron Technology, Inc. Clock distribution apparatus, systems, and methods
JP5384910B2 (ja) * 2008-11-11 2014-01-08 ルネサスエレクトロニクス株式会社 半導体集積回路及びクロック同期化制御方法
US7969219B2 (en) * 2008-11-26 2011-06-28 Texas Instruments Incorporated Wide range delay cell
US9143129B2 (en) * 2009-09-17 2015-09-22 Broadcom Corporation Low power, accurate reference-free threshold detector
JP5657902B2 (ja) * 2010-03-17 2015-01-21 株式会社コスモステクニカルセンター ポリオキシアルキレンステロールエーテル誘導体及び／又はポリオキシアルキレンスタノールエーテル誘導体、及びそれを含有する外用剤組成物
WO2014172252A1 (en) * 2013-04-15 2014-10-23 Kent State University Patterned liquid crystal alignment using ink-jet printed nanoparticles and use thereof to produce patterned, electro-optically addressable devices; ink-jet printable compositions
US9419589B2 (en) * 2013-08-16 2016-08-16 Apple Inc. Power source for clock distribution network
TWI561958B (en) 2014-05-22 2016-12-11 Global Unichip Corp Integrated circuit
US10419005B2 (en) * 2016-12-14 2019-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Phase-locked-loop architecture
KR20210073299A (ko) * 2019-12-10 2021-06-18 삼성전자주식회사 클록 데이터 복원 회로 및 이를 포함하는 장치
KR20220098854A (ko) 2021-01-05 2022-07-12 에스케이하이닉스 주식회사 지연 변동을 보상하는 반도체 장치 및 이를 포함하는 클록 전달 회로
US11334110B1 (en) * 2021-02-01 2022-05-17 Cadence Design Systems, Inc. Systems and methods for communicating clock signals

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4496861A (en) * 1982-12-06 1985-01-29 Intel Corporation Integrated circuit synchronous delay line
US4604582A (en) * 1985-01-04 1986-08-05 Lockheed Electronics Company, Inc. Digital phase correlator
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
US4755704A (en) * 1987-06-30 1988-07-05 Unisys Corporation Automatic clock de-skewing apparatus
US5173617A (en) * 1988-06-27 1992-12-22 Motorola, Inc. Digital phase lock clock generator without local oscillator
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
US5079519A (en) * 1991-02-14 1992-01-07 Notorola, Inc. Digital phase lock loop for a gate array
US5218314A (en) * 1992-05-29 1993-06-08 National Semiconductor Corporation High resolution, multi-frequency digital phase-locked loop
US5355037A (en) * 1992-06-15 1994-10-11 Texas Instruments Incorporated High performance digital phase locked loop
US5828257A (en) * 1995-09-08 1998-10-27 International Business Machines Corporation Precision time interval division with digital phase delay lines
US5838179A (en) * 1996-07-03 1998-11-17 General Signal Corporation Clock compensation circuit
US5900752A (en) 1997-01-24 1999-05-04 Cypress Semiconductor Corp. Circuit and method for deskewing variable supply signal paths
KR100215889B1 (ko) * 1997-05-06 1999-08-16 구본준 클럭 동기 회로
KR100237567B1 (ko) * 1997-05-07 2000-01-15 김영환 지연잠금 회로
EP1250638B1 (de) * 2000-01-24 2008-07-16 Broadcom Corporation System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen

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US20010049812A1 (en) 2001-12-06
WO2001053916A8 (en) 2001-10-04
US6690216B2 (en) 2004-02-10
US6879196B2 (en) 2005-04-12
DE60134830D1 (de) 2008-08-28
US20020089362A1 (en) 2002-07-11
US6636091B2 (en) 2003-10-21
EP1250638A2 (de) 2002-10-23
US6501311B2 (en) 2002-12-31
AU2001233023A1 (en) 2001-07-31
US6693475B2 (en) 2004-02-17
US20040145397A1 (en) 2004-07-29
US7049868B2 (en) 2006-05-23
WO2001053916A3 (en) 2002-05-02
WO2001053916A2 (en) 2001-07-26
ATE401597T1 (de) 2008-08-15
US20020093367A1 (en) 2002-07-18
US20040025075A1 (en) 2004-02-05

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