EP1221096A1 - Method and apparatus for modifying microinstructions in a static memory device - Google Patents
Method and apparatus for modifying microinstructions in a static memory deviceInfo
- Publication number
- EP1221096A1 EP1221096A1 EP00963557A EP00963557A EP1221096A1 EP 1221096 A1 EP1221096 A1 EP 1221096A1 EP 00963557 A EP00963557 A EP 00963557A EP 00963557 A EP00963557 A EP 00963557A EP 1221096 A1 EP1221096 A1 EP 1221096A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory device
- jump point
- address
- microinstructions
- microinstruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/66—Updates of program code stored in read-only memory [ROM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
Definitions
- the present invention relates to the field of control stores for microprocessors. More particularly, the invention relates to the modification of a control store apparatus that utilizes both a Read-Only Memory (ROM) and a Random Access Memory (RAM).
- ROM Read-Only Memory
- RAM Random Access Memory
- Control stores contain executable microinstructions that control the data path of a microprocessor.
- the control store consists of RAM, in others, the control store is ROM.
- the contents of a RAM can easily be rewritten with new information.
- RAM is volatile, i.e., the contents of RAM are retained only during the time period when power is supplied to the circuit.
- the contents of a ROM are inserted at the time of the ROM's manufacture and cannot be changed or erased, even when powered off.
- an error in one portion of the code can be isolated and corrected without having to rewrite the entire code.
- a programmer will create a duplicate subroutine, without the errors, which is called by the program flow instead of the faulty subroutine.
- This technique is possible by utilizing system RAM and ROM together for storing the microinstruction set.
- Subroutines are generally stored in ROM, whereas the main program code that calls the subroutines is generally stored in RAM.
- exit points from the main code allow the program flow to execute the microinstructions of the subroutines in ROM.
- a jump point register is used to hold a jump point address. This jump point address can trigger an interrupt event in the program flow.
- a program counter contains the address of the current microinstruction in the program flow. If the program counter holds an address that equals the jump point address in the jump point register, the interrupt event is generated. This interrupt event initiates an alteration in the program flow from a static memory device to a programmable memory device.
- FIG. 1 is a diagram showing a conventional program flow between RAM and ROM.
- the present practice among those skilled in the art is to debug faulty subroutines by duplicating the entire subroutine in RAM 100, absent programming errors, and reprogramming the RAM 100 to carry the program flow to the duplicated subroutine in RAM 100, rather than to the faulty subroutine stored in ROM 110.
- a programming error 106 is discovered in subroutine 105, then the programmer would have to disable the data path 103 from RAM 100 to ROM 110 and create a new data path 104 to a replacement subroutine 107 residing in RAM 100.
- the data path 108 flows back to any designated microinstruction located in RAM 100 after the disabled data path 103.
- Control line 304 carries the contents of the program counter to the comparators 308, 318, 328.
- the program counter is a register that contains the address of the microinstruction to be executed next. In some data processing systems, the program counter is designed to contain the current microinstruction being executed. It would be apparent to one skilled in the art that the contents of the program counter need not be limited to a predictive state or a current state in order to implement any embodiment of the invention.
- FIG. 4 is a block diagram showing a data processing system. It will be apparent to one skilled in the art that the present invention may be practiced without specific details as to well-known circuits and control logic. In order to avoid obscuring the description, such specific details have been omitted from FIG. 4.
- the block diagram of FIG. 4 is representative of a system wherein the control logic is segregated from the operation core.
- the system may be a digital signal processor or an application specific integrated circuit.
- the present invention can be used in data processing systems with other architectural forms, e.g., where the control logic is combined with the operation core.
- a program flow control device 400 is coupled to the control store RAM 430, the control store ROM 440, an interrupt circuit 450, and an instruction- decoding device 410.
- the interrupt circuit 450 may be the interrupt circuit of FIG. 3.
- the program flow control device 400 generates the contents of the program counter, generates the flags which show whether the current instruction has been executed or canceled, and handles all external events such as direct memory access (DMA) and interrupts.
- the instruction-decoding device 410 may or may not be integrated within the operation core 420 and is connected to the program flow control device 400 through line 405.
- the instruction-decoding device 410 is also connected to the control store RAM 430 and control store ROM 440 through line 404.
- interrupt circuit 450 When interrupt circuit 450 indicates that the current program counter contains an address equal to a jump point address contained in a jump point register (not shown), an interrupt is generated by an interrupt controller (not shown), which may or may not be integrated into the program flow control device 400. When the interrupt circuit 450 generates an interrupt, the program flow control device 400 resets the program counter to hold the address of the next microinstruction specified by the interrupt event.
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Stored Programmes (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39891299A | 1999-09-14 | 1999-09-14 | |
US398912 | 1999-09-14 | ||
PCT/US2000/025474 WO2001020453A1 (en) | 1999-09-14 | 2000-09-14 | Method and apparatus for modifying microinstructions in a static memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1221096A1 true EP1221096A1 (en) | 2002-07-10 |
Family
ID=23577324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00963557A Withdrawn EP1221096A1 (en) | 1999-09-14 | 2000-09-14 | Method and apparatus for modifying microinstructions in a static memory device |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1221096A1 (en) |
JP (1) | JP2003509769A (en) |
KR (1) | KR20020029921A (en) |
CN (1) | CN1373872A (en) |
AU (1) | AU7495300A (en) |
WO (1) | WO2001020453A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7464248B2 (en) | 2005-04-25 | 2008-12-09 | Mediatek Incorporation | Microprocessor systems and bus address translation methods |
CN103268237A (en) * | 2013-05-10 | 2013-08-28 | 东信和平科技股份有限公司 | Patching function extension method and device for mask smart card |
CN106484369B (en) * | 2013-10-24 | 2019-11-29 | 华为技术有限公司 | A kind of method and device of online patch activation |
CN104156241B (en) * | 2014-07-31 | 2019-08-13 | 中国船舶重工集团公司第七0九研究所 | The initiated configuration method and system of processor microprogram |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01232447A (en) * | 1988-03-11 | 1989-09-18 | Mitsubishi Electric Corp | Single chip microcomputer |
US5357627A (en) * | 1989-03-28 | 1994-10-18 | Olympus Optical Co., Ltd. | Microcomputer having a program correction function |
JPH08166877A (en) * | 1994-12-13 | 1996-06-25 | Olympus Optical Co Ltd | One-chip microcomputer that can execute correction program and microcomputer that can correct rom |
US5901225A (en) * | 1996-12-05 | 1999-05-04 | Advanced Micro Devices, Inc. | System and method for performing software patches in embedded systems |
-
2000
- 2000-09-14 WO PCT/US2000/025474 patent/WO2001020453A1/en not_active Application Discontinuation
- 2000-09-14 CN CN 00812750 patent/CN1373872A/en active Pending
- 2000-09-14 KR KR1020027001886A patent/KR20020029921A/en not_active Application Discontinuation
- 2000-09-14 AU AU74953/00A patent/AU7495300A/en not_active Abandoned
- 2000-09-14 JP JP2001523963A patent/JP2003509769A/en active Pending
- 2000-09-14 EP EP00963557A patent/EP1221096A1/en not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO0120453A1 * |
Also Published As
Publication number | Publication date |
---|---|
AU7495300A (en) | 2001-04-17 |
WO2001020453A1 (en) | 2001-03-22 |
CN1373872A (en) | 2002-10-09 |
KR20020029921A (en) | 2002-04-20 |
JP2003509769A (en) | 2003-03-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7613937B2 (en) | Method and apparatus for utilizing a microcontroller to provide an automatic order and timing power and reset sequencer | |
US4524415A (en) | Virtual machine data processor | |
EP0554917B1 (en) | Digital signal processing system having two instruction memories accessed by a processor under control of host | |
US4635193A (en) | Data processor having selective breakpoint capability with minimal overhead | |
US4831517A (en) | Branch and return on address instruction and methods and apparatus for implementing same in a digital data processing system | |
EP0128156B1 (en) | Data processor version validation | |
US7900036B2 (en) | System and method for implementing boot/recovery on a data processing sysem | |
US4488228A (en) | Virtual memory data processor | |
US6006030A (en) | Microprocessor with programmable instruction trap for deimplementing instructions | |
JPH08263282A (en) | Branching control system for rom program processor | |
JP2875842B2 (en) | Programmable controller | |
US6925522B2 (en) | Device and method capable of changing codes of micro-controller | |
EP1221096A1 (en) | Method and apparatus for modifying microinstructions in a static memory device | |
WO1997008618A1 (en) | Data processing apparatus and method for correcting faulty microcode | |
US6990569B2 (en) | Handling problematic events in a data processing apparatus | |
US20030110367A1 (en) | External microcode | |
US20010052114A1 (en) | Data processing apparatus | |
CN111984329A (en) | Standardized boot software generation and execution method and system | |
CA1223079A (en) | Data processor having selective breakpoint capability with minimal overhead | |
GB2373888A (en) | Dynamic vector address allocation for a code patching scheme | |
JPS5835648A (en) | Program execution controlling system | |
JP2005063311A (en) | Patch method and patch application program for processor system | |
JPH04533A (en) | Information processing system | |
JPH04534A (en) | Information processing system | |
JP2004185356A (en) | Debug system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20020226 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: LEE, WAY-SHING Inventor name: ZOU, QIUZHEN Inventor name: FOERSTER, GREGORY, B. Inventor name: ZHANG, LI |
|
17Q | First examination report despatched |
Effective date: 20020926 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20021207 |