CN1373872A - Method and apparats for modifying microinstructions in static memory device - Google Patents
Method and apparats for modifying microinstructions in static memory device Download PDFInfo
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- CN1373872A CN1373872A CN 00812750 CN00812750A CN1373872A CN 1373872 A CN1373872 A CN 1373872A CN 00812750 CN00812750 CN 00812750 CN 00812750 A CN00812750 A CN 00812750A CN 1373872 A CN1373872 A CN 1373872A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/66—Updates of program code stored in read-only memory [ROM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
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Abstract
Method and apparatus for modifying the program flow of microinstructions residing in a static memory device. When microinstructions from the static memory device need to be modified, a jump point register is used to hold a jump point address that triggers an interrupt event. When the current program counter contains an address equal to the jump point address and the jump point register is enabled, an interrupt event is generated that redirects the program flow away from the static memory device to a programmable memory device. Rather than using the interrupt to indicate the occurrence of an external event, the interrupt is used to bypass portions of the microinstructions residing in the static memory device.
Description
Technical field
The present invention relates to be used for the control store field of microprocessor.Specifically, the present invention relates to modification to the control store apparatus that uses ROM (read-only memory) (ROM) and random access memory (RAM) simultaneously.
Background technology
Control store contains the micro-order carried out of control microprocessor data path.On some machines, control store is made up of RAM, and in other machines, control store is exactly ROM.The content of RAM is easy to rewrite with new information.Yet RAM easily loses, and promptly the content of RAM only can keep during the cycle during this period of time that applies power supply to circuit.On the contrary, the content of ROM is to insert when ROM makes, even and can not be changed or wipe when outage.
When extensive manufacturing, ROM is cheap more a lot of than RAM.Be in the consideration to RAM and ROM cost, micro code program person is usually with the new circuit of RAM design, so that revision program mistake at an easy rate, but in the final design phase,, just replace RAM with ROM for production cost being reduced to minimum.Yet, even the check of strict design also can be omitted program error, and these wrong will forever being embedded among the static ROM subsequently.
When finding program error is arranged in the microinstruction set in being stored in ROM, the programmer just creates patch and corrects mistakes." patch " term in the art is meant introduces the fresh code that is used to revise previous code or adds new function.Micro-order is called " code " on the whole, and designs with modular manner, and wherein whole code is made up of independent subroutine.Therefore, can isolate and revise the mistake of certain part in the code, and not need whole code is all rewritten.When finding the defecton program, the programmer will create does not have wrong copy subroutine, and this subroutine can the substitutional defect subroutine be called by program circuit.Just may realize this technology by the system that uses RAM and ROM storage microinstruction set simultaneously.Subroutine is stored among the ROM usually, and the main program code of call subroutine then is stored among the RAM.Because program circuit is undertaken by the microinstruction set among the RAM, so, just allow program circuit to carry out the micro-order of subroutine among the ROM from the exit point of main code.When subroutine is carried out, program circuit just withdraws from subroutine, and returns to the main code among the RAM.Yet, invalid when in subroutine, finding when wrong corresponding to the exit point of defecton program, and the programmer must be with new subroutine fix errors.Because ROM is static, so this new subroutine must be stored among the RAM.
Owing to just can not enter or withdraw from the defecton program the predetermined point in main code, so this method just relatively lacks dirigibility.In addition because for the program error in the patch routine, no matter mistake be how less important also must be in RAM a copying whole subroutine, thereby this method has been wasted the space.There is a need in the art for and have outlet and the inlet point between ROM and RAM more flexibly in the program.In addition, need reduce to minimum by the RMA capacity that program error among the modified R OM is required.
Summary of the invention
The present invention is positioned a kind of for making the programmer have more direct visit and control to the ROM micro-order, and the method and apparatus that the micro-order program circuit that resides among the ROM is made amendment.Because can not change, so any required variation to microinstruction set all must be carried out in RAM to the micro-order among the ROM.The present invention allows the programmer directly to visit program error among the ROM, and need be in RAM a copying whole subroutine.The present invention also allows the programmer to add new function for outmoded ROM, rather than replaces old ROM with newly-designed ROM.
Example embodiment of the present invention is a kind of method that the program circuit of static memory is made amendment of being used for, and this method comprises the step that produces the interruption that triggers the redirect from the static memory to the programmable storage.
In one embodiment of the invention, the jump-point register is used to keep the address of jump-point.Interrupt event in this jump-point meeting trigger flow process.Programmable counter contains the address of current microinstruction in the program circuit.If programmable counter remains with the address that equates with jump-point address in the jump-point register, just produce interrupt event.This interrupt event begins to carry out the change from the static memory to the programmable storage in program circuit.
In one embodiment of the invention, interrupt event can be used to repair the program error of static memory.The programmer can create at the patch that resides in defect code part in the static memory.Subsequently, the programmer can be stored in exit address in register or other memory storages, and wherein exit address is corresponding to the address of predetermined micro-order in the defect code part.Exit address and micro-order that all are carried out in program circuit are compared.When predetermined micro-order in program circuit, occurring, just carry out the micro-order in the patch.
In another embodiment of the present invention, interrupt event can produce the change of adding function to static memory in program circuit.This change can be the extracode form that is stored in the programmable storage, and this form can be carried out at the middle of carrying out from static memory of microcode.
In another embodiment of the present invention, a plurality of jump-point registers can be with corresponding comparer and interruptive port coupling, and this port can make each independent jump-point register effective or invalid.Each independent jump-point register can be related with independent interrupt event.Therefore, use a plurality of jump-point registers to provide dirigibility, and allow her to distribute the jump-point register easily according to needs in the future to the programmer.
This modification has reduced and has been used for the wrong required RAM capacity of modified R OM, and has improved the function of ROM.
By following description, for those of skill in the art of the present invention, other targets of the present invention and advantage will be easy to understand.
Description of drawings
Fig. 1 is the legend that the traditional program flow process between RAM and the ROM is shown.
Fig. 2 illustrates the legend of the program circuit between the RAM and ROM in embodiments of the present invention.
Fig. 3 is the circuit block diagram that is used to realize the program circuit between RAM and the ROM.
Fig. 4 is the block diagram of data handling system.
Embodiment
Fig. 1 illustrates to be used for data handling system, for example computer system or general-purpose microcomputer, the method for micro-order error correction, i.e. " debugging " method, the block diagram realized of prior art.Be in illustration purpose, preferred embodiment of the present invention uses ROM and RAM to be described.Yet, in the following detailed description, can understand described method easily and be applicable to static memory and volatile memory device arbitrarily.In Fig. 1, RAM 100 programmes with the code that is invoked at the subroutine among the ROM 110.The programmable counter (not shown) that contains the microinstruction address that then will carry out is carried out downwards along the RAM storehouse, runs into microinstruction address in the ROM storehouse up to programmable counter.At point 101, withdraw from the microinstruction set of program circuit from RAM 100, and enter microinstruction set among the ROM 110.Programmable counter is carried out downwards along ROM 110, runs into microinstruction address among the RAM 100 up to it.Withdraw from the microinstruction set of program circuit from ROM 110, and at point 102 microinstruction sets that return among the RAM 100.For being stored in each subroutine among the ROM 110, repeat this processing.If yet program error need in ROM 110, revise, perhaps need to add different functions, the programmer can be to RAM 100 reprogrammings, so that walk around the subroutine that is stored among the ROM 110.Present convention is to come the defecton program is debugged by the subroutine of copying whole in RAM100 among the those skilled in the art, eliminate program error, and RAM100 is carried out reprogramming program circuit is taken to the subroutine of duplicating in RAM 100, rather than take to and be stored in defective subroutine among the ROM 110.
Illustrated as Fig. 1, if in subroutine 105 discovery procedure mistake 106, so, it is invalid that the programmer can only make from the data path 103 of RAM 100 to ROM 110, and be created to the data path 104 that resides in the alternative subroutine 107 among the RAM 100.When finishing subroutine 107, data path 108 is back to and is arranged in RAM 100 invalid data paths 103 any designed micro-order afterwards.
When program error big or small minimum, this will become the huge waste to the RAM resource.Because ROM is static, so even only there is the sub-fraction subroutine to need to rewrite, the programmer can not change the micro-order among the ROM, makes program circuit different point from ROM be redirected to RAM.
Fig. 2 illustrates in the embodiment of the invention block diagram of program circuit between the RAM 200 and ROM 210, and this embodiment allows the programmer not need whole subroutine is replicated among the RAM 200, just can debug the defecton program that is stored among the ROM 210.In addition, the programmer can comprise bells and whistles and function in the subroutine that is stored in ROM 210.As Fig. 1, during microcode zero defect part, program circuit withdraws from RAM 200 and enters ROM 210.Yet when finding mistake in ROM 210, the program circuit of Fig. 2 allows the programmer need not sacrifice RAM 200 greatly in order to correct mistakes, and just can create this wrong patch.
The programmable counter (not shown) is carried out downwards along the RAM storehouse, runs into microinstruction address in the ROM storehouse up to programmable counter.At point 201, withdraw from the microinstruction set of program circuit from RAM 200, and enter microinstruction set among the ROM 210.Programmable counter is carried out downwards along ROM 210, runs into microinstruction address among the RAM 200 up to it.Withdraw from the microinstruction set of program circuit from ROM 210, and at point 202 microinstruction sets that return among the RAM 200.Each subroutine for being stored among the ROM repeats this processing.
In example embodiment of the present invention, in the data handling system of prior art, introduced interrupt circuit.Fig. 3 will allow the programmer to create the interrupt circuit block diagram of program circuit as shown in Figure 2.
The interrupt circuit of Fig. 3 is by a plurality of registers, or other memory storages (and becoming the jump-point register usually) that can store microinstruction address are formed arbitrarily.The jump-point register remains with the jump-point address of triggering interrupt event.As known in the art, when external event occurring outside this processing, interruption will cause interim processing hang-up.The appearance of look-at-me indication interrupt event, therefore, processor is hung up current processing, and carries out look-at-me institute tasks requested.Yet in this embodiment of the present invention, be to use look-at-me with diverse method.The interrupt circuit of Fig. 3 uses and interrupts walking around the microcode part that resides among the ROM, rather than uses the generation of interrupting the indication external event.
Included interrupt circuit comprises 3 jump-point registers 300,310,320 in Fig. 3.And those skilled in the art are appreciated that the number of jump-point register can be under the situation that does not influence category of the present invention, change according to the selection of circuit designers.Each register of 3 jump-point registers by line 303,313,323 respectively separately with 3 comparers 308,318,328 in a coupling.Comparer is the device that is used for two input words of comparison, and is made up of XOR gate usually, and for this or other embodiment of the present invention, can use any device that can realize comparing function.Yet for purpose of explanation, will use " comparer " term.Each comparer 308,318,328 is by control line 304,305 and processor 320 couplings.
Each jump-point register 300,310,320 is set the address that has corresponding to interrupt event.Line 301 is loaded into each jump-point register with the address from processor 320.
Comparer 308,318,328 is given in control line 304 carryings from programmable counter content.Programmable counter is the register that contains the address of the micro-order that then will carry out.In some data handling systems, programmable counter is designed to contain the current micro-order of carrying out.The content that is appreciated that programmable counter for those skilled in the art need not be confined to expecting state or current state in order to realize any embodiment of the present invention.
The control signal of control line 305 carrying from processors 320, described signal makes each comparer 308,318,328 effective or invalid in order to realize the desired function related with each jump-point register.
If one of addresses distributed equates in the address in the programmable counter and the jump-point register 300,310,320, and sent the comparer effective control signal that makes corresponding to above-mentioned jump-point register, so, give processor 320 with regard to the transmit status signal, and send a signal to the interruptable controller (not shown), thereby interrupt.
In this example, interrupt event is not the external event that the calling program flow process is hung up, but programmable counter is redirected to the micro-order that is stored among the RAM.Program circuit continues in RAM, up to being redirected back ROM.Because RAM is dynamically, thereby RAM can be redirected to programmable counter any micro-order that is stored among the ROM.
For the purpose of debugged program code, the programmer can discern the mistake in the micro-order subroutine among a part of ROM, and the address of mistake is stored in the jump-point register.If as long as this mistake is capable with regard to recoverable less important mistake, so with several line codes.This wrong patch just can successfully be stored among the RAM.When programmable counter runs into the misaddress that is stored in the jump-point register, comparer allows to send signal to interruptable controller, produces by this signal program circuit is redirected to interruption on the patch that is stored among the RAM.Micro-order in being included in patch has been finished processing, and the RAM micro-order that follows patch closely can be redirected to program circuit follows on the ROM micro-order behind the subroutine error section.In this manner, just can under the situation that does not need whole subroutine copied among the RAM, revise the subroutine that contains the small routine mistake.
For the purpose of the interpolation of the program code in being stored in ROM function, the programmer can use the jump-point register to add more subroutine easily in the ROM subroutine structure that has existed.In one embodiment of the invention, the programmer can insert microinstruction address in the jump-point register, and wherein micro-order is that a part resides in the program subroutine among the ROM.When programmable counter contained the address of this micro-order, program circuit will jump to and reside in microinstruction set corresponding among the RAM.The final injunction of the corresponding collection of micro-order will be redirected to program circuit on the desired subroutine of programmer.In this mode, the programmer can add new function for the ROM subroutine under the situation of not replacing the old ROM that has programmed.Therefore, under the situation that ROM can not need to replace with the ROM of reprogramming, just ROM is upgraded.
The interrupt circuit of Fig. 3 is one embodiment of the present of invention, and among this embodiment, 3 jump-point and corresponding comparer pass through or door 330 and processor, and promptly the interrupt request in the interruptable controller (IRQ) pin links to each other.Still in another embodiment of the present invention,, can in data handling system, use a plurality of interrupt circuits for to no matter when triggering the quantity minimum that fresh code that interruption will occur is tested.When in single interrupt circuit, having many jump-point registers, just need a large amount of MIPS of cost determine which new code is corresponding to the interruption of triggering just.And when there being many interrupt circuits, each only has 3 or jump-point register still less, and each links to each other with independent IRQ pin, so, is realizing corresponding to will spend less MIPS in the interrupt event of triggering.The use of a plurality of interrupt circuits or single lattice interrupt circuit is the design alternative problem according to board design person's needs.Yet any variation to interrupt circuit described here all falls into category of the present invention.
Fig. 4 is the block diagram that data handling system is shown.Be appreciated that under situation about known circuit and steering logic specifically not being described in detail for those skilled in the art, also can realize the present invention.For fear of obscuring description, just from Fig. 4, ignore this concrete detailed description.The block diagram of Fig. 4 is a kind of representative of system, and in this system, steering logic is separated from operation core (operate core).This system can be digital signal processor or special IC.Yet, should be noted that the present invention can be used for having the data handling system of other system forms, for example steering logic combines with the operation core.
Program circuit control device 400 and control store RAM 430, control store ROM 440, interrupt circuit 450 and instruction decoding device 410 couplings.Interrupt circuit 450 can be the interrupt circuit of Fig. 3.The content of program circuit control device 400 generating routine counters produces the sign whether the indication present instruction has been carried out or cancelled, and handles for example direct memory access (DMA) of all external events (DMA) and interruption.Instruction decoding device 410 can not integrate with operation core 420 is integrated yet, and links to each other with program circuit control device 400 by line 405.Instruction decoding device 410 is also by line 404 and control store RAM 430 and control store ROM 440 couplings.Interrupt circuit 450 and program circuit control device 400, control store RAM 430, control store ROM 440 and 420 couplings of operation core.Program circuit control device 400 is according to the input generating routine counter from control store RAM 430, control store ROM 440 or interrupt circuit 450.Program circuit device 400 uses line RAM_CS 401, ROM_CS 403 and EXEC 412 to make from the input of control store RAM 430, control store ROM 440 or interrupt circuit 450 effective.Line 422 deposits the jump-point address in the interrupt circuit 450 jump-point register (not shown).Line 402 sends to control store RAM 430, control store ROM 440 and interrupt circuit 450 with the content of programmable counter.When the current programmable counter of interrupt circuit 450 indication contains the address that equates with the jump-point address contained in the jump-point register (not shown), just by being integrated in program circuit control device 400 or not being integrated in wherein interruptable controller (not shown) generation interruption.When interrupt circuit 450 produced interruption, program circuit control device 400 resetted programmable counter and preserves next specified microinstruction address of interrupt event.
The data handling system of Fig. 4 only is the illustrated example how embodiment of the invention is used.Should notice that the present invention can use various computer programming languages and hardware to realize, and be not limited to any specific hardware and software configuration.For example, shown in module 490, the function of program circuit control device 400, instruction decoder 410 and operation core 420 can realize by using general processor.The present invention can for example use code storage at static memory any among the embodiment in ROM, tape storage element, CD or the floppy disk.
Can recognize that in the case of without departing from the present invention, the present invention can have other and different embodiment, and its some details can be made amendment from different aspects.Thereby accompanying drawing and description are actually as an illustration, rather than limitation of the present invention.
Claims (15)
1, a kind of method that the program circuit of static memory is made amendment of being used for is characterized in that, described method comprises the step that produces the interruption that triggers the redirect from the static memory to the programmable device.
2, the method for claim 1 is characterized in that, the step that described generation is interrupted comprises the steps:
Store the copy of first microinstruction address, wherein first micro-order is the part of first microinstruction set, and first microinstruction set is the subclass that resides in the subroutine in the static memory;
To substitute microinstruction set is stored in the programmable storage;
During program circuit, the address of every micro-order in the subroutine and the copy of being stored are compared; And
When the result of comparison step is mated, with alternative microinstruction set first microinstruction set is replaced, wherein, replacement step produces the redirect from the static memory to the programmable storage in program circuit.
3, method as claimed in claim 2 is characterized in that, described static memory comprises ROM (read-only memory) (ROM) device, and described programmable storage comprises random access storage device (RAM) device.
4, method as claimed in claim 3 is characterized in that, described alternative microinstruction set comprises the patch at the program error that is occurred in subroutine.
5, the method for claim 1 is characterized in that, the step that described generation is interrupted comprises the steps:
Store the copy of first microinstruction address, wherein first micro-order is a part that is embedded in first microinstruction set in first subroutine, and first subroutine resides in static memory;
To add microinstruction set is stored in the programmable storage;
During program circuit, the address of every micro-order in the subroutine and the copy of being stored are compared; And
When the result of comparison step is mated, add additional microinstruction set, wherein, the interpolation step produces the redirect from the static memory to the programmable storage in program circuit.
6, method as claimed in claim 5 is characterized in that, described additional microinstruction set is second subroutine with additional function.
7, the method for claim 1 is characterized in that, the step that described generation is interrupted comprises the steps:
Use the jump-point register to preserve the jump-point address, interrupt event can be triggered in described jump-point address;
Order is carried out first microinstruction set, wherein said first microinstruction set resides in the static memory, is stored in the corresponding address in the programmable counter term of execution that wherein each micro-order carried out in proper order in described first microinstruction set having in order separately; With
If programmable counter is preserved the address that equates with jump-point address in the described jump-point register, just with interrupt event interrupt routine flow process.
8, method as claimed in claim 7 is characterized in that, the step of described interrupt routine flow process comprises the steps:
Control signal is set to have ready conditions makes comparer effective, wherein said comparer compares the address that the address in the described programmable counter and described redirect register are comprised; With
If comparer receives effective control signal, just carry out second microinstruction set corresponding to described jump-point address, wherein said second microinstruction set resides in the programmable storage.
9, method as claimed in claim 8 is characterized in that, described programmable storage is random access storage device (RAM) device.
10, the method for claim 1 is characterized in that, the step that described generation is interrupted further comprises the steps:
Store a plurality of jump-point address, each jump-point address is stored in the corresponding jump-point register, and corresponding interrupt event is triggered in each jump-point address;
Which the jump-point address that pre-determines a plurality of jump-point address will be effectively;
Order is carried out first microinstruction set, and described first microinstruction set resides in the static memory, and wherein programmable counter keeps the address of each micro-order of carrying out in proper order; With
If if programmable counter remain with a plurality of jump-point address in certain address that equates or jump-point address effective, just carry out corresponding interrupt event.
11, method as claimed in claim 10 is characterized in that, the step of described execution interrupt event comprises the steps:
Pre-determine a plurality of microinstruction sets corresponding with each address of a plurality of jump-point address;
It is effective that control signal is set at each unit that makes a plurality of comparers of having ready conditions, wherein the coupling of each comparer and corresponding jump-point register and programmable counter and
If a comparer in a plurality of comparers receives effective control signal, just carry out corresponding microinstruction set with described jump-point address correlation, wherein said jump-point address equates that with address in the programmable counter wherein said corresponding microinstruction set resides in the programmable storage.
12, method as claimed in claim 11 is characterized in that, what the step of the corresponding microinstruction set of described execution was followed later is the follow-up micro-order of carrying out from described first microinstruction set.
13, be used to handle the equipment of programmable machine command signal, it is characterized in that, comprising:
The jump-point register that contains at least one predetermined jump-point;
The static memory that contains first microinstruction set, described static memory and the coupling of jump-point register;
The random access memory device that contains second microinstruction set, described random access memory device and described jump-point register and static memory coupling;
With the procedure control unit of described jump-point register, static memory and random access memory device coupling, wherein said procedure control unit sends a plurality of control signals to described jump-point register, described static memory and random access memory device; With
Comparer with described jump-point register and the coupling of described procedure control unit compares between the signal of wherein said comparer in described predetermined jump-point and a plurality of at least control signal, and according to the described look-at-me that relatively produces.
14, equipment as claimed in claim 13 is characterized in that, further comprises:
A plurality of jump-point registers, each described jump-point register contains at least one predetermined jump-point, and each register, static memory and the random access memory device of wherein said procedure control unit in a plurality of jump-point registers sends a plurality of control signals; And
A plurality of comparers, one of each comparer and described a plurality of jump-point registers and the coupling of described procedure control unit, wherein compare between the signal of each described comparer in corresponding jump-point address and a plurality of at least control signal, and according to the described look-at-me that relatively produces.
15, be used for equipment that the micro-order program circuit that resides in static memory is made amendment, it is characterized in that, comprising:
Be used for to be scheduled to the device that microinstruction address is stored in the device except that static memory;
Be used to store the device of the first microinstruction address collection, wherein said memory storage is easily to lose;
Be used for the device that each address with described predetermined microinstruction address and the described first microinstruction address collection compares; And
Be used to produce the device of a plurality of control signals, described device and described predetermined microinstruction address memory storage, volatile memory device and comparison means coupling, wherein said control signal device can make the modification of program circuit transfer in the described volatile memory device from described static memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US39891299A | 1999-09-14 | 1999-09-14 | |
| US09/398,912 | 1999-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1373872A true CN1373872A (en) | 2002-10-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00812750 Pending CN1373872A (en) | 1999-09-14 | 2000-09-14 | Method and apparats for modifying microinstructions in static memory device |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1221096A1 (en) |
| JP (1) | JP2003509769A (en) |
| KR (1) | KR20020029921A (en) |
| CN (1) | CN1373872A (en) |
| AU (1) | AU7495300A (en) |
| WO (1) | WO2001020453A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7464248B2 (en) | 2005-04-25 | 2008-12-09 | Mediatek Incorporation | Microprocessor systems and bus address translation methods |
| CN103268237A (en) * | 2013-05-10 | 2013-08-28 | 东信和平科技股份有限公司 | Patching function extension method and device for mask smart card |
| CN103530184A (en) * | 2013-10-24 | 2014-01-22 | 华为技术有限公司 | Method and device for online patch activation |
| CN104156241A (en) * | 2014-07-31 | 2014-11-19 | 中国船舶重工集团公司第七0九研究所 | Initialization configure method and initialization configure system for micro-programs of processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01232447A (en) * | 1988-03-11 | 1989-09-18 | Mitsubishi Electric Corp | Single chip microcomputer |
| US5357627A (en) * | 1989-03-28 | 1994-10-18 | Olympus Optical Co., Ltd. | Microcomputer having a program correction function |
| JPH08166877A (en) * | 1994-12-13 | 1996-06-25 | Olympus Optical Co Ltd | One-chip microcomputer that can execute correction program and microcomputer that can correct rom |
| US5901225A (en) * | 1996-12-05 | 1999-05-04 | Advanced Micro Devices, Inc. | System and method for performing software patches in embedded systems |
-
2000
- 2000-09-14 CN CN 00812750 patent/CN1373872A/en active Pending
- 2000-09-14 AU AU74953/00A patent/AU7495300A/en not_active Abandoned
- 2000-09-14 JP JP2001523963A patent/JP2003509769A/en active Pending
- 2000-09-14 EP EP00963557A patent/EP1221096A1/en not_active Withdrawn
- 2000-09-14 KR KR1020027001886A patent/KR20020029921A/en not_active Application Discontinuation
- 2000-09-14 WO PCT/US2000/025474 patent/WO2001020453A1/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7464248B2 (en) | 2005-04-25 | 2008-12-09 | Mediatek Incorporation | Microprocessor systems and bus address translation methods |
| CN103268237A (en) * | 2013-05-10 | 2013-08-28 | 东信和平科技股份有限公司 | Patching function extension method and device for mask smart card |
| CN103530184A (en) * | 2013-10-24 | 2014-01-22 | 华为技术有限公司 | Method and device for online patch activation |
| CN104156241A (en) * | 2014-07-31 | 2014-11-19 | 中国船舶重工集团公司第七0九研究所 | Initialization configure method and initialization configure system for micro-programs of processor |
| CN104156241B (en) * | 2014-07-31 | 2019-08-13 | 中国船舶重工集团公司第七0九研究所 | The initiated configuration method and system of processor microprogram |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001020453A1 (en) | 2001-03-22 |
| AU7495300A (en) | 2001-04-17 |
| EP1221096A1 (en) | 2002-07-10 |
| JP2003509769A (en) | 2003-03-11 |
| KR20020029921A (en) | 2002-04-20 |
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