EP1220455A1 - Décodeur Viterbi, procédé et unité correspondant - Google Patents

Décodeur Viterbi, procédé et unité correspondant Download PDF

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Publication number
EP1220455A1
EP1220455A1 EP00403711A EP00403711A EP1220455A1 EP 1220455 A1 EP1220455 A1 EP 1220455A1 EP 00403711 A EP00403711 A EP 00403711A EP 00403711 A EP00403711 A EP 00403711A EP 1220455 A1 EP1220455 A1 EP 1220455A1
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EP
European Patent Office
Prior art keywords
metric
path metric
metrics
output
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00403711A
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German (de)
English (en)
Inventor
Markus Muck
Ralph Heckmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Motorola Inc filed Critical Freescale Semiconductor Inc
Priority to EP00403711A priority Critical patent/EP1220455A1/fr
Priority to US10/023,543 priority patent/US7042964B2/en
Publication of EP1220455A1 publication Critical patent/EP1220455A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6325—Error control coding in combination with demodulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3961—Arrangements of methods for branch or transition metric calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3988—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Definitions

  • Viterbi decoding is commonly used in the receiving side of digital communication systems where potentially disrupted signals (e.g., disrupted by a fading channel, noise, etc.) must be decoded. Such signals are typically the result of bit-streams that have been encoded using convolutional codes and modulated for transmission, and such received encoded signals are typically decoded using a maximum-likelihood algorithm, generally based on the 'Viterbi algorithm'.
  • the main problem of the Viterbi algorithm lies in its arithmetical decoding complexity (thus leading to high power consumption, etc., which is a paramount consideration in battery-operated portable communication devices).
  • a lot of research has been done with the aim of reducing complexity associated with the Viterbi algorithm.
  • a Viterbi decoder as claimed in claim 1.
  • a method of producing metrics for use in a Viterbi decoder, as claimed in claim 3.
  • a butterfly unit for use in a Viterbi decoder Add-Compare-Select unit, as claimed in claim 9.
  • Convolutional codes are commonly used in digital communication systems in order to encode a bit-stream before transmission.
  • a deconvolution has to be performed on the received symbols that have been possibly corrupted by fading due to a multipath channel and by additive noise.
  • a classical implementation of the Viterbi algorithm, as shown in FIG. 1, to perform a Maximum-Likelihood decoding of the received data consists of three blocks:
  • the present invention concerns techniques for reducing the complexity of a Viterbi decoder.
  • the present invention provides a new ACS unit that may be used at certain positions in a Viterbi decoder to simplify the processing required, and provides certain new metrics for use with the new ACS units to decrease the overall complexity of Viterbi decoding.
  • the critical element in a Viterbi decoder is usually the ACS unit, of which a typical example is shown in FIG. 2.
  • N / 2 ACS butterfly operations have to be performed per trellis transition if a N -state convolutional encoder is used.
  • all N / 2 or at least some (for example, a number P between 1 and N / 2 ) ACS butterflies have to work in parallel, requiring an important amount of chip surface in the case of a hardware implementation. Consequently, the power consumption of the ACS units is important compared to the total consumption of the decoder.
  • the new butterfly unit 300 has one adder 310 for adding the path metric 1 and branch metric 2, and another adder 320 for adding the path metric 2 and branch metric 2.
  • a comparator 330 compares the output of the adder 320 and the path metric 1
  • a comparator 340 compares the output of the adder 310 and the path metric 2.
  • a selector 350 selects between the output of the adder 320 and the path metric 1, dependent on the comparator 330, to produce the survivor path metric 1;
  • a selector 360 selects between the output of the adder 310 and the path metric 2, dependent on the comparator 340, to produce the survivor path metric 2. It is to be noted that only one branch metric value (as shown, branch metric 2) is used in the butterfly unit 300.
  • any branch metric m ba ⁇ ( m b 1 , m b 2 ,..., m bl ) may be chosen and subtracted from all other branch metrics.
  • This rule is based on the typically valid observation that the encoder output bits remain unchanged if both, the input bit to the encoder and the most significant bit (MSB) of the encoder state are inverted.
  • this method has the disadvantage that the resulting metrics m b1 , m b2 , ..., m bl might have a larger dynamic range than the classical metrics m 1 , m 2 , ..., m l .
  • the following discussion progresses from the above general case to a slightly specialised case where this disadvantage is resolved.
  • z 1 is the complex transmitted symbol
  • H * / 1 is the complex conjugate of the channel coefficient
  • AWGN additive white gaussian noise
  • a code rate of R 1 / 2
  • the new metrics m b1 , m b2 , m b3 , m b4 are less complex (2 multiplications, 1 addition) than the classical ones m b1 , m b2 , m b3 , m b4 (2 multiplications, 2 additions, 2 sign inversions).
  • FIG. 5 shows equivalent schematic representations of implementations of the four ACS butterflies of FIG. 4.
  • the low complexity ACS butterflies Type I and Type II are similar to that of FIG. 3, and similar to each other (the input signals 'path metric 1' and 'path metric 2' being interchanged between the Type I and Type II butterflies).
  • the higher complexity ACS butterflies Type III and Type IV are similar to that of FIG. 2 and similar to each other (the input signals 'metric m b2 ' and 'metric m b3 ' being interchanged between the Type III and Type IV butterflies).
  • the metrics can also be used in coloured noise environments.
  • the proposed technique may be used for any Viterbi decoder in general. However, it is especially interesting for OFDM systems, since the resulting optimised metrics do not require any additional precision, at least if the metric calculation is performed adequately, as presented by the example of Table 1.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
EP00403711A 2000-12-29 2000-12-29 Décodeur Viterbi, procédé et unité correspondant Withdrawn EP1220455A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP00403711A EP1220455A1 (fr) 2000-12-29 2000-12-29 Décodeur Viterbi, procédé et unité correspondant
US10/023,543 US7042964B2 (en) 2000-12-29 2001-12-17 Viterbi decoder, method and unit therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00403711A EP1220455A1 (fr) 2000-12-29 2000-12-29 Décodeur Viterbi, procédé et unité correspondant

Publications (1)

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EP1220455A1 true EP1220455A1 (fr) 2002-07-03

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EP (1) EP1220455A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7043682B1 (en) * 2002-02-05 2006-05-09 Arc International Method and apparatus for implementing decode operations in a data processor
US7515658B2 (en) * 2004-06-29 2009-04-07 Stmicroelectronics Asia Pacific Pte. Ltd. Method to adaptively scale the input to a channel decoder
US20080152044A1 (en) * 2006-12-20 2008-06-26 Media Tek Inc. Veterbi decoding method for convolutionally encoded signal
US8181098B2 (en) * 2008-06-11 2012-05-15 Freescale Semiconductor, Inc. Error correcting Viterbi decoder
TWI422165B (zh) * 2009-10-16 2014-01-01 Mstar Semiconductor Inc 解碼方法及其裝置
CN102045070B (zh) * 2009-10-19 2015-11-25 晨星软件研发(深圳)有限公司 译码方法及其装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5742621A (en) * 1995-11-02 1998-04-21 Motorola Inc. Method for implementing an add-compare-select butterfly operation in a data processing system and instruction therefor
FR2769434A1 (fr) * 1997-08-30 1999-04-09 Hyundai Electronics Ind Methode de decodage viterbi et decodeur viterbi utilisant la valeur de distance minimale et/ou la valeur metrique de trajet minimale

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US5327440A (en) * 1991-10-15 1994-07-05 International Business Machines Corporation Viterbi trellis coding methods and apparatus for a direct access storage device
US5291499A (en) * 1992-03-16 1994-03-01 Cirrus Logic, Inc. Method and apparatus for reduced-complexity viterbi-type sequence detectors
US5414738A (en) * 1993-11-09 1995-05-09 Motorola, Inc. Maximum likelihood paths comparison decoder
US5530707A (en) * 1994-03-09 1996-06-25 At&T Corp. Area-efficient decoders for rate-k/n convolutional codes and other high rate trellis codes
US5815515A (en) * 1996-03-28 1998-09-29 Lsi Logic Corporation Edge metric calculation method and apparatus using permutations
KR100195745B1 (ko) * 1996-08-23 1999-06-15 전주범 비터비 복호화기의 가산 비교 선택 장치
DE69719141T2 (de) * 1996-10-15 2003-07-24 Matsushita Electric Ind Co Ltd Vorrichtung zur Zurückverfolgung des Pfades in einem Viterbi Dekodierer
US6163581A (en) * 1997-05-05 2000-12-19 The Regents Of The University Of California Low-power state-sequential viterbi decoder for CDMA digital cellular applications
US6334202B1 (en) * 1998-07-22 2001-12-25 Telefonaktiebolaget Lm Ericsson (Publ) Fast metric calculation for Viterbi decoder implementation
US6553541B1 (en) * 1999-04-14 2003-04-22 Texas Instruments Incorporated Reduced-complexity sequence detection
BR0007197A (pt) * 1999-10-05 2001-09-04 Samsung Electronics Co Ltd Decodificador de componente e método do mesmo em sistema de comunicação móvel
US6901118B2 (en) * 1999-12-23 2005-05-31 Texas Instruments Incorporated Enhanced viterbi decoder for wireless applications

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5742621A (en) * 1995-11-02 1998-04-21 Motorola Inc. Method for implementing an add-compare-select butterfly operation in a data processing system and instruction therefor
FR2769434A1 (fr) * 1997-08-30 1999-04-09 Hyundai Electronics Ind Methode de decodage viterbi et decodeur viterbi utilisant la valeur de distance minimale et/ou la valeur metrique de trajet minimale

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US7042964B2 (en) 2006-05-09

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