EP1203409A1

EP1203409A1 - Arrangement with p-doped and n-doped semiconductor layers and method for producing the same

Info

Publication number: EP1203409A1
Application number: EP01956284A
Authority: EP
Inventors: Richard Spitz; Alfred Goerlach
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2000-07-05
Filing date: 2001-06-22
Publication date: 2002-05-08
Also published as: AU7836601A; US20020179924A1; AU781754B2; DE10032543A1; JP2004503092A; WO2002003473A1; TW512538B; US7170104B2

Abstract

The invention relates to an arrangement with P-doped semiconductor layers (12) and N-doped semiconductor layers (14, 10). Said arrangement has junctions between said P-doped semiconductor layers (12) and said N-doped semiconductor layers (14, 10), these junctions showing a Zener breakdown when a characteristic voltage for a junction is applied. A plurality of junctions are present between the P-doped semiconductor layers (12) and the N-doped semiconductor layers (14, 10) and the characteristic voltages enter additively into the breakdown voltage of the arrangement overall. The invention also relates to a method for producing an inventive arrangement.

Description

Arrangement with P-doped and N-doped semiconductor layers and method for their production

The invention relates to an arrangement with P-doped and N-doped semiconductor layers, which has transitions between the P-doped semiconductor layers and the N-doped semiconductor layers, the transitions showing a Zener breakdown when a voltage characteristic of a transition is applied. The invention further relates to a method for producing the arrangement according to the invention.

State of the art

It is known to use semiconductor components for voltage limitation. Zener diodes (Z diodes) are used in particular for this purpose. If Zener diodes are operated in reverse or reverse direction, they show a distinctive breakdown behavior with comparatively low breakdown voltages. The size of the breakdown voltage of a diode essentially depends on the doping concentration of the semiconductor material. In the case of highly doped diodes, a very narrow barrier layer is formed, so that high electrical field strengths lie above the PN junction even when small reverse voltages are applied. If the field strength exceeds a value in the order of 10 ⁵ V / cm, valence electrons in the region of the almost charge-free PN junction can be torn out of their bonds. In the band model, this effect presents itself as a tunneling of the forbidden band. At low voltages below the breakdown voltage, which is also called Zener voltage, only the generally negligible reverse current flows. When the Zener voltage is reached, the current rises sharply due to the charge carrier emission. This prevents a further increase in voltage. At breakdown voltages below 4.5 V one speaks of a pure Zener breakdown. At higher breakdown voltages, another breakdown effect competes, namely the so-called avalanche or avalanche breakdown. This predominates at voltages above 7 V and essentially results from avalanche-like impact ionizations in the semiconductor. A Zener diode is suitable as a voltage limiter due to the defined and reversible breakdown. If you interconnect two Zener diodes in an antiserial manner - that is, in series, but with opposite polarity - you get symmetrical breakdown behavior.

Such a circuit is shown in Figure 6. A first Zener diode 110 and a second Zener diode 112 are shown, which are connected in series. Such arrangements are used for voltage limitation if both polarities of the voltage of a voltage applied to the contacts 114, 116 are to be limited. Figure 7 shows the corresponding current-voltage characteristic of the circuit shown in Figure β. In the diagram from FIG. 7, the current flowing through the Zener diodes 110, 112 is plotted against the voltage applied to the contacts 114, 116. The breakdown voltage of the arrangement is UZ1 + UF, provided that rail resistances and the rise in breakdown voltage due to self-heating are neglected. Here UZ1 denotes the breakdown voltage of one of the Zener diodes, which in the present case are assumed to be identical, and ÜF the voltage drop of a diode in the forward direction. ^• However, If you want to interpret for greater border tensions such a voltage limiting circuit, so it comes to the indicated in Figure 7 positive temperature coefficient of the breakdown voltage. FIG. 7 shows a solid line at room temperature (RT) and a broken line at high temperature (HT). The positive temperature response to be recognized mainly results from the fact that the avalanche breakdown dominates in diodes which are designed for higher breakdown voltages.

The temperature dependence of the characteristic curve shown in FIG. 7 is undesirable. Furthermore, the voltage limiting circuit according to FIG. 6 has the disadvantage that two separate components are required for implementation, which entails additional circuit complexity. Advantages of the invention

The invention is based on the _^ generic arrangement according to claim 1 characterized in that a plurality of over- addressed doped between P-type semiconductor layers and n-type semiconductor layers is present and that the characteristic voltages additive in the breakdown voltage of the whole assembly received. It is therefore no longer necessary to use two separate components in order to limit the voltage for both polarities of the voltage. Rather, a single arrangement with a plurality of transitions between P-doped semiconductor layers and N-doped semiconductor layers can provide a voltage limitation of both polarities. In addition, since the characteristic voltages of the transitions, in which the transitions show a breakdown, are additively included in the breakdown voltage of the entire arrangement, it is possible to select the individual breakdown voltages as low and still limit them to one by adding the individual breakdown voltages to cause comparatively high voltage. Since the Zener effect dominates at the small characteristic voltages of the individual transitions, which may be 4.2 V, for example, i.e. the avalanche breakdown does not play a role or only plays a minor role, despite the high limit voltage provided, a practically temperature-independent characteristic curve can be used Will be provided.

The semiconductor layers are preferably highly doped. A high doping leads to a low breakthrough Voltage and thus to the desired temperature independence of the device.

It can be advantageous if the semiconductor layers have constant doping. This offers itself in the sense of simple manufacture. Furthermore, the breakdown voltage can be calculated in a simple manner on the basis of the identical properties of the transitions between the layers with constant doping.

It can also be preferred if the P-doped semiconductor layers and the N-doped semiconductor layers are doped with the same concentration. This results in a uniform formation of the depletion zone both in the N-doped semiconductor layers and in the P-doped semiconductor layers. This allows the layer sequence to be designed uniformly.

It can be preferred that the P-doped semiconductor layers form at least two groups that are doped with different concentrations. In this way, it is possible to obtain a characteristic curve that is asymmetrical with respect to the voltage polarity, unlike in the case of uniform doping of all P semiconductor layers or of all N semiconductor layers, where a symmetrical characteristic curve is present. Different voltage limits can thus be provided depending on the polarity of the voltage.

For the same reason, it can be advantageous if the N-doped semiconductor layers have at least two groups form, which are doped with different concentrations.

It is possible for the semiconductor layers to be arranged on an N-doped substrate.

It is also possible for the semiconductor layers to be arranged on a P-doped substrate. Consequently, no particular doping of the substrate is required, which means that the arrangement is flexible with regard to manufacture and use.

It can be useful that the type of doping of the semiconductor layer furthest from the substrate corresponds to the type of doping of the substrate.

On the other hand, it is also possible that the type of doping of the semiconductor layer furthest from the substrate is different than the type of doping of the substrate. Here, too, one is flexible with regard to the manufacture and the areas of application of the arrangement and is not restricted to a specific type of doping of the outermost semiconductor layers.

It can be advantageous if the semiconductor layers have a thickness of approximately 4 μm. Such a thickness is suitable for the practical breakdown voltages of the individual transitions and the associated thicknesses of the depletion zones, that is to say it is sufficiently high. The corresponding thickness prevents the minority charge carriers injected through the transitions polarized in the direction of flow from entering a space charge zone. reach a neighboring transition that is in reverse polarity. This is absolutely necessary, otherwise the entire arrangement would be "ignited" (thyristor effect).

It may be useful if the substrate is about 500 microns thick. Adequate mechanical stability is ensured, among other things, by such a substrate thickness.

The concentration of the doping is preferably in the range of 2 × 10 ¹⁹ atoms / cm ³ . With such a high doping concentration, a Zener effect is obtained in every transition at the desired low Zener voltage and thus with a correspondingly low temperature dependence.

In a special embodiment, about 10 transitions between P-doped semiconductor layers and N-doped semiconductor layers are provided. With Zener voltages in the range of 4.2 V and forward voltages in the range of 0.7 V, an exemplary total breakdown voltage of 50 V is obtained without significant temperature dependence. If one wanted to implement such a voltage limitation with a conventional construction of the prior art, that is to say with individual Zener diodes, one would have a considerable and sometimes intolerable temperature dependency due to the strong dominance of the avalanche effect.

The arrangement preferably has metal contacts on its top and bottom that are extend over their entire area. The arrangement is thus prepared for further processing, as is usually the case with semiconductor components.

The semiconductor layers are preferably silicon layers. The high doping and the desired layer structure can be realized in a particularly favorable manner with silicon.

The invention further consists, according to claim 17, in a method for producing an arrangement with P-doped and N-doped semiconductor layers, which has transitions between the P-doped semiconductor layers and the N-doped semiconductor layers, the transitions when applying a characteristic of a transition Voltage show a Zener breakdown, there are a plurality of transitions between P-doped semiconductor layers and N-doped semiconductor layers, and the characteristic voltages additively enter into the breakdown voltage of the entire arrangement, the method comprising the application of the semiconductor layers by epitaxy. Epitaxy is a particularly suitable method for building up layer arrangements which make up the present invention.

The epitaxy preferably takes place at approximately 1180 ° C. This temperature has proven to be particularly favorable for an error-free layer formation.

It is also useful if the epitaxy occurs at a growth rate of approximately 4 μm / min. This ensures a high quality layer structure, whereby the manufacturing process is of sufficient speed.

Metal contacts are preferably sputtered onto the top and bottom of the arrangement. The arrangement is prepared for further processing by means of these metal contacts, which preferably cover the entire upper side and the entire lower side of the arrangement. The sputtering method has proven to be particularly reliable for the application of thin metal layers.

The arrangement is preferably divided into individual chips after the metal contacts have been sputtered on. For example, a silicon substrate initially used could have a diameter of 125 mm. The chips resulting from the method, which are produced, for example, using a circular saw, can then have an area of 20 mm ² , for example.

It is particularly preferred that the edges of the chips are removed. If the chips are produced, for example, by a sawing process, crystal disturbances occur at the edge of the chip, which have a negative effect on the electrical properties of the component. This disturbed semiconductor area at the edge of the chip is then removed, for example, to a depth of approximately 50 μm. This can be achieved, for example, by etching in KOH. The etching often only takes place when the front and back of the chip have been soldered into a copper housing. The further packaging is then carried out in a manner customary in diode technology. In addition to the structure of the layer arrangement by epitaxy, it is also possible to join thin silicon wafers using wafer bonds. So you are variable in terms of production.

The invention is based on the surprising finding that it is possible with a corresponding layer arrangement of P-doped and N-doped semiconductor layers to provide bipolar voltage limitation with negligible temperature dependence. The breakdown voltage of individual PN junctions can be selected by suitable doping so that a practically pure Zener breakdown takes place. By designing the layer arrangement in such a way that the breakdown voltages of the individual PN junctions additively enter into the breakdown voltage of the overall arrangement, a voltage limitation can also be generated for high voltages with low temperature dependence.

drawings

The invention is explained below by way of example with reference to the accompanying drawings using embodiments.

Figure 1 shows schematically a cross section of an arrangement according to the invention;

FIG. 2 shows a characteristic curve of an arrangement according to FIG. 1; FIG. 3 shows a doping profile of an arrangement according to FIG. 1;

Figure 4 shows schematically a cross section of a further embodiment of an arrangement according to the invention;

FIG. 5 shows a characteristic curve of an arrangement according to FIG. 4;

Figure 6 shows a circuit of the prior art;

FIG. 7 shows a characteristic curve of the arrangement according to FIG. 6.

Description of the embodiments

Figure 1 shows schematically a cross section of an arrangement according to the invention. A plurality of P-doped semiconductor layers 12 and N-doped semiconductor layers 14 are arranged on an N-doped silicon substrate 10. A plurality of semiconductor junctions are present between the P-doped semiconductor layers 12 and the N-doped semiconductor layers 14. The P-doped semiconductor layers 12 have a thickness TP, while the N-doped semiconductor layers have a thickness TN. In the present case, the thicknesses TP and TN ^'are approximately equal and are approximately 4 μ. The substrate has a thickness TS of approximately 525 μm in the present example. Since a total of 10 P-doped semiconductor layers and 10 N-doped semiconductor layers 14 are arranged on the substrate 10, the total thickness of the arrangement results from this information. T to 605 μm. In the present example, silicon is chosen as the semiconductor. On the N-doped substrate 10 and the uppermost semiconductor layer, which in the present case is an N-doped semiconductor layer 14, there are metal contacts 16, 18 which have been applied by a sputtering process. The semiconductor layers 12, 14 each have a constant doping of approximately 2 × 10 ¹⁹ atoms / cm ³ . Layers 12, 14 were applied to the layer below by epitaxes. In a preferred embodiment, the epitaxy takes place in such a way that a temperature of 1180 ° C. and a growth rate of 4 μm / min is selected. In the present example according to FIG. 1, the layer arrangement is selected such that the top layer and the bottom layer (substrate) have the same doping type, in the present case an N doping. Furthermore, it is possible that the two outer comprise ^{'semiconductor} layers, a P-type doping. Furthermore, the outer layers can be of different doping types, both for an N substrate and for a P substrate.

FIG. 2 shows in simplified form a characteristic curve of the arrangement from FIG. 1. If a voltage U, which is positive in comparison to electrode 16, is applied to the metal electrode 18, no current flows except for a relatively small reverse current until the reverse voltage UZ is reached. If an attempt is made to increase the voltage U even further, the current through the arrangement rises sharply due to the zener breakdowns in the individual transitions between the semiconductor layers. Since the arrangement is symmetrical, the same electrical behavior occurs when the polarity of the applied voltage U is reversed with the opposite sign. For n P-doped epitaxial layers and n N-doped epitaxial layers, the breakdown voltage UZ is:

UZ = n x (UZ1 + UF).

UZ1 is the breakdown voltage of a single junction, and UF is the forward voltage of a single PN diode. The solid line in Figure 2 shows the current-voltage behavior of the arrangement at room temperature (RT). The broken line shows the behavior at a high temperature (HT). It can be seen that up to very high currents there is practically no influence on the characteristic curve due to the temperature. Only at very high current densities, for example in the range above 200 A / cm ² , is there again a non-negligible positive temperature coefficient.

FIG. 3 shows the doping profile of the arrangement from FIG. 1, the number density of the doping atoms N being plotted against the location x. The solid lines indicate N-doped silicon. The dotted lines indicate P-doped silicon. The left side of the diagram in FIG. 3 corresponds to the N-doped silicon layer from FIG. 1, which adjoins the metal electrode 18, while the right side of the diagram in FIG. 3 corresponds to the substrate 10 from FIG. 1, which extends from the metal electrode 16 Figure 1 is adjacent. It can be seen that there is a constant doping concentration of 2 × 10 ¹⁹ atoms / cm ³ . FIG. 4 schematically shows a cross section of a further embodiment of an arrangement according to the invention, which likewise results in voltage limitation with any voltage polarity. It was mentioned that the arrangement according to FIG. 1 has a symmetrical characteristic curve with regard to the polarity of the applied voltage. By contrast, the arrangement shown in FIG. 4 achieves an asymmetrical characteristic curve. The special feature of this arrangement is that there are two types of P-doped semiconductor layers. A first P-doped semiconductor layer 20 has a lower doping concentration than a second P ^{^} -doped semiconductor layer 22. The doping concentration of the N semiconductor layers is uniform. This gives diodes with different

Breakdown voltages, corresponding to the transitions N (P ⁺ P) or (P ⁺ P) N. If the diodes are loaded in the reverse direction, the breakdown voltage UZl is the

(P ⁺ P) N — Diode greater than the breakdown voltage UZ2 of the N (P ⁺ P) diode. With n transitions, with a positive voltage at the metal contact 18 with respect to the metal contact 16, a breakdown voltage of

UZ = n x (UZ2 + UF).

If the polarity of the voltage is reversed, the breakdown voltage results

UZ = -n x (UZl + UF).

The arrangement according to FIG. 4 is also with regard to the outermost semiconductor layers and with regard to the Animal types principally variable. A P substrate can also be used instead of an N substrate. Accordingly, higher doped N ⁺ layers and less highly doped N layers would be used for a P substrate. The outermost layers of the semiconductor arrangement can in turn match or differ with regard to the doping type.

FIG. 5 shows a characteristic curve of an arrangement according to FIG. 4. With suitable dimensions, both with regard to the geometry and with regard to the concentrations, characteristic curves that are practically independent of temperature are obtained again, which is shown in FIG. 5. Figure 5 corresponds in its basic structure to Figure 2, but here the asymmetrical characteristic curve is decisive.

The preceding description of the exemplary embodiments according to the present invention is only for illustrative purposes and not for the purpose of restricting the invention. Various changes and modifications are possible within the scope of the invention without leaving the scope of the invention and its equivalents.

Claims

Expectations

1. Arrangement with P-doped semiconductor layers (12, 20, 22) and N-doped semiconductor layers (14, 10), which between the P-doped semiconductor layers (12, 20, 22) and the N-doped semiconductor layers (14, 10 ) Has transitions, the transitions showing a Zener breakdown when a voltage characteristic of a transition is applied, characterized in that a plurality of transitions between P-doped semiconductor layers (12, 20, 22) and N-doped semiconductor layers (14, 10 ) is present and that the characteristic voltages are added to the breakdown voltage of the entire arrangement.

2. Arrangement according to claim 1, characterized in that the semiconductor layers (10, 12, 14, 20, 22) are heavily doped.

3. Arrangement according to claim 1 or 2, characterized in that the semiconductor layers (10, 12, 1, 20) have a constant doping.

4. Arrangement according to one of the preceding claims, characterized in that the P-doped semiconductor layers (12) and the N-doped semiconductor layers (14) are doped with the same concentration.

5. Arrangement according to one of the preceding claims, characterized in that the P-doped semiconductor layers (20, 22) form at least two groups which are doped with different concentrations.

6. Arrangement according to one of the preceding claims, characterized in that the N-doped semiconductor layers form at least two groups which are doped with different concentrations.

7. Arrangement according to one of the preceding claims, characterized in that the semiconductor layers (12, 14, 20, 22) are arranged on an N-doped substrate (10).

8. Arrangement according to one of the preceding claims, characterized in that the semiconductor layers are arranged on a P-doped substrate.

9. Arrangement according to one of the preceding claims, characterized in that the type of doping of the most distant semiconductor layer from the substrate (10) corresponds to the type of doping of the substrate (10).

10. Arrangement according to one of the preceding claims, characterized in that the type of doping of the most distant semiconductor layer from the substrate is different than the type of doping of the substrate.

11. Arrangement according to one of the preceding claims, characterized in that the semiconductor layers (12, 14, 20, 22) have a thickness of about 4 microns.

12. Arrangement according to one of the preceding claims, characterized in that the substrate (10) has a thickness of about 500 microns.

13. Arrangement according to one of the preceding claims, characterized in that the concentration of the doping is in the range of 2 x 10 ¹⁹ atoms / cm ³ .

14. Arrangement according to one of the preceding claims, characterized in that about 10 transitions between P-doped semiconductor layers (12) and N-doped semiconductor layers (14) are provided.

15. Arrangement according to one of the preceding claims, characterized in that it has on its top and on its underside metal contacts (16, 18) which extend over their entire surface.

16. Arrangement according to one of the preceding claims, characterized in that the semiconductor layers (10, 12, 20, 22) are silicon layers.

17. A method for producing an arrangement with P-doped semiconductor layers (12, 20, 22) and N-doped semiconductor layers (14, 10), which between the P-doped semiconductor layers (12, 20, 22) and the N-doped semiconductor layers (14, 10) transitions, the transitions showing a Zener breakdown when a voltage characteristic of a transition is applied, a plurality of transitions between P-doped semiconductor layers (12, 20, 22) and N- doped semiconductor layers (14, 10) is present and the characteristic voltages are added to the breakdown voltage of the entire arrangement, the method comprising the application of the semiconductor layers (12, 14, 20, 22) by epitaxy.

18. The method according to claim 17, characterized in that the epitaxy takes place at about 1180 ° C.

19. The method according to claim 17 or 18, characterized in that the epitaxy takes place at a growth rate of about 4 microns / min.

20. The method according to any one of claims 17 to 19, characterized in that metal contacts (16, 18) are sputtered onto the top and the bottom of the arrangement.

21. The method according to any one of claims 17 to 20, characterized in that the arrangement after sputtering the metal contacts (16, 18) is divided into individual chips.

22. The method according to any one of claims 17 to 21, characterized in that the edges of the chips are removed.

23. The method according to any one of claims 17 to 22, characterized in that thin silicon wafers are joined together by afer bonding.