EP1191601A1 - A lateral DMOS transistor - Google Patents

A lateral DMOS transistor Download PDF

Info

Publication number
EP1191601A1
EP1191601A1 EP00830628A EP00830628A EP1191601A1 EP 1191601 A1 EP1191601 A1 EP 1191601A1 EP 00830628 A EP00830628 A EP 00830628A EP 00830628 A EP00830628 A EP 00830628A EP 1191601 A1 EP1191601 A1 EP 1191601A1
Authority
EP
European Patent Office
Prior art keywords
transistor
region
voltage
electrode
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00830628A
Other languages
German (de)
French (fr)
Other versions
EP1191601B1 (en
Inventor
Nicola Zatelli
Massimo Atti
Elisabetta Palumbo
Cosimo Torelli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Priority to EP00830628A priority Critical patent/EP1191601B1/en
Priority to DE60037248T priority patent/DE60037248T2/en
Priority to US09/960,254 priority patent/US6624471B2/en
Publication of EP1191601A1 publication Critical patent/EP1191601A1/en
Application granted granted Critical
Publication of EP1191601B1 publication Critical patent/EP1191601B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Definitions

  • the present invention relates to semiconductor devices and, more particularly, to a lateral DMOS, field-effect transistor as defined in the preamble of Claim 1.
  • a lateral DMOS (double-diffused metal-oxide semiconductor) transistor in which the drain region has a portion with a low concentration of impurities, known as a "drift” or “drain extension” region, is known.
  • Figures 1 and 2 show, in plan and in section respectively, a transistor of this type which constitutes part of an integrated circuit formed in a silicon substrate, indicated 10.
  • a p-type region 11 formed in the substrate 10 constitutes the body region of the transistor.
  • Various active areas are defined on the front surface of the substrate 10 and are insulated from one another by silicon dioxide (field oxide) plaques 12.
  • the plaques 12 may be formed, for example, by conventional techniques for the selective oxidation of the silicon.
  • An n-type region 14 having a high concentration and indicated N+ extends in the region 13, wholly occupying an active area, and constitutes the high-concentration portion of the drain region.
  • a metal element 15 in contact with the region 14 constitutes the drain electrode D of the transistor.
  • Another high-concentration n-type region 16 extends in the body region 11 and delimits, with the region 13, a channel 17.
  • a metal element 18 in contact with the region 16 constitutes the source electrode S of the transistor.
  • a strip 19 of electrically conductive material extends over the channel region and over a portion of the drift region 13 to form the gate electrode of the transistor.
  • This strip is separated from the front surface of the substrate 10 by a thin layer 9 of insulating material which constitutes the gate dielectric.
  • the strip 19 also extends partially over the plaque 12 which separates the two active areas in which the transistor is formed and, on top of the strip 19, there is a metal contact element 20 of the gate G.
  • a p-type region 21 with a high concentration of impurities extends in the body region 11 to ensure an ohmic contact between this region and a metal element 22 which constitutes the body electrode B of the transistor.
  • the conductivity of the channel that is, of the portion of the body region 11 beneath the gate electrode, is reversed so that a current can pass between the source electrode 18 and the drain electrode 15.
  • the drift region 13 acts as a resistance distributed between the drain electrode 15 and the channel region 17 so that the potential of the drain region in the vicinity of the channel is lower than the drain-electrode potential.
  • This transistor can be formed by the same method as is used for conventional MOS and CMOS transistors of low-voltage logic circuits (2-3V) but, by virtue of the characteristic described above, can be used with higher supply voltages (7-8V). Some circuits which have to be supplied with high voltages, for example, control circuits for non-volatile memories, can therefore be produced with a smaller number of components and hence in smaller areas of the integrated circuit with the use of transistors of this type.
  • the object of the present invention is to propose a lateral DMOS transistor which does not have the limitations described above.
  • Figure 3 in which elements identical or corresponding to those of Figure 1 are indicated by the same reference numerals, shows a lateral DMOS transistor according to the invention.
  • the cross-section of Figure 2 is also valid for the transistor according to the invention.
  • the latter differs from the known transistor shown in Figures 1 and 2 in that it comprises an additional contact electrode disposed on the drift region 13 at a point closer to the channel region 17 than to the high-concentration portion 14 of the drain region.
  • the additional electrode, indicated 25 is in contact with the drift region by means of a high-concentration n-type region, indicated 26 in Figure 4.
  • the additional electrode 15 is disposed beside the channel at a point at which it does not affect the conduction of the transistor and does not modify the effective width of the transistor.
  • the additional electrode permits a direct measurement of the potential of the drain region at a point very close to the channel. By taking such a measurement, the designer can thus obtain information useful for characterizing the transistor and for selecting its dimensions, and can thus optimize the electrical performance and the reliability both of the transistor itself and of the whole integrated circuit containing the transistor.
  • the information can be stored in a register to be used in the design of the integrated circuit or may be used directly by activating a protection circuit for preventing the application of excessive voltages to some components of the integrated circuit.
  • FIG. 5 shows, in schematic form, an advantageous application of the transistor according to the invention, more precisely, a row decoder of an EPROM memory.
  • a generic EPROM cell, indicated 30, of a matrix of cells not shown further, has its gate terminal connected to the output of a high-voltage driver circuit 31.
  • the amplitude of the voltage supplied by the driver circuit 31 is determined by a ramp-voltage generator 32.
  • a switching device 33 controlled by a control logic circuit of the memory can supply to the ramp-voltage generator 32 a high supply voltage VH or a low supply voltage VL.
  • the high supply voltage VH is supplied by a voltage supply 34, for example, a charge pump, by means of a voltage regulator 35.
  • circuits of the row decoder advantageously use lateral DMOS transistors to withstand the fairly high voltages (7-8V) necessary to polarize the row of the matrix.
  • the circuits 31, 32 and 33 comprise transistors of the type shown in Figures 1 and 2 and the regulator 35 comprises at least one transistor TR according to the invention, such as that shown in Figures 3 and 4, supplied with the voltage provided by the supply 34.
  • the circuits 31-33 are designed so as to take account of the fact that the potential of the drift region 13 in the vicinity of the channel 17 cannot be known precisely, as explained above with reference to Figures 1 and 2, so that the voltage between the sources and the drains of the lateral DMOS transistors has to be kept prudently low. Moreover, according to the prior art, it is necessary to take appropriate steps to protect the circuits from possible supply overvoltages and this requires limiters and other additional circuits.
  • the transistor TR has its additional drain terminal, indicated D2, connected to a first input terminal of a comparator 36.
  • a second input terminal of the comparator is connected to a voltage supply 37 which generates a constant voltage Vlim that can be set at the design stage at a safety value below the breakdown voltage of the gate dielectric.
  • the output of the comparator is connected to the regulator 35. If the voltage at the additional terminal D2 is equal to or greater than the voltage Vlim, for example, because of a transient pulse in the supply 34, a signal appears at the output of the comparator 36 and activates suitable means, contained in the regulator 35, for protecting the transistor TR, for example, a limiter (not shown).
  • the output of the comparator is also connected to the switching circuit 33 so that, in the event of overvoltages in the supply 34, the switch is activated and the high-voltage supply VH of the circuits 31, 32, and 33 is interrupted.
  • the output signal of the comparator 36 can also be used to activate specific protection means of the lateral DMOS transistors.
  • the use of the transistor according to the invention enables maximum use to be made of the advantageous characteristics of lateral DMOS transistors, by virtue of the fact that the additional terminal of the transistor TR permits a precise knowledge not only of the maximum voltage which can be withstood by the transistor TR, but also of that which can be withstood by lateral DMOS transistors without additional terminals.

Abstract

A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.
Figure 00000001

Description

  • The present invention relates to semiconductor devices and, more particularly, to a lateral DMOS, field-effect transistor as defined in the preamble of Claim 1.
  • A lateral DMOS (double-diffused metal-oxide semiconductor) transistor in which the drain region has a portion with a low concentration of impurities, known as a "drift" or "drain extension" region, is known. Figures 1 and 2 show, in plan and in section respectively, a transistor of this type which constitutes part of an integrated circuit formed in a silicon substrate, indicated 10. A p-type region 11 formed in the substrate 10 constitutes the body region of the transistor. Various active areas are defined on the front surface of the substrate 10 and are insulated from one another by silicon dioxide (field oxide) plaques 12. The plaques 12 may be formed, for example, by conventional techniques for the selective oxidation of the silicon. An n-type region 13 having a low concentration of impurities and indicated N-, extends in the body region 11 partially beneath a field oxide plaque 12 and constitutes the drift region of the transistor. An n-type region 14 having a high concentration and indicated N+ extends in the region 13, wholly occupying an active area, and constitutes the high-concentration portion of the drain region. A metal element 15 in contact with the region 14 constitutes the drain electrode D of the transistor. Another high-concentration n-type region 16 extends in the body region 11 and delimits, with the region 13, a channel 17. A metal element 18 in contact with the region 16 constitutes the source electrode S of the transistor. A strip 19 of electrically conductive material, for example, doped polycrystalline silicon, extends over the channel region and over a portion of the drift region 13 to form the gate electrode of the transistor. This strip is separated from the front surface of the substrate 10 by a thin layer 9 of insulating material which constitutes the gate dielectric. The strip 19 also extends partially over the plaque 12 which separates the two active areas in which the transistor is formed and, on top of the strip 19, there is a metal contact element 20 of the gate G. A p-type region 21 with a high concentration of impurities extends in the body region 11 to ensure an ohmic contact between this region and a metal element 22 which constitutes the body electrode B of the transistor.
  • As is known, when a voltage above a predetermined threshold is applied between the gate and body electrodes, the conductivity of the channel, that is, of the portion of the body region 11 beneath the gate electrode, is reversed so that a current can pass between the source electrode 18 and the drain electrode 15. In these conditions, the drift region 13 acts as a resistance distributed between the drain electrode 15 and the channel region 17 so that the potential of the drain region in the vicinity of the channel is lower than the drain-electrode potential.
  • This transistor can be formed by the same method as is used for conventional MOS and CMOS transistors of low-voltage logic circuits (2-3V) but, by virtue of the characteristic described above, can be used with higher supply voltages (7-8V). Some circuits which have to be supplied with high voltages, for example, control circuits for non-volatile memories, can therefore be produced with a smaller number of components and hence in smaller areas of the integrated circuit with the use of transistors of this type.
  • However, it is not possible to make the best use of the advantageous characteristics of the transistor described above because the voltage drop in the drift region when the transistor is conducting cannot be evaluated precisely at the stage of the design of the integrated circuit, because of the variability of the production parameters. To avoid the risk of the electric field formed between the gate electrode 19 and the drift region 13 in the vicinity of the channel 17 adopting values which are dangerous to the integrity of the gate dielectric 9, the device therefore has to be designed with quite large safety margins.
  • The object of the present invention is to propose a lateral DMOS transistor which does not have the limitations described above.
  • This object is achieved by the provision of the transistor defined and characterized in general in Claim 1.
  • The invention and the advantages resulting therefrom are described in detail below with reference to an embodiment thereof which is described by way of nonlimiting example with reference to the appended drawings, in which:
  • Figure 1 is a plan view of a known lateral DMOS transistor,
  • Figure 2 is a section taken on the line II-II of Figure 1,
  • Figure 3 is a plan view of a lateral DMOS transistor according to the invention,
  • Figure 4 is a section taken on the line IV-IV of Figure 3, and
  • Figure 5 shows, in schematic form, a portion of an integrated circuit in which the transistor according to the invention is used.
  • Figure 3, in which elements identical or corresponding to those of Figure 1 are indicated by the same reference numerals, shows a lateral DMOS transistor according to the invention. It will be noted that the cross-section of Figure 2 is also valid for the transistor according to the invention. The latter differs from the known transistor shown in Figures 1 and 2 in that it comprises an additional contact electrode disposed on the drift region 13 at a point closer to the channel region 17 than to the high-concentration portion 14 of the drain region. The additional electrode, indicated 25, is in contact with the drift region by means of a high-concentration n-type region, indicated 26 in Figure 4. The additional electrode 15 is disposed beside the channel at a point at which it does not affect the conduction of the transistor and does not modify the effective width of the transistor.
  • The additional electrode permits a direct measurement of the potential of the drain region at a point very close to the channel. By taking such a measurement, the designer can thus obtain information useful for characterizing the transistor and for selecting its dimensions, and can thus optimize the electrical performance and the reliability both of the transistor itself and of the whole integrated circuit containing the transistor.
  • The information can be stored in a register to be used in the design of the integrated circuit or may be used directly by activating a protection circuit for preventing the application of excessive voltages to some components of the integrated circuit.
  • Figure 5 shows, in schematic form, an advantageous application of the transistor according to the invention, more precisely, a row decoder of an EPROM memory. A generic EPROM cell, indicated 30, of a matrix of cells not shown further, has its gate terminal connected to the output of a high-voltage driver circuit 31. The amplitude of the voltage supplied by the driver circuit 31 is determined by a ramp-voltage generator 32. A switching device 33 controlled by a control logic circuit of the memory (not shown) can supply to the ramp-voltage generator 32 a high supply voltage VH or a low supply voltage VL. The high supply voltage VH is supplied by a voltage supply 34, for example, a charge pump, by means of a voltage regulator 35. The circuits of the row decoder advantageously use lateral DMOS transistors to withstand the fairly high voltages (7-8V) necessary to polarize the row of the matrix. More particularly, the circuits 31, 32 and 33 comprise transistors of the type shown in Figures 1 and 2 and the regulator 35 comprises at least one transistor TR according to the invention, such as that shown in Figures 3 and 4, supplied with the voltage provided by the supply 34.
  • According to the prior art, the circuits 31-33 are designed so as to take account of the fact that the potential of the drift region 13 in the vicinity of the channel 17 cannot be known precisely, as explained above with reference to Figures 1 and 2, so that the voltage between the sources and the drains of the lateral DMOS transistors has to be kept prudently low. Moreover, according to the prior art, it is necessary to take appropriate steps to protect the circuits from possible supply overvoltages and this requires limiters and other additional circuits.
  • These limitations of the prior art are completely eliminated with the use of the transistor according to the invention, as explained below.
  • The transistor TR has its additional drain terminal, indicated D2, connected to a first input terminal of a comparator 36. A second input terminal of the comparator is connected to a voltage supply 37 which generates a constant voltage Vlim that can be set at the design stage at a safety value below the breakdown voltage of the gate dielectric. The output of the comparator is connected to the regulator 35. If the voltage at the additional terminal D2 is equal to or greater than the voltage Vlim, for example, because of a transient pulse in the supply 34, a signal appears at the output of the comparator 36 and activates suitable means, contained in the regulator 35, for protecting the transistor TR, for example, a limiter (not shown). In the embodiment shown, the output of the comparator is also connected to the switching circuit 33 so that, in the event of overvoltages in the supply 34, the switch is activated and the high-voltage supply VH of the circuits 31, 32, and 33 is interrupted. Alternatively, the output signal of the comparator 36 can also be used to activate specific protection means of the lateral DMOS transistors.
    As can be appreciated, the use of the transistor according to the invention enables maximum use to be made of the advantageous characteristics of lateral DMOS transistors, by virtue of the fact that the additional terminal of the transistor TR permits a precise knowledge not only of the maximum voltage which can be withstood by the transistor TR, but also of that which can be withstood by lateral DMOS transistors without additional terminals. In fact, these are produced in the same integrated circuit by exactly the same process and are therefore identical to the transistor TR with regard to the maximum voltage which they can withstand. Moreover, in view of the fact that the function of protection against overvoltages in the supply is performed upstream of the circuits 31-33, specific circuit devices for protecting the individual circuits are not necessary. Finally, with the transistor according to the invention, it is possible to produce circuits which are simpler and hence smaller than known circuits.

Claims (7)

  1. A lateral DMOS transistor comprising a substrate of semiconductor material (10) having a front surface,
    a body region (11) with a first type of conductivity (p), extending in the substrate from the front surface,
    a source region (16) and a drain region (13, 14) with a second type of conductivity (n), extending in the body region (11) from the front surface and delimiting a channel region (17) between them,
    a gate electrode (19) which extends over the channel region (17) and is insulated from the front surface by a layer of dielectric material (9), and
    a body electrode (B), a source electrode (S), and a drain electrode (D) which are in contact with the body region (11), the source region (16), and the drain region (13, 14), respectively,
    the drain region (13, 14) comprising a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region (17),
       characterized in that the transistor comprises an additional electrode (25) in contact with the low-concentration portion (13) of the drain region (13, 14) at a point closer to the channel region (17) than to the high-concentration portion (14) of the drain region.
  2. A transistor according to Claim 1 in which the additional electrode (25) is disposed beside the channel region (17).
  3. An integrated circuit comprising at least one transistor according to Claim 1 or Claim 2, further comprising a voltage comparator (36), a source (37) of a limit voltage (Vlim), and means for protecting the transistor against overvoltages, in which the comparator has a first input terminal connected to the additional electrode (D2) of the transistor, a second input terminal connected to the source (37) of the limit voltage, and an output terminal connected to the means for protecting the transistor (TR), and can generate an output signal when the voltage at its first input terminal is greater than the voltage at its second input terminal.
  4. An integrated circuit according to Claim 3 in which the protection means comprise a voltage limiter.
  5. An integrated circuit according to Claim 3 or Claim 4, comprising at least one transistor according to the preamble to Claim 1 and further means for protecting this latter transistor against overvoltages, in which the output terminal of the comparator (36) is also connected to the further protection means.
  6. An integrated circuit according to Claim 5, comprising a row decoder of an EPROM memory having at least one voltage regulator (35) comprising a transistor according to Claim 1 or Claim 2 and at least one circuit (31, 32, 33) comprising at least one transistor according to the preamble of Claim 1.
  7. An integrated circuit according to Claim 6, in which the further protection means comprise at least one switching device (33).
EP00830628A 2000-09-21 2000-09-21 A lateral DMOS transistor Expired - Lifetime EP1191601B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00830628A EP1191601B1 (en) 2000-09-21 2000-09-21 A lateral DMOS transistor
DE60037248T DE60037248T2 (en) 2000-09-21 2000-09-21 Lateral DMOS transistor arrangement
US09/960,254 US6624471B2 (en) 2000-09-21 2001-09-20 Lateral DMOS transistor with first and second drain electrodes in respective contact with high-and low-concentration portions of a drain region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00830628A EP1191601B1 (en) 2000-09-21 2000-09-21 A lateral DMOS transistor

Publications (2)

Publication Number Publication Date
EP1191601A1 true EP1191601A1 (en) 2002-03-27
EP1191601B1 EP1191601B1 (en) 2007-11-28

Family

ID=8175486

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00830628A Expired - Lifetime EP1191601B1 (en) 2000-09-21 2000-09-21 A lateral DMOS transistor

Country Status (3)

Country Link
US (1) US6624471B2 (en)
EP (1) EP1191601B1 (en)
DE (1) DE60037248T2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006033692B4 (en) * 2006-07-20 2011-01-05 Austriamicrosystems Ag A method of fabricating a patterned dielectric for an LDMOS transistor
DE102011087845A1 (en) * 2011-12-06 2013-06-06 Infineon Technologies Ag LATERAL TRANSISTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7602019B2 (en) * 2006-04-20 2009-10-13 Texas Instruments Incorporated Drive circuit and drain extended transistor for use therein

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019560A1 (en) * 1979-05-21 1980-11-26 ETAT FRANCAIS repr. par le Secrétaire d'Etat aux Postes & Télécommunications (Centre National d'Etudes des Télécommunications) Multiple-drain MOS transistor logic gates
EP0035453A1 (en) * 1980-03-04 1981-09-09 Thomson-Csf Insulated gate field effect transistor structure and use in logic gates
EP0267768A1 (en) * 1986-11-10 1988-05-18 SILICONIX Incorporated High voltage drifted-drain MOS transistor
US4977434A (en) * 1987-07-31 1990-12-11 Thomson Hybrides Et Microondes Field-effect semiconductor device comprising an ancillary electrode
US6002301A (en) * 1996-11-18 1999-12-14 Matsushita Electronics Corporation Transistor and power amplifier

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303961B1 (en) * 1998-04-29 2001-10-16 Aqere Systems Guardian Corp. Complementary semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019560A1 (en) * 1979-05-21 1980-11-26 ETAT FRANCAIS repr. par le Secrétaire d'Etat aux Postes & Télécommunications (Centre National d'Etudes des Télécommunications) Multiple-drain MOS transistor logic gates
EP0035453A1 (en) * 1980-03-04 1981-09-09 Thomson-Csf Insulated gate field effect transistor structure and use in logic gates
EP0267768A1 (en) * 1986-11-10 1988-05-18 SILICONIX Incorporated High voltage drifted-drain MOS transistor
US4977434A (en) * 1987-07-31 1990-12-11 Thomson Hybrides Et Microondes Field-effect semiconductor device comprising an ancillary electrode
US6002301A (en) * 1996-11-18 1999-12-14 Matsushita Electronics Corporation Transistor and power amplifier

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006033692B4 (en) * 2006-07-20 2011-01-05 Austriamicrosystems Ag A method of fabricating a patterned dielectric for an LDMOS transistor
DE102011087845A1 (en) * 2011-12-06 2013-06-06 Infineon Technologies Ag LATERAL TRANSISTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
CN103151377A (en) * 2011-12-06 2013-06-12 英飞凌科技股份有限公司 Lateral transistor component and method for producing same
DE102011087845B4 (en) * 2011-12-06 2015-07-02 Infineon Technologies Ag LATERAL TRANSISTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
CN103151377B (en) * 2011-12-06 2016-01-06 英飞凌科技股份有限公司 Lateral transistor component and manufacture method thereof

Also Published As

Publication number Publication date
DE60037248T2 (en) 2008-10-09
US20020040995A1 (en) 2002-04-11
DE60037248D1 (en) 2008-01-10
US6624471B2 (en) 2003-09-23
EP1191601B1 (en) 2007-11-28

Similar Documents

Publication Publication Date Title
JP4756557B2 (en) Semiconductor device
CN107527904B (en) Semiconductor integrated circuit device with a plurality of semiconductor chips
JP3911566B2 (en) MOS type semiconductor device
US5079608A (en) Power MOSFET transistor circuit with active clamp
US20080017920A1 (en) Structure and method for improving shielded gate field effect transistors
US20050286194A1 (en) Power transistor device and a power control system for using it
EP2187441A1 (en) Switching device for electric circuit
JPH0666472B2 (en) MOSFET with overcurrent protection function
US4481521A (en) Insulated gate field effect transistor provided with a protective device for a gate insulating film
US6924532B2 (en) Field-effect power transistor
EP1469523B1 (en) A junction electronic component and an integrated power device incorporating said component
EP0562352B1 (en) High voltage structures with oxide isolated source and RESURF drift region in bulk silicon
EP1168449A2 (en) Zweipol-halbleiter-überstromschutz
US5089871A (en) Increased voltage mos semiconductor device
JP4431761B2 (en) MOS type semiconductor device
JP2002517116A (en) Smart power element
EP1191601B1 (en) A lateral DMOS transistor
JP3489404B2 (en) Insulated gate semiconductor device
US5162883A (en) Increased voltage MOS semiconductor device
DE102014119544B4 (en) semiconductor device
US5895959A (en) Input port electrostatic discharge protection circuit for an intergrated circuit
JP2004228317A (en) Semiconductor memory device
KR19990087142A (en) Semiconductor device
JPS61214576A (en) Semiconductor device
JP3431127B2 (en) Electronic device and electronic switch device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20020724

AKX Designation fees paid

Free format text: DE FR GB IT

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REF Corresponds to:

Ref document number: 60037248

Country of ref document: DE

Date of ref document: 20080110

Kind code of ref document: P

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20080829

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20080929

Year of fee payment: 9

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20080921

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080921

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20100531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090930

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080930

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 60037248

Country of ref document: DE

Representative=s name: KLUNKER, SCHMITT-NILSON, HIRSCH, DE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 60037248

Country of ref document: DE

Representative=s name: SCHMITT-NILSON SCHRAUD WAIBEL WOHLFROM PATENTA, DE

Effective date: 20131209

Ref country code: DE

Ref legal event code: R081

Ref document number: 60037248

Country of ref document: DE

Owner name: MICRON TECHNOLOGY, INC., US

Free format text: FORMER OWNER: STMICROELECTRONICS S.R.L., AGRATE BRIANZA, IT

Effective date: 20131209

Ref country code: DE

Ref legal event code: R082

Ref document number: 60037248

Country of ref document: DE

Representative=s name: KLUNKER, SCHMITT-NILSON, HIRSCH, DE

Effective date: 20131209

Ref country code: DE

Ref legal event code: R081

Ref document number: 60037248

Country of ref document: DE

Owner name: MICRON TECHNOLOGY, INC., BOISE, US

Free format text: FORMER OWNER: STMICROELECTRONICS S.R.L., AGRATE BRIANZA, MAILAND/MILANO, IT

Effective date: 20131209

Ref country code: DE

Ref legal event code: R081

Ref document number: 60037248

Country of ref document: DE

Owner name: MICRON TECHNOLOGY, INC., BOISE, US

Free format text: FORMER OWNER: STMICROELECTRONICS S.R.L., AGRATE BRIANZA, IT

Effective date: 20131209

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 60037248

Country of ref document: DE

Representative=s name: SCHMITT-NILSON SCHRAUD WAIBEL WOHLFROM PATENTA, DE

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20191129

Year of fee payment: 20

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 60037248

Country of ref document: DE