EP1179243A1 - Moteur cryptographique utilisant la conversion de base de numeration, des operations logiques et un generateur de nombres pseudo-aleatoires pour des matrices de donnees de fa on a augmenter la dispersion dans le texte chiffre - Google Patents

Moteur cryptographique utilisant la conversion de base de numeration, des operations logiques et un generateur de nombres pseudo-aleatoires pour des matrices de donnees de fa on a augmenter la dispersion dans le texte chiffre

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Publication number
EP1179243A1
EP1179243A1 EP99927081A EP99927081A EP1179243A1 EP 1179243 A1 EP1179243 A1 EP 1179243A1 EP 99927081 A EP99927081 A EP 99927081A EP 99927081 A EP99927081 A EP 99927081A EP 1179243 A1 EP1179243 A1 EP 1179243A1
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EP
European Patent Office
Prior art keywords
array
elements
att
data
byte
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99927081A
Other languages
German (de)
English (en)
Other versions
EP1179243A4 (fr
Inventor
Richard C. Satterfield
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
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Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority claimed from PCT/US1999/010967 external-priority patent/WO2000070819A1/fr
Publication of EP1179243A1 publication Critical patent/EP1179243A1/fr
Publication of EP1179243A4 publication Critical patent/EP1179243A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/04—Masking or blinding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Definitions

  • the present invention relates to apparatus and methods for encryption and decryption wherein a ciphertext is generated. More particularly, the present invention is related to the use of symrnetrix private key incryption. This invention contains changes which improve the security of the resulting ciphertext and well as features which aid in masking the arrays used to encrypt information from statistical analysis of the ciphertext.
  • ENCIPHERING DEVICE describes in the abstract: "A substitution-permutation enciphering device. This device, adapted for transforming a binary word into another binary word, by succession of substitutions and permutations, under the control of a key ... " This use of a substitution memory as described by US 4,751,733 has a limitation in that this patent discloses and teaches changes only to the bits of a byte.
  • US PATENT 5,412,729 entitled “DEVICE AND METHOD FOR DATA ENCRYPTION” introduces the concept of using matrix operations to multiplex the bytes in the cleartext so that the a byte in the ciphertext may contain elements of more than one cleartext bytes.
  • the patent teaches about the multiple use of a data element to create a ciphertext element. This is different from the combination of: creating a single working element by concatenating several bytes together (with permutation of sequence during the concatenation), binary rotating the resultant single element, and the breaking up the single element back into multiple bytes to be placed in an output buffer (also with permutation of sequence).
  • a matrix presentation may be used to represent the effect of the rotation operation.
  • the moduli (m,) are chosen to be relatively prime to each other.
  • the Madryga consists of two nested cycles. The outer cycles repeats eight time (although this could be increased if security warrants) and consists of an application of the inner cycle to the plaintext.
  • the inner cycle transforms plaintext to ciphertext and repeats once for each 8-bit block (byte) of the plaintext.
  • An iteration of the inner cycle operates on a 3 -byte window of data, called the working frame [figure reference omitted]. This window advances 1 byte for each iteration.
  • the data are considered circular when dealing with the last 2 bytes.
  • the first 2 bytes of the working frame are together rotated a variable number of positions, while the last byte is XORed with some key bits.
  • all bytes are successively rotated and XORed with key material. Successive rotations overlap the results of a previous XOR and rotation, and the data from the XOR is used to influence the rotation. This makes the entire process reversible. Because every byte of data influences the 2 bytes to its left and the 1 byte to its right, after eight passes every byte of the ciphertext is dependent upon 16 bytes to the left and 8 bytes to the right.
  • each iteration of the inner cycle starts the working frame at the next-to-last byte of the plaintext and advances circularly through to the third-to-last byte of the plaintext.
  • the entire key is XORed with a random constant and then rotated to the left 3 bits.
  • the low-order 3 bits of the low-order byte of the working frame are saved; they will control the rotation of the other 2 bytes.
  • the low-order byte of the working frame is XORed with the low-order byte of the key.
  • the concatenation of the 2 high-order bytes are rotated to the left the variable number of bits (0 to 7).
  • engine decoder, and encryptor are used interchangeably herein.
  • a relative address pointer (rap or RAP) is defined herein as relative address index, pointing to an entry within a table of bytes, an array of bytes or an I/O buffer.
  • RAP relative address pointer
  • That counter is constructed so that it counts modulo the size of the I/O Buffer, Mask Array, or table with which it is associated.
  • an ordinary binary counter may usually be used to supply the relative address pointers.
  • RAP relative address pointer
  • ATT Operations This will mean the converting of a relative address pointer (RAP) into a scrambled relative address pointer (SRAP).
  • RAP relative address pointer
  • SRAP scrambled relative address pointer
  • ATT Entries, or ATT Block Entries, or ATT Blocks are defined herein as tables of relative address pointers or modified relative index values 2 in size, having values of 0 to 2 -1.
  • Other sized ATT Block Entries may be used for non- power-of 2 XORn and ATT Block Entry Modulo operations.
  • an ATT Block of 1014 entries will use an XORn (based 13) and a Modulo operation of 1014.
  • Each ATT Block contains only 1 unique value in its range. There are no duplicate entry values and thus an ATT Block is completely different from a thesaurus as defined in either US 5,113,444 or US 5,307,412. because no synonyms or duplicate entries are present.
  • the size of the I/O buffers and Masking Arrays should be an integer multiple of the ATT Block Entries to be used with them. Thus if a ATT Block Entry for I/O is 1000, then the I/O Buffers should be integer multiples of 1000 bytes in size. If the masking arrays are 64K in size, then a ATT Block Entry for them should be a power of 2 in size less than or equal to 64K.
  • a buffer size of 1014 is interesting if 3 byte (24 bit wide) arithmetic/logic operations are chosen.
  • ATT Column is defined herein as a collection of one or more ATT Blocks used one at a time so that even though the collection of multiple ATT Blocks all contain the same entries, though probably in a different order, they are not a table of Synonyms as defined by either US 5,113,444 or US 5,307,412. Also these ATT Blocks are used to modify the value of a relative address pointers and not the data to be encrypted or decrypted as is done by these patents.
  • ATTN is the number of ATT Blocks in an ATT Column.
  • ATTSIZE is the ATT Block size within an ATT Column and ATT BASE is the number base for the XORn masking operations to be used with the ATT Block size.
  • ATTB is the number of the ATT Block Entry being used (counting from 0 upwards) within an ATT Column.
  • an Address Translation Table consists of one or more ATT columns.
  • MF's Multiple byte fetches
  • MF Multiple byte fetches
  • Decatenation or decatenate are defined herein as the breaking apart of a single multibyte width entity, previously created by the concatenation of individual bytes, back into individual bytes.
  • MP Multiple byte put
  • a byte is defined herein as being of any width greater than or equal to 2 bits.
  • a barrel shifter is defined herein as a shift register arranged such that any bits shifted off either end of the register are also shifted back in the other end of the shift register at the same time. No information is added, lost or changed in the process.
  • a barrel shifter may also be constructed using a simple latch register and multiple selects for the inputs to the latch creating a barrel shifter which only requires one clock period to perform any size rotate. Rotation can also be performed in a register within most typical CPUs. Usually, there is an instruction native to the CPU which will perform this operation.
  • rotation rotational operation
  • rotation operation rotation operation
  • an encoder pass is defined to mean the encoding of a block of cleartext into an intermediate-text or ciphertext block, or the decoding of a block of ciphertext into an intermediate-
  • BCN is defined herein as the binary to base n conversion of a number and the representation of the base n number as a digit shown in binary.
  • a common example (base 10) is BCD (binary coded decimal) where the values 0 through 9 are represented by 4 binary bits.
  • an encryption apparatus and method providing an address pointer scrambler, a byte concatenator, a barrel shifter and a decatenator which encrypt and decrypt input data.
  • the present invention provides an encryption/decryption method wherein binary data may be encrypted through the use of multiple applications of the combination of: a concatenation of bytes (with permuted sequence) forming a single data item, a rotational shifting of the data item by an arbitrary amount and a separating operation or deconcatenation operation of the data item back into individual bytes (with permuted sequence).
  • This method and apparatuses may also employ arithmetic/logic modification of the data during the process.
  • Encoding or Decoding will consist of one or more passes through a cleartext message with the combination of: multiple byte fetches (MF concatenation) from an input buffer with address scrambling (permutation of sequence), rotation of the single element (created by concatenation) by an arbitrary amount and multiple byte puts (MP decatenation) to an output buffer with address scrambling.
  • An interesting aspect of the present invention is the address scrambling mechanism and the use of Address Translation Tables entries (ATT Columns and ATT Block Entries) to permute the order of address selection from I/O buffers A and B and from the two Masking Arrays. This scheme does not require pure random numbers to create the ATT Column Entries. Any digital source may be used, including plain text.
  • Another aspect of the present invention is the ATT mechanism's flexibility to generate different scrambled relative addressing pointer sequences (SRAP values) from the same ATT Block Entry through the use of offsets and masks being applied to the ATT operation.
  • SRAP values scrambled relative addressing pointer sequences
  • the scheme may also employ different sized ATT Column entries. For example, a 4 KB input buffer may be sourced (data fetched) with 4 different 1 KB ATT Column Block Entries and written out using a different single 4 KB ATT Column Block Entry.
  • the only restrictions are that the ATT Block size cannot exceed the size of the Buffer or table being accessed and the Buffer should be an integer multiple of the ATT Block size.
  • XORn (XOR+ and XOR-) describes an exclusive-or operation (base n) defined as: let the numbers A and B base n be defined (for m digits) as:
  • XORn is identical to the standard XOR operation.
  • Eq. 1 is a type of Vigenere cipher using XOR+ while Eq. 2 is a Variant Beaufort cipher is using XOR- These two ciphers being applied to the digits resulting from the conversion of binary to base n numbers and the subsequent reconversion back into a number in the original number base is defined herein as XORing the numbers base n (XORn).
  • Arbitrary and random numbers are created by normal digital processes. Most digitized music which comes on a CD-ROM is 16 bits of Stereo sampled at a 44.1 kilohertz rate. This produces approximately 10.5 million bytes per minute. Of these about one half may be used as arbitrary data bytes, or about 5 million bytes per minute. Reasonably random data byte are generated by reading in the digital data stream which makes up the music and throwing away the top 8 bits and sampling only the lower eight bits of sound to produce an arbitrary or random number. Fourier analysis on the resultant byte stream shows no particular patterns. It should be kept in mind that silent passages are to be avoided. If taking every byte of music in order is undesirable, then using every nth byte should work quite well for small values of n between 11 and 17.
  • the error correction inherent with a music CD-ROM is not perfect and the user might want to convert the CD-ROM music format to a WAVE (.WAV) file format and then send the WAVE (.WAV) file to someone by either modem, large capacity removable drive, digital magnetic tape cartridge, or by making a digital CD-ROM containing the WAVE (.WAV) file.
  • Another source of digital randomness is the pixel by pixel modification (ex-clusive oring, adding, subtracting) of several pictures from a PHOTO CD- ROM, again looking at the low order bytes.
  • Computer Zipped (.ZIP) files and other compressed file formats can be used.
  • the intelligent sampling of digital sources can be used to advantage to lessen the reconstruction of the byte stream used for encryption.
  • encryption and hashing algorithms may be used to modify the digital sources prior to their use.
  • the modification of pseudo-random numbers for tables, arrays and/or masks may also be used to advantage.
  • a General Pointer In the Encoder, a General Pointer (GP) is used to retrieve an eight bit byte from the RDT. Each time the General Pointer is used, its value is incremented after the retrieval of the byte from the RDT. The General Pointer is incremented Modulo the length of the RDT.
  • the addition of a pre or post rotate operation to this encoding scheme increases the security of the encrypted material.
  • 32 bit arithmetic/logic operations is utilized, which means that 4 bytes of data must be fetched from the input buffer at one time and written back out as 4 bytes of data to our output buffer. These 4 bytes may be rotated either left or right by any number from 1 to 31 bits. Normally, a rotate value of zero or a multiple of 8 is not is not used.
  • each variable has its own individual source pointer.
  • pointers indicate the locations within one or more tables or mask arrays which are to be used and how these retrieved byte values are to be combined to supply a byte to the Encoder for updating a variable, counter or pointer value.
  • addressing modes other than incremental, may be used, where individual relative address pointers into table are incremented by values other than +1, or where the next value of a relative address pointer is calculated from one or more entries presently in an array or table of bytes, thus creating a pointer which jumps around.
  • the expansion from one General Pointer to individual source pointers is not difficult for anyone skilled in the art to implement.
  • a selectable number of pointers are assigned to the variables in a manner determined by information sent to the encoder by the user interface.
  • each set of 4 byte fetches (1 MF) or puts (1 MP) will be considered 1 counter decrement operation for the Encoder counters associated with the Encoder control variables ALV,
  • the retrieved masking array values may be modified by any of: complementation, negation, hashing, or conversion to BCN digits (base n).
  • the expansion of the ALV to two bytes allows for the negation of the data and the expansion of other A/L options such as the use of an XORn (non-power of 2).
  • Another preferred embodiment using a second ALV operation and counter contains bits which indicate whether the MF values (masking arrays and data), the intermediate or ending modified data elements are bit reversed.
  • the RDT replaces the characters in the Password String (as previously defined in US Patent application 08/336,766) and the retrieved bytes now control the sequence of arithmetic/logic and rotational operations as well as provide counter values which control the duration of these operations usage within the Encoder.
  • Starting offset values for the General Pointer, the Array #1 Pointer, the Array #2 Pointer and any other initial value for a variable, counter, mask or offset may be obtained by any combination of: a Password String, hashing or other mathematical functions and values retrieved through the GP.
  • 32 bit operations is arbitrary, other sizes such as 16 bits, 24 bits, or 64 bits may be implemented if desired, in another preferred embodiment, 2 bytes or 16 bit arithmetic/logic and rotational operations are employed. In the preferred embodiment shown in FIG. 4C, and additional rotate operation is inserted between the first and the second arithmetic/logic operations. This rotate and the pre and post rotate operations also have the effect of further hiding the values or the mask arrays from detection by statistical processes.
  • FIG. 8 shows the minimum, average, and maximum number of 8 bits segments (bytes) which contain the original 8 bit byte as a function of the number of scramble/rotate passes performed.
  • a simulator was built where rotates of only plus or minus 1 to 7 positions are allowed and once bits are moved into another byte, this other byte is treated as being independent form the original byte, The is, the maximum number of bytes containing the original 8 bits is 8 after 7 passes of the rotate function (with address scrambling). This is the result of each rotate breaking 1 bit off with each pass. Obviously, this does not happen that frequently because 7 passes has an average result of 5.6, meaning that the original 8 bits are now spread throughput 5 to 6 other bytes (see Fig. 8)
  • the rotate operation has the effect of splitting an n bit data byte into two parts.
  • the size of the smaller part (SP) is given by Eq. 4, while the larger part (LP) is given by Eq. 5.
  • the rotate operation may split a byte only into a maximum of two parts for each PASS, where with US patent '729 the degree of splitting (data multiplexing) is limited only by the size of the matrix and the number of integer entries in the respective matrix employed. Eq.'s 4 and 5 work well for the first rotation pass where n equals the byte width.
  • This encoder uses a symmetric private key encryption method, the sender of a message and the receiver must decide ahead of time on what sources will be used and how these sources will be accessed and used to build the ATT entries and other internal tables, mask arrays, counter, variable and pointers.
  • the intelligent sampling of digital sources can be used to advantage to lessen the reconstruction of the byte stream used for encryption,.
  • encryption ad hashing algorithms may be used to modify the digital sources prior to their use.
  • the modification of pseudo-random numbers for table, arrays, and or masks may also be used to advantage.
  • FIG. 1 is a block diagram of the encryption engine
  • Fig. 2A and 2B are listings of variables, counters, pointers and control bytes which must be saved and restored for each I/O pass;
  • Fig. 2C illustrates the entries in the encoder Control Variables, as well as the formats for the rotate values and the arithmetic/logic variable;
  • Fig. 3 A and 3B are flow charts of the encryption/decryption sequence
  • Fig. 3C is a flowchart detailing the Address Translation Process Operation
  • Fig. 3D is a flowchart detailing the Multiple Byte Put (MP) operation
  • Fig. 3E is a flowchart detailing the Multiple Byte Fetch (MF) operation
  • Fig. 4A is a diagram showing the MF operations being applied to the retrieval of information of mask arrays and their modification by the control bits;
  • Fig. 4B is a diagram showing the MF and MP operations as they apply to data I/O operations
  • Fig. 4c is a diagram detailing the operation of the Data Modification operations
  • Fig. 5A is a flowchart showing how ATT Block entries are made
  • Fig. 5B is a table showing the structure of Address Translation columns
  • Fig. 6 is a diagram showing the operations of a sample Data Modification operation with only a rotate element
  • Fig. 1 shows a basic block diagram of the encoder/decoder engine.
  • the user interface 1 is used by the controller 6 to communicate information to and from the user.
  • a communications bus 20 is used to transfer information between the user interface and the controller.
  • the controller is in charge of general housekeeping details for t encoder. It also takes commands form the user interface which direct the controller to place data bytes in: the masking arrays 13 and 14, the random data table (RDT) 2, the parameter save tables 3, the address translating tables 4, the data modifier 7, and I/O buffer 15 or 16, or to read back data bytes from the previous I/O buffers.
  • RTT random data table
  • address and control lines56 and 57 are used by the controller to load data bytes into and to read data bytes from the I/O-a and I/O-B, respectively.
  • the I/O, address and control lines 32 and 37 are used to send data bytes to Mask Array #1 (MA#1) 13 and Mask Array #2 (MA#2) 14, respectively.
  • line 21 is used to load data bytes into the random data table (RDT).
  • the RDT is a large table of bytes, some of which are periodically sent to the Data Modifier, 7, via line 26 to supply direction and control information to the Data Modifier (DM).
  • the General Pointer (GP) see Figure 2A, is a RAP into the RDT which designates which byte will be sent to the DM unit. After each access with the GP, the value of the GP is incremented (modulo the length of the RDT).
  • the RDT has assumed and expanded upon the direction and control function previously supplied by the Password String in the parent U.S. patent application 08/336,766.
  • Parameters (pointer, variable, counters, etc.) used by each encoding pass within the encoder may be loaded into the Parameter Save Table (PST) by one of two means: either through I/O, address and control line 23 directly from the Controller, or by another I/O, address and control line 27, directly from the Data Modifier 7.
  • the Parameters must first be loaded into the DM and then saved from the DM into the PST (with the appropriate PN information being supplied by the Controller so that the information is stored in the correct section of the PST.
  • the PST normally holds up to sixteen different sets of Parameters, though this is an arbitrary number and its value may be changed during implementation.
  • the PST is where the encoder saves the state of the Parameters of the Data Modifier 7, after processing the I/O buffers for one pass and reloads the previously saved Parameters of the Data Modifier for the next processing passes.
  • the designation of input and output buffers is swapped after each processing pass. Care must be taken so that after the processing pass, BUFSEL is not complemented so that it correctly points to the output buffer which holds the completed ciphertext.
  • the process is initiated for the RAP for MA#2 (Array #2 Pointer, Fig.2A) to be converted into a SRAP by the M2 ATT Processor 5B using lines 29a to 29d, and the SRAP is sent via 41 a to MA#2 and the Array #2 Pointer value is incremented.
  • the resulting byte from MA#2 is sent via 38 to MF#2. Again, this process is repeated three times and the resulting 32 bit wide value (M2, Fig. 4A) is sent via 39 to the DM units.
  • the GP may be used to update the counter with a new value, otherwise the GP may be used to retrieve a new value for the variable. Only upon completion of the processing of an I/O buffer's ATT Block entry is the ATT counter for that buffer decremented once
  • ALV is the Arithmetic/Logic control Variable. It instructs the DM on how the fetched Array values are to be changed and how they are to be combined with the fetched data from the input buffer.
  • RV2 the limitation on the value RV2 may take can be eliminated if desired. It is important that at least RVl, if not both RVl and RV2, have the above value limitations imposed so as to increase the likelihood that the rotate operation will cause the bits in the multibyte wide data byte to be split across byte boundaries.
  • the bits in the ALV from right to left are as follows: DCF, CF1 , CF2,
  • the variable ALNB may be chosen from a digital source or computed using any combination of arithmetic or logic operations, but should have a value greater than or equal to two.
  • One advantage of using a number base that is not a power of 2 is that, with the operations of XOR+ and XOR-, it is more difficult to recover useful cryptanalytic information by xoring (base 2) messages or parts of messages against each other. The utilization of a varying number base helps increase the security of the encrypted information.
  • base 3 for example, (with data bytes having values within the range of 0 to 63 __) the data which is initially in the lower 6 bits of the byte will be converted to the whole 8 bits of the byte.
  • FIGS. 3A and 3b represent a flowchart showing the sequence of Encoder operations.
  • Step 4 is the first step after the initialization sequence.
  • the Pass Number, PN is set equal to SV (either 1 or PASSES), BUFSEL is set equal to 0, and I/O-A is filled with information to be processed.
  • the local counter K is set equal to 1.
  • Step 8 updates the pass counter PN by the value in D and the local counter K is incremented.
  • Step 9 if the K value is less than PASSES indicating addition processing passes are to be performed with the same I/O buffers, then the value of BUFSEL is complemented (Step 10) and the process returns to "2" on Figure 3 A which goes to step 5 above for addition processing. Otherwise, when all processing passes for a buffer have been performed, BUFSEL points to the output buffer and the output buffer (step 11) is sent through the Controller to the User Interface and thus to the user.
  • Step 12 if additional information needs to be processed, the process goes to "3" on Figure 3A which takes the process back to step 4, otherwise the process is done.
  • FIG. 3C ADDRESS TRANSLATION PROCESSOR OPERATION, is a detailed description of an ATT Process.
  • Step 1 indicates what variables will be needed.
  • the ATT Process requires an ATT Column with at least 1 ATT Block Entry, a RAP, the variables ATTB, OFFSET #1, MASK #1, OFFSET #2 AND MASK #2.
  • the ATT Column contains ATTN, ATTSIZE and ATTBASE see Figure 5B.
  • ATTN is the number of ATT Block entries within the ATT Column while ATTSIZE is the size of the ATT Block Entries.
  • ATTBASE is the number base to be used with the ATT operation.
  • the I/O Buffer, table or mask array being accessed is an integer multiple in size of ATTSIZE.
  • the value UPPER is the RAP divided by ATTSIZE while LOWER is the RAP mod ATTSIZE.
  • UPPER is the quotient of RAP/ATTSIZE while LOWER is the remainder.
  • step 3 the value LOWER is modified by adding OFFSET#l to it. If we tread the RAP as the output of a counter, then adding an offset is the same as phasing the counter. The result of the addition is XORn'd with MASK#1 and the result of this operation is taken mod ATTSIZE. The XORn introduces a nonlinear aspect to the phased value. The last mod ATTSIZE operation is needed to keep the results of the ADD and XORn with the ATT Block's address space.
  • step 4 The resulting LOWER value is used as a RAP into the ATT Block pointed to by ATTB within the ATT Column. This RAP (LOWER) is used to obtain LOOKUP from the ATT Block Entry.
  • Step 3 takes the Ouput RAP and other ATT variables and sends them to the OUTPUT ATT Processor.
  • Step 6 is used to determine whether there are more bytes to be decatenated and placed into the output buffer. Since J is the local counter, if J is equal to K (because counting started at 0) then the process is done, otherwise the steps 3 through 6 need to be repeated until all of the bytes have been processed.
  • FIG. 3E MULTIPLE BYTE FETCH, is a description of the MF operation.
  • K is equal to 4.
  • Step 1 shows what variables are needed for the MF operation.
  • step 2 TEMP and J are both set equal to 0. J is used as a temporary counter within the MF process.
  • Step 4 takes the retrieved 8 bit data item, DATABYTE, and multiplies it by 2 which has the effect of left shifting the data byte by 8J bits prior to its being summed into the temporary variable TEMP. J is incremented so that the next time through the DATABYTE will be shifted 8 more bits to the left before being added into TEMP.
  • the address Pointer associated with the RAP being used is incremented for use during the next iteration within the MF operation.
  • Step 5 checks to see if the appropriate number of bytes have been fetched. If more fetch operations are needed, then steps 3 and 4 are repeated until the correct number of bytes have been retrieved. When the correct number of bytes have been retrieved, TEMP contains the single concatenated data item which is the result of the MF operation and is output of the MF operation.
  • step 3 if the MF operation concerns either of the two masking arrays, then the incrementing of their Pointer values follows some special rules.
  • the Pointer for Mask Array #2 will need to incremented an extra time (modulo it's length) whenever the Mask Array #1 Pointer wraps around from the end of the array to its beginning. Since the Mask Array #1 Pointer is also incremented modulo the length of MA#1, if the incrementing of the Array #1 Pointer results in a zero value, then the Array #2 should also be incremented an additional time. Please note, this only involves the Mask Array pointers and not the Input Pointer.
  • Figure 4A is a detailed diagram showing how masking bytes are retrieved from the masking arrays and modified by control variables from ALV before being placed in the mask registers Ml and M2.
  • the contents of the Ml SRAP register is sent via 36a to the address inputs for MASK ARRAY #1.
  • Control lines 36b and 35 synchronize the transfer of a mask data byte (addressed by the Ml SRAP) to the MF#1, 8. Once this process has occurred four times, the MF#1 contains a 32 bit wide mask value which is transferred to the ROTATOR ,118, via line 34.
  • Distance and direction information is supplies to ROTATOR 118 by MRVl, 92, via line 108.
  • the Output of the ROTATOR, 118 is sent to XOR, 1 12, via line 122.
  • the resulting SRAP is sent by 29b to the M2 SRAP register ,111.
  • An incrementing control pulse, 29c causes the ARRAY #2 POINTER counter to be incremented via OR 100 and line 101 to ARRAY #2 POINTER, 97, after the RAP is sent to the M2 ATT PROCESSOR.
  • the contents of the M2 SRAP register is sent via 41a to the address inputs for MASK ARRAY #2.
  • Control lines 41b and 40 synchronize the transfer of a mask data byte (addressed by the M2 SRAP) to the MF#2, 9.
  • the MF#2 contains a 32 bit wide mask value which is transferred to ROTATOR, 121, via line 39.
  • Distance and direction information is supplies to ROTATOR 121 by MRV2, 93, via line 109.
  • the Output of the ROTATOR, 121 is sent to XOR, 1 13, via line 125.
  • the XOR, 113 is constructed in such a manner that each of the 32 input bits is XOR'd with the value of the CF2, 77, status bit from the ALV.
  • the CF2 information is transferred to the XOR via line 103.
  • FIG. 4B is a detailed diagram showing the input and output MF and MP operations.
  • ED, 60 is equal to 0 for encryption and is equal to 1 for decryption.
  • ED, 60 is a bit within ECV1.
  • ED is sent to two SELECTORS, 136 and 137, by lines 134 and 135 respectively.
  • the counter,94 containing the INPUT POINTER goes to SELECTOR 136 via line 130, and the counter, 95 containing the OUTPUT POINTER goes to the same SELECTOR, 136, via line 132.
  • the SRAP from the INPUT ATT PROCESSOR, 5C is sent via 28b to the INPUT SRAP register, 138.
  • the SRAP from the OUTPUT ATT PROCESSOR, 5D is sent via 29b to the OUTPUT SRAP register, 139.
  • the INPUT SRAP, 138 goes to SELECTOR 142 via line 140, while the OUTPUT SRAP, 139, goes to the same SELECTOR, 142, via line 141.
  • the action of the SELECTOR, 142 is controlled by BUFSEL, 65, via line 143.
  • the SELECTOR, 142 sends the INPUT SRAP, 138, to the address inputs of A I/O BUFFER, 15, via line 46a and also sends the OUTPUT SRAP, 139, to the address inputs of B I/O BUFFER, 16, via 47a.
  • MUX 147 selects the 8 bit data from the A I/O Buffer (via 53) and sends the data byte from MUX 147 via line 41 to the MF#3 processor, 10.
  • Control lines 52 (going to MP#1, 1 1), 44 (going to MF#3, 10), 46a (going to A I/O BUFFER, 15) and 47b (going to B I/O BUFFER, 16) are used to synchronize the I/O process to prevent any address, data, or timing conflicts.
  • the 32 bit wide modified data byte, OUTPUT DATA, 218, goes via 51 to the MP#1 processor, 11.
  • the output of the MP#1 process, 11, is a 8 bit wide byte which is sent via 49 to the data inputs of both I/O Buffers. Only the buffer whose data input is enabled via BUFSEL will actually take the 8 bit data byte on line 49 and write it into the buffer.
  • the write enabled buffer uses OUTPUT SRAP sent to it via SELECTOR 142 as the address where the data byte is to be written.
  • FIG 4C is a diagram showing the details of the Data Modification Operation, DM, Figure 1 item 7.
  • ED 60, the 1 bit status bit from the ECV1 byte, is sent via 174 to the inverter 175.
  • the output of the inverter, 175, is ED- which is sent via 176 to AND 177.
  • the output of XOR 161 is a 32 bits wide data byte which is the input to a 32 bit wide ROTATE OPERATION, 164.
  • ED Encrypt/Decrypt Flag
  • 60 also goes via line 163 to the first ROTATE OPERATION, 164, where it is used to complement the value of the sign (direction) bits of the RVl , 90, variable sent to the Rotator via line 189.
  • the 32 bit wide output of the ROTATE OPERATION, 164 goes out on line 165.
  • RF (Rotate First) flag, 82 (from the ALV variable, see Figure 2C) is an input, via line 181 to XOR, 182.
  • the other input to XOR 182 is ED, 60, via line 179.
  • Figure 4C is shown how the third
  • DCF Data Complement Flag
  • the other input of AND 213 is ED, 60, via line 211.
  • the second Rotate Operation is always enabled and that the first and third Rotate Operations are not enabled or disabled at the same time.
  • Another preferred embodiment eliminates the RF flag (in ALV) and uses a RV3 (variable and counter) for the third Rotate Operation, 204.
  • the 32 bit wide output of this Rotate Operation goes out via line 165 to XOR 166, ADD 167, and SUB 168.
  • Ml, 123 (see Figure 4A) the 32 bit wide masking value derived from Mask Array #1, goes via line 124 to XOR 166, ADD 167, and SUB 168.
  • the 32 bit wide output of XOR 166 goes via line 170 to select 0 and 1 inputs of MUX 169.
  • the 32 bit wide output of ADD 167 goes via line 171 to the select 2, 3, 5 and 6 inputs of MUX 169.
  • the 32 bit wide output of SUB 168 goes via line 172 to the select 4 and 7 inputs of MUX 169.
  • the inputs of the MUX's have been arranged so that when ED complements the A/L Bit 3, it causes a reverse arithmetic/logic operations to be performed (along with ED complementing the rotate sign bits and the MSF control bit) on the input data, see the discussion on Figure 2C.
  • the 32 bit wide output of MUX 169 goes via line 173 to the input of the second ROTATE OPERATION, 194, (32 bits wide).
  • This Rotate Operation is always enabled.
  • the 32 bit wide output of the second ROTATE OPERATION, 194, goes via line 195 to ADD 196, XOR 197 and SUB 198.
  • M2, 126 (see Figure 4A) the 32 bit wide masking value derived from Mask Array #2, goes via line 127 to ADD 196, XOR 197 and SUB 198.
  • the 32 bit wide output of ADD 196 goes via line 199 to the select 0 and 3 inputs of MUX 202.
  • the 32 bit wide output of XOR 197 goes via line 200 to the select 4 and 5 inputs of MUX 202.
  • the 32 bit wide output of SUB 198 goes via line 201 to the select 1, 2, 6 and 7 inputs of MUX 202.
  • the 32 bit wide output of MUX 202 goes via 203 to the third ROTATE OPERATION, 204 (see prior discussion of this rotate operation).
  • the 32 bit wide output of the third ROTATE OPERATION, 204 goes via line 205 to XOR 216 (also previously discussed), then via line 217 to the 32 bit wide OUTPUT DATA register, 218 (see also Figure 4B).
  • Step 3 creates K records where each record contains two fields.
  • the first field will holds an integer which will become the RAP entry, and the second field will contain an 8 bit byte sampled from some digital source.
  • This 8 bit byte may also be a byte stream from a pseudo-random number generator, or even a text file.
  • Steps 4 & 5 fill all of the first fields with sequential values of J (0 to ATTSIZE- 1) while the second fields are filled with sampled (arbitrary) 8 bit bytes. When this process is complete, step 5 no longer goes back to step 4, but instead goes to step 6.
  • Step 6 sorts all of the K records in ascending order by the contents of the second field. As the sorting takes place, the field 1 entries are shuffled around.
  • Step 7 the shuffled field 1 entries are transferred to the ATT Block Entry.
  • Figure 5B shows the structure of an ATT Column which makes up the ADDRESS TRANSLATION TABLES.
  • the number of ATT Columns is only limited by the amount of storage available.
  • Each ATT Column has a unique number assigned to it, so that an ATT Processor knows which ATT Column to use.
  • the next entry in the Column is ATTN which specifies how many ATT Block Entries are in that Column.
  • ATTSIZE which specifies the size of the ATT Block entries within the Column.
  • FIG. 6 shows a simplified Data Modifier, 232, which could replace the previously described Data Modifier, 219.
  • Figure 7 shows a four stage pipeline Encoder/Decoder. It consists of four individual Encoders, (250a - 254a, 250b - 254b, 250c - 254c, and 250d - 254d).
  • a common RAP counter, 257, via 249 is used to supply RAPs for the use of all four Encoders.
  • a Cleartext 248, is loaded into the input buffer of 250a.
  • the first Encoder contains intermediate-text in the output buffer within 254a.
  • the output buffer of 253a is transferred to the input buffer of the second Encoder via 255 to the input buffer of 250b. This process is repeated with successive encoders.
  • the Ciphertext is transferred via 256 to the user for distribution in some manner.
  • the only delay in processing four passes of encryption/decryption is only the time needed to process 1 buffer.
  • the pipeline structure, with multiple Encoders is a very fast and effective method to encrypt and decrypt information.
  • Figure 8 is a tabular representation of the average number of segments (bytes) containing the original 8 bits as a function of the number of passes between 1 and 32. Also shown is that average sorted original bit density per segment (byte). The entries were derived from a software simulator. An illustration of an unsorted density is that the two segments resulting from pass 1 would on average both have an equal probability of containing 4 bits each. This is because sometimes the larger portion may be on one side of the original byte boundary and sometimes it would be on the other. Therefore, for sorted statistics, the bit densities are arranged in declining order before being averaged into previous distributions. Consequently after 5 passes, the approximate average bit density (in some location of bytes in a buffer) would be 3,2,1,1,1 (with rounding).
  • Equation 4 The size for the biggest segment (X1 P ) of the sorted bit density of 8 original bits as a function of the number of passes is approximated by the formula (Equation 4) shown below:

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  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
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  • Storage Device Security (AREA)

Abstract

Selon la présente invention, on prend le texte en claire et on le découpe par blocs dont la tailles définie par l'utilisateur est une puissance de 2 (étape 1). Les octets de données du bloc d'entrée sont sélectionnés M octets à la fois avec M ≥ 2, l'adressage étant permuté pour former un unique octet de données concaténées ou 'CDB' (concatenated data byte). Ce CDB est modifié par permutation circulaire sur une distance binaire aléatoire (étape 7). Le CDB peut également être modifié avant ou après permutation circulaire par de simples opérations arithmétiques ou logiques (étape 12). Après modification, le CDB est découpé en M octets, chacun de ces M octets étant mis dans le bloc de sortie avec un adressage permuté (étape 4). Le bloc de sortie ou texte crypté, peut de nouveau servir de bloc d'entrée, le traitement se répétant avec un nouveau bloc de sortie. Cette logique peut s'utiliser comme principe de cryptage en tant que telle, ou en relation avec d'autres procédés de cryptage de blocs. Ces derniers procédés peuvent se réaliser en utilisant ce procédé entre deux étapes consécutives de cryptage de données en blocs, ou dans le cours d'une étape interne des autres procédés. La source du nombre aléatoire (étape 2) utilisée pour évaluer la distance utilisée pour l'opération de permutation circulaire peut être un générateur de nombre pseudo aléatoire, des CD-ROM de musique échantillonnés, des rubriques de matrices de tables, des tampons, ou d'autres sources numériques.
EP99927081A 1999-05-18 1999-05-18 Moteur cryptographique utilisant la conversion de base de numeration, des operations logiques et un generateur de nombres pseudo-aleatoires pour des matrices de donnees de fa on a augmenter la dispersion dans le texte chiffre Withdrawn EP1179243A4 (fr)

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PCT/US1999/010967 WO2000070819A1 (fr) 1998-02-07 1999-05-18 Moteur cryptographique utilisant la conversion de base de numeration, des operations logiques et un generateur de nombres pseudo-aleatoires pour des matrices de donnees de façon a augmenter la dispersion dans le texte chiffre

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JP2005309148A (ja) * 2004-04-22 2005-11-04 Hitachi Ltd データ変換装置およびデータ変換方法
KR20070042511A (ko) * 2004-06-14 2007-04-23 디 유니버시티 오브 노스 캐롤라이나 앳 그린스보로 디지털 콘텐트 보안 시스템 및 방법

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SCHNEIER, B.: "Applied Cryptography, Protocols, Algorithms and Source Code in C, Second Edition" 1996, JOHN WILEY & SONS, INC. , NEW YORK 218930 , XP002329180 * page 304, line 5 - page 306, line 31 * * figure 13.1 * *
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CN113542196A (zh) * 2020-04-16 2021-10-22 北京威努特技术有限公司 一种数据报文加密判定方法、装置、系统及存储介质
CN113542196B (zh) * 2020-04-16 2023-03-24 北京威努特技术有限公司 一种数据报文加密判定方法、装置、系统及存储介质

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