EP1178538A2 - Heterojunction bipolar transistor with reduced thermal resistance - Google Patents

Heterojunction bipolar transistor with reduced thermal resistance Download PDF

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Publication number
EP1178538A2
EP1178538A2 EP01116726A EP01116726A EP1178538A2 EP 1178538 A2 EP1178538 A2 EP 1178538A2 EP 01116726 A EP01116726 A EP 01116726A EP 01116726 A EP01116726 A EP 01116726A EP 1178538 A2 EP1178538 A2 EP 1178538A2
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EP
European Patent Office
Prior art keywords
collector
sub
hbt
substrate
inp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP01116726A
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German (de)
French (fr)
Other versions
EP1178538A3 (en
Inventor
Augusto Gutierrez-Aitken
K.Aaron Oki
Patrick T. Chin
Dwight C. Streit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Corp
Original Assignee
TRW Inc
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Filing date
Publication date
Application filed by TRW Inc filed Critical TRW Inc
Publication of EP1178538A2 publication Critical patent/EP1178538A2/en
Publication of EP1178538A3 publication Critical patent/EP1178538A3/en
Ceased legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821Collector regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors

Definitions

  • an HBT 110 is shown.
  • This HBT is constructed with a substrate 114 formed of InP, a sub-collector 116 formed on the substrate, a collector 118 formed on the sub-collector, a base 120 formed on the collector and an emitter 122 formed on the base.
  • An emitter metal 124 is provided on the emitter 122 (with collector metal being provided on the sub-collector 116 and base metal provided on the base 120).

Abstract

The performance of a heterojunction bipolar transistor (HBT) operating at high power is limited by the power that can be dissipated by the device. This, in turn, is limited by the thermal resistance of the device to heat dissipation. In a typical HBT, and especially InP-based HBTs, heat generated during operation is concentrated near the collector-base junction. In order to more efficiently dissipate heat downward through the device to the substrate, both the collector and the sub-collector are formed of InP, which has a substantially lower thermal resistance than other typically used semiconductor materials.

Description

    Field of the Invention
  • The present invention relates generally to heterojunction bipolar transistors (HBTs), and, more particularly, to HBTs constructed to have reduced thermal resistance to permit rapid dissipation of heat.
  • Background of the Invention
  • In HBTs operating at high power, the performance of the device is limited by the amount of power that can be dissipated in the device. Typically, a high power HBT will generate a large amount of heat which must be dissipated quickly to permit proper operation.
  • Recently, metallic thermal shunts have been developed to permit dissipation of heat from the collector of the HBT device. Typically, in any HBT, and especially in InP based HBTs, most of the power dissipation and heat generation are located in the upper region of the collector layer near the base layer, where there is a large voltage drop and a large current. Fig. 1 shows an HBT with a metallic thermal shunt designed in accordance with known principles to dissipate this heat.
  • Referring to Fig. 1, an HBT 110 is shown. This HBT is constructed with a substrate 114 formed of InP, a sub-collector 116 formed on the substrate, a collector 118 formed on the sub-collector, a base 120 formed on the collector and an emitter 122 formed on the base. An emitter metal 124 is provided on the emitter 122 (with collector metal being provided on the sub-collector 116 and base metal provided on the base 120).
  • As can be seen in Fig. 1, the majority of the heat generated during operation of the HBT 110 is located in a region 112 near the base-collector junction. In order to dissipate this heat to the substrate, a metallic thermal shunt 126 is coupled between the emitter metal 124 and the substrate 114. Thus, the heat generated in the collector 118 will dissipate through the base 120, the emitter 122, the emitter metal 124 and the metallic thermal shunt 126 to the substrate 114. It is noted that this arrangement is also taught in U.S. Patent No. 5,734,193 to B. Bayraktaroglu et al.
  • From their studies of the thermal shunt technique described above, the inventors have noted certain disadvantages. The first of these is that the heat dissipation is limited by the fact that the heat must go through the base and emitter layers (and an emitter cap layer if one is used), and these layers generally have relatively low thermal conductivity, especially in InP-based HBTs. For example, the material used in the base of InP-based HBTs is the ternary InGaAs that has a very low thermal conductivity. Furthermore, in InP-based HBTs, the emitter material is typically the ternary semiconductor InAlAs, which also has a very poor thermal conductivity. The thermal shunt approach would provide limited improvement for these type of devices. Also, InGaAs is generally used as a cap layer on top of the emitter to improve the ohmic contact resistance to the emitter, which adds another layer with low thermal conductivity in the path for heat dissipation.
  • The metallic thermal shunt technique was initially developed for AlGaAs/GaAs - based HBTs. In these HBTs, the emitter layer consists of the ternary semiconductor AlGaAs, which has a poor thermal conductivity (see Figure 4). Therefore, the thermal shunt technique also provides limited improvement in this instance.
  • A second disadvantage of the thermal shunt approach is the fact that it requires an extra processing step to construct the thermal shunt after the device itself is completed. Also, additional space is required for the shunt, thereby increasing the overall size of the device.
  • Summary of the Invention
  • It is an object of the present invention to provide an HBT with improved heat dissipation.
  • It is a further object of the present invention to provide an HBT in which heat is dissipated downward to the substrate directly without the need for a thermal shunt.
  • It is still a further object of the present invention to provide an HBT with reduced thermal resistance between the heat generated near the collector-base junction and the substrate.
  • Yet another object of the present invention is to provide a method of fabricating an HBT to improve heat dissipation downward to the substrate.
  • To achieve these and other objects, an HBT is provided with a collector and a sub-collector which are each comprised of InP and located relative to one another so that heat generated in the collector during operation of the HBT dissipates downward from the collector through the sub-collector into the substrate.
  • Brief Description of the Drawings
  • Fig. 1 is a prior art HBT with a thermal shunt to dissipate heat from the collector to the substrate through the base and emitter.
  • Fig. 2 is an illustration of the InP-based HBT for explaining the principle of the present invention.
  • Fig. 3A-3D are illustrations of various devices studied by the inventors in developing the present invention.
  • Fig. 4 is a table of thermal conductivity at room temperature for semiconductors used in HBTs and of gold, for comparison.
  • Fig. 5 shows an HBT constructed in accordance with a first embodiment of the present invention.
  • Fig. 6 shows an HBT constructed in accordance with a second embodiment of the invention.
  • Fig. 7 shows a test device studied by the inventors to compare with the device shown in Fig. 6.
  • Fig. 8 shows comparative results between the device shown in Fig. 6 and the device shown in Fig. 7 to illustrate measured thermal resistance for the respective HBTs as a function of collector area.
  • Detailed Description
  • Referring to Fig. 2, as discussed above for the prior art Fig. 1 device, most of the heat generated in an HBT, and especially in an InP-based HBTs, is concentrated at a location in the collector 218 near the collector-base junction. Because of the proximity of this heat to the upper portion of the device, prior art structures have naturally sought to dissipate the heat upwards through the base 220 and the emitter 222. However, from their studies of this matter, the inventors have determined that a better approach is to dissipate the heat downward through the collector 218 and the sub-collector 216 directly into the substrate 214, as illustrated in Fig. 2.
  • The performance of an HBT operating at high power is limited by the power than can be dissipated in the device, which depends on the thermal resistance of the device (Rth) · Rth is defined as Rth = ts A·Ks where ts is the semiconductor layer thickness, A is the device area, and Ks is the semiconductor thermal conductivity.
  • The collector and sub-collector structure of a typical InP-based HBT is usually fabricated using a combination of InGaAs and InP layers as depicted in Figs. 3(a)-3(d). The thermal conductivities at room temperature of five common semiconductor materials and gold used in the fabrication of HBTs are listed in the table shown in Fig. 4. The thermal conductivity is given in units of Watt per Centimeter per degree Kelvin.
  • Semiconductor materials with high thermal conductivity, such as InP or GaAs, conduct heat readily through them and materials with low thermal conductivity, such as InGaAs or InAlAs, behave more like thermal insulators.
  • All the structures illustrated in Figs. 3(a)-3(d) have a layer with poor thermal conductivity in the collector (e.g., Figs. 3(a) and 3(b)) or sub-collector (e.g., Figs. 3(a), 3(b) and 3(d)) or both (e.g., Fig. 3(a)). As a consequence, the heat generated in the collector cannot be efficiently dissipated.
  • In accordance with the present invention, as illustrated in Fig. 5, InP semiconductor materials are used for both the collector 518 and the sub-collector 516. With regard to this, it is noted that the thermal conductivity of InP is approximately fifteen times higher than that of the thermal conductivity of InGaAs. Thus, by forming both the collector 518 and the sub-collector 516 of InP material, the desired downward flow of heat from the collector through the sub-collector to the substrate 514 is encouraged. As noted above, typically, the base and emitter layers contain material with low thermal conductivity such as InGaAs, so that the relative amount of heat dissipated in the structure of Fig. 5 in the downward direction is much greater than that which would typically be dissipated in the upward direction.
  • It is noted that very thin layers of InGaAs or InAlAs ternary layers could be used as etching stop layers. This is shown, for example, by the layer 532 in Fig. 5 and the layers 632 shown in a second embodiment of the present invention in Fig. 6. Typically, these layers 532 and 632 would be made of low thermal conductivity material such as InGaAs or InAlAs. However, they have determined that if these layers are kept to a thickness below 100Å, the effect of these etching stop layers 532 and 632 on thermal resistance of the device will be minimal. Accordingly, in accordance with the embodiment of Figs. 5 and 6, it is possible to provide these extremely thin etch stop layers 532 and 632 to assist in the fabrication of the HBT without adversely affecting the desired heat dissipation discussed above.
  • The thermal resistance Rth of the HBT structure of Fig. 6 was experimentally compared with the device shown in Fig. 7 to demonstrate and measure the effect of the present invention. The comparison device of Fig. 7 is substantially the same as that of Fig. 6, except for the fact that an InGaAs sub-collector 716 is used instead of the InP sub-collector 616 of Fig. 6. In other words, the device of Fig. 7 includes both an InP collector 718 and an InP substrate 714, but does not include an InP sub-collector. Fig. 8 shows the results of measurement of the thermal resistance Rth for several devices constructed in accordance with both Figs. 6 and 7, with each of the devices differing by increasing the collector areas. As can be seen in Fig. 8, the device as constructed in accordance with Fig. 6 clearly have lower thermal resistances, especially as the collector area becomes smaller.
  • In accordance with the principles of the present invention, a method and device are provided which significantly reduce the thermal resistance in the downward direction in an InP-based HBT. Thus, heat generated in the collector can go through the sub-collector to the substrate without the thermal resistance previously encountered in the base and emitter layers. In addition, the arrangement of the present invention has distinct advantages over the prior art structure since it is simple and does not require additional processing steps.
  • Although the present invention is intended to be an alternative to the prior art metallic thermal shunt approach, it is noted that the present invention can be used in addition to providing a metallic thermal shunt if desired. In other words, in addition to providing the downward path for heat dissipation in accordance with the present invention, a thermal shunt can be used similar to the arrangement shown in Fig. 1 to dissipate the relatively small amount of heat which does go upward in the device through the thermal shunt to the substrate.
  • It is noted that the reduced thermal resistance HBT described above has many applications in microwave circuits and high efficiency power amplifiers for phased array components and defense and space applications.
  • While the present invention has been described in detail and pictorially in the accompanying drawings, it is not limited to such details since many changes and modifications recognizable to those of ordinary skill in the art may be made to the invention without departing from the spirit and the scope thereof.

Claims (12)

  1. An HBT with low thermal resistance comprising:
    a substrate;
    a sub-collector formed on the substrate;
    a collector formed on the sub-collector;
    a base formed on the collector; and
    an emitter formed on the base,
       wherein the substrate, the sub-collector and the collector all consist essentially of InP and are located relative to one another so that heat generated in the collector during operation of the HBT is dissipated through the collector and the sub-collector into the substrate.
  2. An HBT according to claim 1, wherein the substrate is in direct contact with the sub-collector.
  3. An HBT according to claim 1, wherein the collector is in direct contact with the sub-collector.
  4. An HBT according to claim 1, wherein the substrate is in direct contact with the sub-collector and the collector is in direct contact with the sub-collector.
  5. An HBT according to claim 1, further comprising an etch stop layer formed between the collector and the sub-collector.
  6. An HBT according to claim 5, wherein the etch stop layer is comprised of InGaAs.
  7. An HBT according to claim 5, wherein the etch stop layer is comprised of InAlAs.
  8. An HBT according to claim 1, further comprising an etch stop layer formed between the sub-collector and the substrate.
  9. An HBT according to claim 8, wherein the etch stop layer is comprised of InGaAs.
  10. An HBT according to claim 8, wherein the etch stop layer is comprised of InAlAs.
  11. A method of fabricating an HBT comprising:
    forming a sub-collector on a substrate;
    forming a collector on the sub-collector;
    forming a base on the collector; and
    forming an emitter on the base,
       wherein the collector and sub-collector are each comprised of InP and located relative to one another so that heat generated in the collector during operation of the HBT will dissipate from the collector through the sub-collector into the substrate.
  12. A method according to claim 11, wherein the substrate is comprised of InP.
EP01116726A 2000-08-03 2001-07-18 Heterojunction bipolar transistor with reduced thermal resistance Ceased EP1178538A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US631597 1996-04-15
US09/631,597 US6376867B1 (en) 2000-08-03 2000-08-03 Heterojunction bipolar transistor with reduced thermal resistance

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EP1178538A2 true EP1178538A2 (en) 2002-02-06
EP1178538A3 EP1178538A3 (en) 2002-05-15

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EP01116726A Ceased EP1178538A3 (en) 2000-08-03 2001-07-18 Heterojunction bipolar transistor with reduced thermal resistance

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EP (1) EP1178538A3 (en)
JP (1) JP2002083818A (en)
TW (1) TW511289B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4438133B2 (en) * 1999-08-19 2010-03-24 シャープ株式会社 Heterojunction bipolar transistor and manufacturing method thereof
JP3507828B2 (en) * 2001-09-11 2004-03-15 シャープ株式会社 Heterojunction bipolar transistor and method of manufacturing the same
US6797995B2 (en) * 2002-02-14 2004-09-28 Rockwell Scientific Licensing, Llc Heterojunction bipolar transistor with InGaAs contact and etch stop layer for InP sub-collector
US6806129B1 (en) * 2003-05-09 2004-10-19 Agilent Technologies, Inc. Self-aligned process using indium gallium arsenide etching to form reentry feature in heterojunction bipolar transistors
US6924203B2 (en) * 2003-05-27 2005-08-02 Northrop Grumman Corporation Double HBT base metal micro-bridge
JP2005310754A (en) * 2004-03-24 2005-11-04 Fuji Photo Film Co Ltd Line light source and image information reading device
US7342294B2 (en) * 2005-07-01 2008-03-11 International Business Machines Corporation SOI bipolar transistors with reduced self heating
GB2453115A (en) * 2007-09-25 2009-04-01 Filtronic Compound Semiconduct HBT and FET BiFET hetrostructure and substrate with etch stop layers
US9836123B2 (en) 2014-02-13 2017-12-05 Mide Technology Corporation Bussed haptic actuator system and method
US10319830B2 (en) * 2017-01-24 2019-06-11 Qualcomm Incorporated Heterojunction bipolar transistor power amplifier with backside thermal heatsink
CN112885710A (en) * 2021-01-15 2021-06-01 广州爱思威科技股份有限公司 Preparation method and application of epitaxial wafer of semiconductor

Citations (5)

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EP0551110A2 (en) * 1992-01-09 1993-07-14 Mitsubishi Denki Kabushiki Kaisha Compound semiconductor devices
US5682046A (en) * 1993-08-12 1997-10-28 Fujitsu Limited Heterojunction bipolar semiconductor device and its manufacturing method
US5923058A (en) * 1995-11-09 1999-07-13 Northrop Grumman Corporation Aluminum gallium nitride heterojunction bipolar transistor
US6049099A (en) * 1998-05-11 2000-04-11 The United States Of America As Represented By The Secretary Of The Air Force Cadmium sulfide layers for indium phosphide-based heterojunction bipolar transistors
WO2000021125A1 (en) * 1998-10-02 2000-04-13 Research Triangle Institute Self aligned symmetric intrinsic process and device

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JP2804095B2 (en) * 1989-07-10 1998-09-24 株式会社東芝 Heterojunction bipolar transistor
US5734193A (en) 1994-01-24 1998-03-31 The United States Of America As Represented By The Secretary Of The Air Force Termal shunt stabilization of multiple part heterojunction bipolar transistors
US5946582A (en) * 1997-01-07 1999-08-31 Telcordia Technologies, Inc. Method of making an InP-based heterojunction bipolar transistor with reduced base-collector capacitance

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551110A2 (en) * 1992-01-09 1993-07-14 Mitsubishi Denki Kabushiki Kaisha Compound semiconductor devices
US5682046A (en) * 1993-08-12 1997-10-28 Fujitsu Limited Heterojunction bipolar semiconductor device and its manufacturing method
US5923058A (en) * 1995-11-09 1999-07-13 Northrop Grumman Corporation Aluminum gallium nitride heterojunction bipolar transistor
US6049099A (en) * 1998-05-11 2000-04-11 The United States Of America As Represented By The Secretary Of The Air Force Cadmium sulfide layers for indium phosphide-based heterojunction bipolar transistors
WO2000021125A1 (en) * 1998-10-02 2000-04-13 Research Triangle Institute Self aligned symmetric intrinsic process and device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
COWLES J ET AL: "Double heterojunction bipolar transistors with InP epitaxial layers grown by solid-source MBE" 1997 INT. CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS. HYANNIS, CAPE COD, MAY 11 - 15, 1997, INDIUM PHOSPHIDE AND RELATED MATERIALS, NEW YORK, NY: IEEE, US, 11 May 1997 (1997-05-11), pages 548-550, XP010232041 ISBN: 0-7803-3898-7 *

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TW511289B (en) 2002-11-21
US6376867B1 (en) 2002-04-23
JP2002083818A (en) 2002-03-22
EP1178538A3 (en) 2002-05-15

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