EP1175014A3 - Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes - Google Patents

Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes Download PDF

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Publication number
EP1175014A3
EP1175014A3 EP01123870A EP01123870A EP1175014A3 EP 1175014 A3 EP1175014 A3 EP 1175014A3 EP 01123870 A EP01123870 A EP 01123870A EP 01123870 A EP01123870 A EP 01123870A EP 1175014 A3 EP1175014 A3 EP 1175014A3
Authority
EP
European Patent Office
Prior art keywords
data
block
decoder
decoding
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01123870A
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English (en)
French (fr)
Other versions
EP1175014A2 (de
Inventor
Ronald P. Smith
Oliver W. Saunders
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Corp
Original Assignee
TRW Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TRW Inc filed Critical TRW Inc
Publication of EP1175014A2 publication Critical patent/EP1175014A2/de
Publication of EP1175014A3 publication Critical patent/EP1175014A3/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2978—Particular arrangement of the component decoders
    • H03M13/2987—Particular arrangement of the component decoders using more component decoders than component codes, e.g. pipelined turbo iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
EP01123870A 1999-01-26 2000-01-25 Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes Withdrawn EP1175014A3 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/237,714 US6304995B1 (en) 1999-01-26 1999-01-26 Pipelined architecture to decode parallel and serial concatenated codes
US237714 1999-01-26
EP00101241A EP1024601A1 (de) 1999-01-26 2000-01-25 Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes (turbo Codes)

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP00101241A Division EP1024601A1 (de) 1999-01-26 2000-01-25 Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes (turbo Codes)

Publications (2)

Publication Number Publication Date
EP1175014A2 EP1175014A2 (de) 2002-01-23
EP1175014A3 true EP1175014A3 (de) 2003-09-17

Family

ID=22894852

Family Applications (2)

Application Number Title Priority Date Filing Date
EP00101241A Withdrawn EP1024601A1 (de) 1999-01-26 2000-01-25 Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes (turbo Codes)
EP01123870A Withdrawn EP1175014A3 (de) 1999-01-26 2000-01-25 Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP00101241A Withdrawn EP1024601A1 (de) 1999-01-26 2000-01-25 Pipeline Architektur zur Dekodierung von parallel und seriell verketteten Codes (turbo Codes)

Country Status (2)

Country Link
US (1) US6304995B1 (de)
EP (2) EP1024601A1 (de)

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US6996767B2 (en) * 2001-08-03 2006-02-07 Combasis Technology, Inc. Memory configuration scheme enabling parallel decoding of turbo codes
US7085969B2 (en) * 2001-08-27 2006-08-01 Industrial Technology Research Institute Encoding and decoding apparatus and method
FR2834146A1 (fr) * 2001-12-20 2003-06-27 St Microelectronics Sa Turbo-decodeur compact a haute efficacite
US7073114B2 (en) * 2002-06-24 2006-07-04 Massey Peter C Method of decoding utilizing a recursive table-lookup decoding method
KR100584170B1 (ko) * 2002-07-11 2006-06-02 재단법인서울대학교산학협력재단 터보 부호화된 복합 재전송 방식 시스템 및 오류 검출 방법
US7055102B2 (en) * 2002-12-06 2006-05-30 Sandbridge Technologies, Inc. Turbo decoder using parallel processing
KR20050097924A (ko) * 2002-12-30 2005-10-10 코닌클리케 필립스 일렉트로닉스 엔.브이. 코딩 시스템
US6959355B2 (en) * 2003-02-24 2005-10-25 Standard Microsystems Corporation Universal serial bus hub with shared high speed handler
US7185126B2 (en) * 2003-02-24 2007-02-27 Standard Microsystems Corporation Universal serial bus hub with shared transaction translator memory
JP4217887B2 (ja) * 2003-07-22 2009-02-04 日本電気株式会社 受信装置
US7236546B2 (en) * 2003-09-10 2007-06-26 Bae Systems Information And Electronic Systems Integration Inc. Pipelined turbo multiuser detection
US7702968B2 (en) 2004-02-27 2010-04-20 Qualcomm Incorporated Efficient multi-symbol deinterleaver
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US7461328B2 (en) * 2005-03-25 2008-12-02 Teranetics, Inc. Efficient decoding
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US7523243B2 (en) * 2006-04-14 2009-04-21 Standard Microsystems Corporation Multi-host USB device controller
US7480753B2 (en) * 2006-04-27 2009-01-20 Standard Microsystems Corporation Switching upstream and downstream logic between ports in a universal serial bus hub
US20080005262A1 (en) * 2006-06-16 2008-01-03 Henry Wurzburg Peripheral Sharing USB Hub for a Wireless Host
US20090063717A1 (en) * 2007-08-28 2009-03-05 Bohm Mark R Rate Adaptation for Support of Full-Speed USB Transactions Over a High-Speed USB Interface
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US20110202819A1 (en) * 2010-02-12 2011-08-18 Yuan Lin Configurable Error Correction Encoding and Decoding
US8799532B2 (en) 2011-07-07 2014-08-05 Smsc Holdings S.A.R.L. High speed USB hub with full speed to high speed transaction translator
US9558782B2 (en) 2012-05-29 2017-01-31 International Business Machines Corporation Partial reverse concatenation for data storage devices using composite codes
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Also Published As

Publication number Publication date
US6304995B1 (en) 2001-10-16
EP1175014A2 (de) 2002-01-23
EP1024601A1 (de) 2000-08-02

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