EP1157336B1 - Datenprozessor mit cachespeicher - Google Patents

Datenprozessor mit cachespeicher Download PDF

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Publication number
EP1157336B1
EP1157336B1 EP00981340A EP00981340A EP1157336B1 EP 1157336 B1 EP1157336 B1 EP 1157336B1 EP 00981340 A EP00981340 A EP 00981340A EP 00981340 A EP00981340 A EP 00981340A EP 1157336 B1 EP1157336 B1 EP 1157336B1
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Prior art keywords
cache memory
cache
address
main memory
addresses
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English (en)
French (fr)
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EP1157336A1 (de
Inventor
Adwin H. Timmer
Françoise J. HARMSZE
Jeroen A. J. Leijten
Jozef L. Van Meerbergen
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NXP BV
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NXP BV
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Definitions

  • Cache memory is conventionally used to speed up access to data from a main memory.
  • Each cache memory location can be used as a placeholder for a selectable one of a number of main memory locations.
  • the cache memory determines the cache memory location that acts as placeholder for the main memory location that is addressed by the main memory address. This cache memory location is subsequently used instead of the main memory location.
  • the determination of the cache memory location from the main memory address will be called address mapping.
  • the type of address mapping used in the cache memory is an important design parameter of the cache memory. Different types of address mapping are used in fully associative caches, set-associative caches and direct-mapped caches.
  • the fully associative cache contains an address mapping unit that can map each main memory address (or memory block address) to any cache location (or block of locations). This requires an address-mapping unit that, given a main memory address, determines which, if any, of the cache locations is currently associated with that main memory address. For this purpose the mapping unit has to perform a costly associative memory function, which potentially slows down access speed.
  • a direct mapped cache there is no choice as to which cache memory location corresponds to a main memory address: a given main memory address can map only to a single cache memory location. Thus an address-mapping unit in the direct cache can easily determine the required cache memory location. However, when the cache memory location is already in use for another main memory address, the data for that other main memory address will have to be removed from the cache memory, even if that data is still useful. This is a disadvantage compared with the fully associative cache, which can store data for any combination of main memory addresses.
  • a set-associative cache is a compromise between the direct mapped cache and the fully associative cache.
  • the set-associative cache uses sets of cache memory locations (a set being smaller than the whole cache memory). Each memory address corresponds to a set.
  • the main memory address can be associated with any cache location in its corresponding set of cache memory locations.
  • it is easier to determine a cache memory location from a main memory address because the associative memory function has to be performed only within the set corresponding to that main memory address.
  • data has to be removed from the cache less often than in a direct mapped cache, because there i choice of memory locations within the set, so that data for combinations of main memory addresses can be stored in the set.
  • the fully associative cache, a set-associative cache and the direct mapped cache differ in the number of alternative cache memory locations that can be used for the same memory address.
  • This number is a fixed design parameter and it is successively smaller for fully associative caches, set-associative caches and direct-mapped caches. The larger this number, the less frequently it will be necessary to remove useful data from the cache to make room for new data. However, making this number larger also increases the complexity of the cache and it may decrease its access speed. Thus, the choice of this number represents an important tradeoff in cache design.
  • the data processor according to the invention is described in Claim 1.
  • set-associative mapping this data processor limits the number of associations between main memory addresses and cache memory locations that need to be consulted to determine a cache memory location that is to be accessed.
  • the search for an association is limited to a group of associations, as it is limited to a set in set-associative mapping. Within each group associative mapping is possible to any cache memory location assigned to the group. But in contrast to set-associative mapping, the cache memory locations are dynamically assigned to the groups.
  • the number of assigned memory locations may can be made dependent on the needs of the program or program part that is executed. This number may vary at least between a zero and a non-zero number of cache memory locations.
  • the mapping can be adapted to the needs of the program without an overhead in cache memory locations.
  • the program executed by the processor selects dynamically (that is, during execution of a program) which and how many memory addresses are involved in associative relations of each group.
  • a high cache performance is can be guaranteed for those memory addresses. For example if the number of main memory addresses that can be associated simultaneously in one group is equal to the number of addresses needed for a certain real time task, real time response of the cache can be guaranteed.
  • main memory addresses can be mapped to certain cache memory locations in one group and in another program main memory addresses can be mapped to those cache memory addresses in another group.
  • the processor is arranged to prefetch or write one or more streams of data from iteratively computed main memory addresses (separated for example by a fixed address step size). At any point in time only a window of the addresses in the stream that have been used before will be used later as well.
  • the addresses for these streams are mapped using the first group, whereas other addresses are mapped with other groups.
  • the remaining groups may use set associative mapping, i.e. the main memory address may be mapped directly on one of the remaining groups.
  • each stream may have its own group of associations of addresses from the stream with cache memory locations assigned to that group.
  • the remaining cache memory locations are accessed with set associative mapping.
  • cache memory locations can be assigned to different streams on an "as needed" basis and the remaining cache memory locations can be used for non-stream addresses.
  • the group to be used for a memory access instruction can be selected on an instruction by instruction basis, the instructions indicating explicitly what type of address mapping should be used to access their own operands or results, i.e. by indicating a stream.
  • an instruction may indicate the type of address mapping for use by other instructions, for example by specifying a range or set of main memory addresses for which a specific type of address mapping is to be used. The former is more flexible; the latter requires less instruction overhead.
  • Cache memory locations used for one group will generally not be available for use in another group.
  • set associative mapping is used for main memory addresses that do not belong to any stream, removal of a cache address from a set reduces the effectivity of that set.
  • the cache memory addresses that are used for a group that supports a stream are selected evenly from different sets used in set associative mapping.
  • Figure 1 shows a data processor that comprises a processing unit 10, a main memory 12 and a cache memory unit 14.
  • the cache memory unit 14 contains a cache memory 140, a cache control unit 146 and an address-mapping unit 141, comprising a first and second address-mapping sub-unit 142, 144.
  • the processing unit 10 has an address output and a cache mechanism selection output coupled to the address mapping units 142, 144 and the cache control unit 146.
  • the address mapping units 142, 144 and the cache control unit have a cache address output coupled to the cache memory 140.
  • the address mapping units 142, 144 have a cache miss handling interface coupled to the cache control unit 146.
  • the cache control unit has a main memory address output coupled to the main memory 12.
  • the main memory 12 has a data output coupled to the cache memory 140.
  • the processing unit 10 executes a program that causes it to issue a main memory address for reading or writing data, in combination with implicit or explicit information that indicates a cache address mapping unit 142, 144 that is to be used for that main memory address.
  • the signal selects the appropriate one of the address mapping units 142, 144, which determines whether the data corresponding to the address is present in the cache memory 140. If so, the corresponding cache memory address is retrieved and supplied to the cache memory 140. In response, the cache memory 140 supplies the data for that address to the processing unit 10.
  • the cache control unit 146 determines which cache memory locations may be mapped to by the first address mapping unit 142. This is done under program control. A program executing in the processor indicates how many cache memory locations are needed for mapping with the first address mapping unit. Thereupon, the cache control unit selects a sufficient number of those locations and signals the selected locations to the cache mapping unit, so that main memory addresses can be mapped to those locations.
  • Cache control unit 146 contains for example a suitably programmed microcontroller core to perform these functions.
  • cache mapping units 142, 144 each with its own dynamically selected group of cache memory addresses to which the cache mapping unit can map main memory addresses.
  • a main memory address is signaled to the cache mapping units 142, 144 and the selected address mapping unit 142, 144 does not detect that the data corresponding to the main memory address is present in the cache memory 140, there is a cache miss for the main memory address.
  • the address mapping unit 142, 144 signals the cache miss to the cache control unit 146.
  • the cache control unit 146 supplies the main memory address to the main memory 12 to fetch the data for that address.
  • the cache control unit selects a cache mapping unit 142, 144 for the address.
  • the cache control unit 146 also selects a cache memory address for the data from the cache memory addresses assigned to that cache mapping unit 146.
  • the data from main memory 12 is stored in cache memory 140 at the selected cache memory address and supplied to the processing unit 10.
  • the cache control unit 146 signals the selected cache memory address to the cache mapping units 142, 144. If the cache memory address was in use for another main memory address, the cache mapping units 142, 146 ensure that that other main memory address will no longer be mapped to the selected cache memory address. At least the selected one of the cache mapping units 142, 144 records that data has been stored in cache memory 140 for the main memory address at the selected cache memory address. In an embodiment, both cache mapping units 142, 144 record the association between the cache memory address and the main memory address at least for some cache memory addresses.
  • the cache control unit 146 selects the selected cache memory address according to some cache replacement strategy and dependent on the address mapping used in the selected cache-mapping unit 142, 144.
  • Some cache replacement strategy are known per se to the skilled person.
  • An example of a strategy is the "least recently used" (LRU) strategy. According to this strategy, the cache control unit 146 determines which of the cache memory addresses has not been used longer than any other cache memory address. That LRU cache memory address is then selected for storing data for the main memory location.
  • LRU least recently used
  • the cache control unit selects the cache memory address from the cache memory addresses that are available for the main memory address in the selected cache-mapping unit 142, 144, again according to some strategy such as LRU.
  • Address mapping units 142, 144 may use mutually different address mapping mechanisms.
  • the first address mapping unit 142 uses fully associative address mapping to a dynamically selected, limited set of cache memory addresses and the second address mapping unit 144 uses set associative mapping to all cache memory address, preferably minus those used in the first address mapping unit 142. Implementations of address mapping units for these and other kinds of mapping are known per se.
  • data from main memory 10 is fetched and stored in cache memory 140 in units of cache lines, each of which comprises data for a plurality of successive addresses with the same most significant bits.
  • a fully associative mapping unit these most significant bits (the tag bits) of those main memory addresses that are represented in cache memory 140 are stored for each cache memory address that can be mapped by the fully associative mapping unit.
  • the tag bits of an incoming main memory address are compared with the tag bits of stored addresses. If there is a match, the associated cache memory address is returned.
  • a set associative mapping unit the most significant part of the main memory address is divided into set selection bits and tag bits.
  • the set selection bits are translated into cache address bits in a predetermined way. These cache address bits select a set of cache memory locations.
  • the tag bits are used to select among this limited number of cache memory addresses, just as the tag bits are used in the fully associative mapping unit to select among all usable cache memory addresses.
  • the fully associative cache mapping unit may map main memory addresses to cache memory locations that belong to different sets (as defined by the set-associative cache mapping unit), even when the set-associative mapping unit would map them to the same set.
  • more main memory locations that map to the same set can be present in cache memory 140 than would be possible using a set-associative cache mapping unit on its own.
  • the fully associative cache does not need to provide the ability to map to all of the cache memory 140 in this case, because unmapped addresses are still useful for the other mapping mechanism. Hence the fully associative cache-mapping unit may be kept small. Different cache replacement strategies may be used for cache memory addresses that are mapped by different cache mapping units 142, 144.
  • the fully associative mapping unit may be limited to special types of memory access. For example, in case of a program that uses stream access, a part of the main memory addresses comes from a series of addresses that can be computed in advance (for example addresses at fixed distances from one another). In stream access, the main memory addresses that can be used at a point in time lie in a window in the series (i.e. of all addresses in the stream that have been used before the point in time only those in the window can be used later). This window shifts in time.
  • the cache memory 140 has to store data for the addresses in the window. That is, the cache memory 140 stores data for a window of successive addresses in the series. The data accessed in this way may involve prefetched data for reading by the processor and/or data written by the processor at the computed addresses.
  • stream prefetching and writing is known per se.
  • stream prefetching is implemented using a stream prefetch unit (not shown), which monitors addresses or address indications issued by the processor and compares them with a current stream address. Either all issued addresses are compared or only those addresses or indications that the processor identifies as stream addresses. If there is a match, the stream prefetch unit computes a next main memory address in the stream and submits this address to the cache in order to cause the data corresponding to this address to be stored in the cache memory.
  • Figure 2 shows a fully associative mapping unit for stream access.
  • the mapping unit contains a base address register 20, a top address register 21, a base index register 22, an index computation unit 24, an address comparison unit 25 and an address memory 26 all coupled to the cache miss handling interface 28 (connections not shown for clarity).
  • the address input of the mapping unit is coupled to the index computation unit 24 and the address comparison unit 25.
  • the base address register 20 is coupled to the index computation unit 24.
  • the top address register 21 is coupled to the address comparison unit 25.
  • the base index register 22 is coupled to the index computation unit 24.
  • the index computation unit 24 has an index output coupled to the address memory 26.
  • the address memory 26 has an input coupled to the mapping mechanism selection input of the mapping unit and an output coupled to the address output of the mapping unit.
  • the mapping unit serves to supply cache memory addresses for a window in the series of cache memory addresses used in stream access.
  • a fixed set of cache memory addresses is used for the stream.
  • the cache control unit 146 loads the address memory 26 with a number of cache memory addresses for storing data for the stream. These cache memory address that will not normally be changed as the window advances. These cache memory addresses will be used cyclically for the addresses in the series. This has the advantage that the cache memory addresses can be computed without comparison of the main memory address with all available address, as in the case of conventional fully associative mapping units.
  • Base address register 20 contains the oldest main memory address A0 from the series that is present in cache memory 140.
  • Top address register 21 contains the youngest main memory address AN from the series that is present in cache memory 140.
  • Base index register 22 contains the address 10 of a location in address memory 26 that contains the cache address that stores data for the oldest main memory address.
  • Address comparison unit 25 signals when a main memory address outside the currently stored window is used. If so, cache control unit 146 loads data for that main memory address from main memory 12 into cache memory 140 at address A0 and updates A0, AN and I0. Preferably, data for the stream is prefetched, that is, its main memory address is applied to cache memory unit 14 before the program actually needs the data. Thus, no cache miss delay need be incurred.
  • data for the cached main memory addresses is stored in a series of cache memory locations, which are used cyclically for successive addresses from a stream of addresses. Indices in the series are computed from the addresses from the stream and used to determine the addresses in the series. In the example, the latter is realized by means of an address memory, but of course other realizations may be used, such as using the index directly to address the cache memory relative to some base address.
  • mapping unit of fig. 2 is but an advantageous example of a mapping unit. Without deviating from the invention other fully associative mapping units may be used.
  • cache control unit 146 selects a cache memory address for a main memory location on a cache miss.
  • the cache mapping unit 142, 144 are a fully associative mapping unit and a set-associative mapping unit respectively
  • the cache control unit 146 selects the cache memory addresses for use by the fully associative mapping unit so that they are evenly spread out over the different sets of the set-associative mapping unit.
  • the fully associative mapping unit has full freedom of associating a main memory address with any cache memory address.
  • the set-associative mapping unit on the other hand can map a main memory address only to one of a number of cache memory addresses in a relatively small set.
  • that cache memory address will be said to be "occupied” by the fully associated mapping unit.
  • Only those cache memory address in a set that are not "occupied" by the fully associative cache mapping unit can be used by the set-associative mapping unit without interfering with the fully associative mapping unit, usually, occupation is enforced by some hardware locking mechanism that disables replacement in the cache at occupied locations by the set associative mapping unit.
  • cache control unit 146 preferably selects cache memory addresses for fully associative mapping avoiding cache memory addresses from those sets that contain more occupied cache memory addresses than other sets. Thus the maximum number of cache memory addresses that is occupied in any set is minimized.
  • the cache control unit 146 maintains a linked list of cache memory addresses that are not used by the fully associative mapping unit. Initially, this list cycles through the sets: cache memory addresses that appear successively in this list belong to successively different sets, until cache memory addresses from all set have appeared and from there the list runs through all sets again and so on.
  • the list may contain (A0, A1, A2, A3, A4, A5, A6, A7, A8, A9...) successively, where A0, A4, A8 belong to a first set, A1, A5, A9 belong to a second set, A2, A6 belong to a third set and so on.
  • the cache control unit 146 needs to select cache memory addresses for use in the fully associative mapping unit, the cache control unit selects these cache memory in the order that they appear in the list.
  • cache memory addresses When cache memory addresses are released from use in the fully associative cache, they are put back in the list in a sequence that preserves the property that successive addresses from the same set are separated by addresses from a maximum possible number of addresses from other sets.
  • a program run by the processing unit 10 preferably declares a stream when it starts using that stream, the declaration specifying implicitly or explicitly a number of cache memory addresses that is to be used for the stream. When the stream starts the required number of cache memory locations is taken from successive positions in the list.
  • the processing unit 10 outputs a signal indicating whether a memory address belongs to a stream and, if so, to which stream.
  • the signal selects the cache-mapping unit 142, 144 that is to be used. If there is a cache miss, the signal also enables the cache control unit 146 to select the cache mapping unit 142, 146 that has to map the main memory address.
  • the processing unit 10 may issue the main memory address in the form of a complete address or in the form of an index relative to a current window in the stream.
  • the selected cache-mapping unit is determined by checking whether the main memory address issued by the processing unit 10 belongs to a specified range or collection of addresses.
  • a program instruction defines a ranges or collection of main memory addresses which must be mapped by the fully associative cache mapping unit. If there is a cache miss, the cache control unit 146 selects the cache mapping unit 142, 146 that has to map the main memory address on the basis of whether it belongs to such a range or collection. Belonging to such a range or collection may also be used to select the address-mapping unit 142, 144 during normal address mapping.
  • all address mapping units 142, 144 in parallel may try to determine a cache memory address for a main memory address issued by the processing unit 10. If any one of the cache mapping units 142, 144 does not report a cache miss, the cache memory address produced by that cache mapping unit 142, 144 may be used to address cache memory 140. If all of the cache mapping units 142, 144 report a cache miss, the cache control unit 146 is triggered to fetch data from main memory 12. If more than one address mapping unit 142, 144 reports a cache hit, only one of the cache memory addresses reported by the address mapping units 142, 144 needs to be used for a memory read operation. In case of a memory write operation, the data may be written to all reported cache memory locations, or only to one of the reported locations, the data in the other reported locations being invalidated.

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Claims (9)

  1. Ein Datenprozessor mit einem Cachespeicher, wobei der Cachespeicher umfasst:
    - einen Eingang zum Empfangen einer Hauptspeicheradresse;
    - Cachespeicherstellen;
    - Assoziativspeicher zum Speichern mindestens einer ersten und zweiter Gruppen von Assoziationen jeweils zwischen einer jeweiligen Hauptspeicheradresse und Cachespeicherstelle, wobei mindestens eine Cachespeicherstelle unterschiedlichen der Gruppen dynamisch zuweisbar ist, um in Assoziationen der zugewiesenen Gruppe verwendet zu werden;
    - Auswahlmittel zum Auswählen einer ausgewählten Gruppe für die Hauptspeicheradresse;
    - eine Adressabbildungseinheit, die zum Auswählen und Adressieren einer adressierten Cachespeicherstelle eingerichtet ist, die mit der Hauptspeicheradresse in der ausgewählten Gruppe assoziiert ist.
  2. Ein Datenprozessor nach Anspruch 1, der eine Stromzugriffseinheit zum Zugreifen auf Daten im Cachespeicher für einen Strom iterativ berechneter Hauptspeicheradressen umfasst, wobei der Datenprozessor so eingerichtet ist, dass er die Hauptspeicheradressen von Daten aus dem Strom, auf die beim Zugriff für jenen Strom zugegriffen wird, alle unter Verwendung von Assoziationen der ersten Gruppe mit Cachespeicherstellen assoziiert.
  3. Ein Datenprozessor nach Anspruch 2, wobei das Auswahlmittel die Satzassoziativabbildung verwendet, die Hauptspeicheradressen jeweils in ihrer eigenen der zweiten oder weiteren der Gruppen direkt abbildet, wobei jede der zweiten oder weiteren der Gruppen Cachespeicherstellen aus einem eigenen Satz ihr zugewiesener Cachespeicherstellen aufweist, wobei der Datenprozessor Cachespeicherstellen dynamisch der ersten Gruppe zuweist, wobei eine solche Zuweisung die Zuweisung der Cachespeicherstellen an die zweiten und weiteren der Gruppen sperrt.
  4. Ein Datenprozessor nach Anspruch 3, wobei der Datenprozessor die Zuweisung von Cachespeicherstellen an die erste Gruppe gleichmäßig über die unterschiedlichen Sätze verteilt.
  5. Ein Datenprozessor nach Anspruch 2, wobei die Adressabbildungseinheit die Hauptspeicheradressen, für welche die erste Gruppe ausgewählt ist, auf der Grundlage ihrer Rangordnung im Strom abbildet.
  6. Ein Datenprozessor nach Anspruch 2, der eine Stromzugriffseinheit zum Zugreifen auf Daten für zwei oder mehrere Ströme iterativ berechneter Hauptspeicheradressen in den Cachespeicher umfasst, wobei die Hauptspeicheradressen von Daten aus jedem Strom, auf die bei einem solchen Zugriff zugegriffen wird, alle unter Verwendung von Assoziationen einer jeweiligen der Gruppen, die jenem Strom zugeordnet sind, mit Cachespeicherstellen assoziiert werden.
  7. Ein Datenprozessor nach Anspruch 1, der zum Empfangen und Verarbeiten eines Befehls zum Definieren eines Satzes von Hauptspeicheradressen zur Verwendung in Assoziationen in der ersten Gruppe eingerichtet ist.
  8. Ein Datenprozessor nach Anspruch 1, wobei Cachespeicherstellen zur Wiederverwendung für eine andere Hauptspeicheradresse ausgewählt werden, wobei die Cachespeicherstellen, die in Assoziationen der ersten Gruppe verwendet werden, zur Wiederverwendung gemäß Unterschieden in der früheren Verwendung von Cachespeicherstellen in der ersten Gruppe, unabhängig von der früheren Verwendung von Cachespeicherstellen in anderen Gruppen ausgewählt werden.
  9. Ein Datenprozessor nach Anspruch 1, der eine Verarbeitungseinheit zum Ausführen eines Befehls mit einem Operanden oder Ergebnis umfasst, das die Hauptspeicheradresse referenziert, wobei der Befehl die auszuwählende Gruppe anzeigt, die zum Zugreifen auf den Operanden oder das Ergebnis des Befehls verwendet wird.
EP00981340A 1999-12-17 2000-12-04 Datenprozessor mit cachespeicher Expired - Lifetime EP1157336B1 (de)

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EP99204375 1999-12-17
EP99204375 1999-12-17
PCT/EP2000/012231 WO2001044948A1 (en) 1999-12-17 2000-12-04 Data processor with cache
EP00981340A EP1157336B1 (de) 1999-12-17 2000-12-04 Datenprozessor mit cachespeicher

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EP1157336B1 true EP1157336B1 (de) 2009-07-29

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EP (1) EP1157336B1 (de)
JP (1) JP2003517682A (de)
KR (1) KR100810781B1 (de)
CN (1) CN1206594C (de)
DE (1) DE60042640D1 (de)
WO (1) WO2001044948A1 (de)

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JP2003517682A (ja) 2003-05-27
DE60042640D1 (de) 2009-09-10
KR20010102210A (ko) 2001-11-15
US20020004876A1 (en) 2002-01-10
CN1347527A (zh) 2002-05-01
WO2001044948A1 (en) 2001-06-21
EP1157336A1 (de) 2001-11-28
KR100810781B1 (ko) 2008-03-06
US6643738B2 (en) 2003-11-04

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