EP1151541A1

EP1151541A1 - A low energy adc

Info

Publication number: EP1151541A1
Application number: EP00902234A
Authority: EP
Inventors: Jan-Erik Eklund
Original assignee: Infineon Technologies AG; Telefonaktiebolaget LM Ericsson AB
Current assignee: Infineon Technologies AG
Priority date: 1999-01-20
Filing date: 2000-01-13
Publication date: 2001-11-07
Also published as: KR100890842B1; SE9900157D0; AU2336300A; SE513434C2; WO2000044099A1; CN1338151A; SE9900157L; CA2359677A1; KR20010101464A; JP2002535909A

Abstract

The present invention relates to a parallel analog to digital converter (ADC) that includes at least two A/D channels which have an input and an output, where the analog input signal is converter to a digital output signal, and where each of the inputs of the A/D channels is coupled to a sample and hold unit, a multiplexing unit which includes at least two inputs, where each of the inputs is coupled to the output of the A/D channel, a time control unit for clocking the A/D channels and for controlling the multiplexing unit, wherein the analog to digital converter is provided with means for switching between a so-called idle mode and a so-called normal mode. The invention also relates to a method of saving energy in parallel analog to digital conversion.

Description

A LOW ENERGY ADC

FIELD OF INVENTION

The present invention relates to a parallel analog to digital converter, and to a method of parallel analog to digital conversion in accordance with the preambles of respective Claims 1 and 7.

DESCRIPTION OF THE BACKGROUND ART

A parallel analog to digital converter according to earlier known states of the art is taught in publication "A 10-b, 100- MS/s CMOS A/D Converter, Kwang Young Kim, Student Member, IEEE, Naoya Kusayanagi, and Asad A. Abidi, Fellow, IEEE Journal of Solid State Circuits, Vol. 32, No. 3, March 1997, among others.

One problem with analog to digital converters of this kind is that they consume unnecessary high levels of energy.

SUMMARY OF THE INVENTION

The object of the present invention is to reduce the power consumption of a parallel analog to digital converter.

This problem is addressed in accordance with the present invention with an arrangement and a method according to the characterising clauses of respective Claims 1 and 7.

The environment with which a parallel analog to digital converter is envisaged for use is a system in which activity varies with use, for instance in a DSL modem (Digital Subscriber Loop) , or in mobile telephony system. These are two equivalent systems, although not necessarily mutually identical, which communicate with one another via a communications channel, consisting, for instance, of a cable or of radio waves. It is pos'sible that many units share one and the same communications channel, which is the case when communication takes place via radio waves.

One advantage with the present invention is that energy can be saved by adapting the A/D converter to prevailing requirements, instead of solely using the on/off modes as was earlier the case.

Another advantage with the invention is that the method can be readily implemented in a parallel A/D converter.

The invention will now be described in more detail with reference to preferred embodiments thereof and also with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

Figure 1 illustrates an embodiment of a parallel analog to digital converter in which the inventive power-saving function can be implemented.

Figure 2 illustrates another embodiment of a parallel analog to digital converter in which the inventive power-saving function can be implemented.

DESCRIPTION OF PREFERRED EMBODIMENTS

In the illustrated embodiment of a parallel analog to digital converter according to Figure 1, an analog input signal 5 is excited into four A/D channels 20, 22, 24 and 26, each of which includes a respective sample and hold unit 21, 23, 25 and 27. The A/D channels have a signal input and a signal output. The sample and hold units 21, 23, 25 and 27 are monitored and controlled by a time control unit 10. The A/D channels 20, 22, 24 and 26 are connected to a supply voltage source 50, which in the illustrated case is an external supply. Supply voltage switches 30, 32, 34 and 36 are disposed between the supply voltage source 50 and each of the A/D channels. The signals 40, 42, 44 and 46 steer the A/D channels between a normal state and a rest state under the control of the activity control 15. The activity control 15 is, in turn, controlled by a system control unit (not shown) . The outputs on the A/D channels 40, 42, 44 and 46 are multiplexed together in a multiplexing unit 17. The output signal from the multiplexing unit 17 is a digital representation of the analog input signal.

Because the parallel A/D converter has an operating cycle that extends over several clock periods, it is necessary to determine the start time. The A/D channels are, in principle, independent of each other. The time control unit 10 tells when each channel shall begin. The time control unit 10 can also be used to reduce power consumption. If the operation sequence consumes more energy than in a rest state, energy can be saved by starting the A/D channels less frequently. A more positive way of saving energy, is to switch off the supply voltage 50 via the switches 30, 32, 34 and 36. The supply voltage 50 may be +5V, for instance.

In the case of the embodiment of a parallel analog to digital converter shown in Figure 2, an analog input signal 5 is excited into four A/D channels 20, 22, 24 and 26 via a common sample and hold unit 21. The A/D channels include a signal input and a signal output. The sample and hold unit 21 is monitored and controlled by a time control unit 10. A supply voltage source 50 is connected to the A/D channels 20, 22, 24 and 26, this source being an external source in the illustrated case. Supply voltage switches 30, 32, 34 and 36 are disposed between the supply voltage source 50 and each of the A/D channels. The signals 40, 42, 44 and 46 steer the A/D channels between a normal state and a rest state, under the control of the activity control 15. The activity control 15 is, in turn, controlled by a system control unit (not shown) . The outputs on the A/D channels 40, 42, 44 and 46 are multiplexed together in a multiplexing unit 17. The output signal from the multiplexing unit 17 is a digital representation of the analog input signal.

The Figure 2 embodiment differs from the Figure 1 embodiment in that the utility signal (the input signal) is sampled with each period and A/D converted at selected times, instead of being solely sampled and A/D converted at chosen times. The principle difference is that it may be practical for some reason or other to shut off only a part of the A/D converter and allow the remainder of the converter to operate as usual. Although savings in energy will be smaller in this case, it may be a necessary procedure when problems are experienced with a startup routine. The S/H unit 21, 23, 25 and 27, is an example of a part of the A/D converter that may be constantly active.

In certain instances, several of the A/D channels can be switched-off in a parallel analog to digital converter, so as to save energy. A wake-up tone, or alert tone, can be detected with one or a few A/D channels. The frequency cannot be positively determined. However, if a signal that could possibly be a correct signal occurs, the other A/D channels are alerted and a closer investigation is made.

A waiting mode often requires a lower performance. A low performance can be achieved, for instance, by lowering the clock frequency or changing the current in comparators and operational amplifiers, which are building blocks in the A/D channels .

An A/D converter of the pipe-lined or successive approximation type operates with an algorithm to find the digital representation of an analog input signal. The algorithm begins with the most significant bits, such as to obtain a sub-result. The accuracy of the sub-result increases as the bits are calculated. When the required precision of the digital output signal is low, energy can be saved by terminating the conversion subsequent to having achieved a predetermined degree of accuracy.

Generally speaking, a high power input is required to achieve a high performance. Not much precision or energy consumption is required to detect the presence of an activating signal. Several situations are conceivable in this regard. A first situation is one in which the communications channel is quiet when not in use. A signal is sent when the system shall be activated. This is sufficient to detect the presence of a signal. A second situation is when noise or other traffic is present on the communications channel when the channel is not in use. It is then necessary to detect a particular tone or groups of tones. It is sufficient, however, to detect the presence of the tone or tones. A third situation is when the incoming activating signal contains a message or an address stating that a certain unit shall be activated. It is necessary to first decode the message in this case. According to the invention, the analog to digital conversion is used in the first situation to detect the presence of a signal. This detection is effected by analysing received data. An activating signal is assumed to contain less information than a real message signal. The reception requirement may therefore be low, although sufficient to detect a signal. This can be achieved with a few A/D channels or solely one A/D channel. The precision in the A/D channel may also be reduced, as before described.

According to the invention, the analog to digital converter must be used intelligently in the second situation. The specification applicable for a signal and noise is used as a basis for the number of channels that must be used. It is assumed that the requirement is lower in this respect than in respect of full operation. When one or more tones shall be detected, it is perhaps not possible to detect said tones in a unique manner. Aliasing? will change the frequency representation on the output of the A/D converter. A parallel analog to digital converter takes samples at the time points n/fs, where n is an integer and fs is the effective sampling frequency for the parallel analog to digital converter. Each channel takes samples at a time spacing of m/fs, where m is the number of channels. The sampling frequency for each channel is then fs/m. A time control unit determines when the various channels shall take their respective sample. If it is assumed that the samples shall be evenly spread in time, the first channel will take its sample at the times mxn/fs and the second channel will take its sample at the times (mxn+m-1) /fs. According to Nyqvist, analog frequencies are unique in the time discrete representation arriving from the analog to digital converter for up to half the sampling frequency. Although the frequency representation will not be unique when some channels are switched-off, the analog frequency which digital representation obtains will be known.

If the analog to digital converter waits to detect a signal outside the frequency band that can be represented uniquely, it can be gathered from the sampled values whether or not it is possible to assume that the received tone is correct. By correct frequency is meant, for instance, that when fs is 44MHz and the tone is 10MHz and all permitted input signals to the ADC are in the frequency band 0-22MHz, it will be possible to detect the tone 10MHz clearly. If three of four A/D channels are now shut off, the effective sampling frequency is changed to 11MHz. According to Nyqvist' s sampling theorem, tones having the frequency 1MHz, 10MHz, 12MHz and 21MHz will have identical appearances in the output data of the A/D converter.

When the tone is a narrow-band tone and it is known from the system specification that no tone other than the wake-up tone may be sent, it is highly likely that the tone can be detected. In doubtful cases, it is necessary to activate the analog to digital converter so as to decide definitely what is received.

In the third situation, if the message is a narrow-band message the message can be detected without fully activating the analog to digital converter, owing to the fact that the frequency representation is unique even with low precision of the A/D converter. When the message is a broadband message, it is necessary to activate the entire analog to digital converter.

A channel can be switched off and therewith energy saved, by fully throttling the supply current to one or more A/D channels, by switching off one or more of the switches 30, 32, 34 or 36.

An alternative method is to switch-off the circuit clock. If the clock is static it suffices to switch the clock off, although when the clock includes dynamic modes it is often beneficial to switch-off the voltage supply via the switches 30, 32, 34 and 36. The problem with dynamic modes is that the logic value is sustained with the aid of a charge in a capacitor. This charge is liable to leak away with time. The charges are normally updated with each clock period. A 10% charge leakage will not have any great effect, because it is still possible to distinguish between a logic 1 and a logic 0. However, a large amount of the charge can leak out, when the clock is switched-off over a long period of time. If the dynamic mode is an input to an inverter and the potential reaches somewhere between earth and supply voltage, a short circuit can occur through the inverter due to the passage of a large current therethrough.

An inverter, a logic block (gates) in CMOS will normally include two transistors. If the inverter input is connected to earth, then one of said transistors will conduct, whereas if the inverter input is connected to the supply voltage, then the other transistor will conduct. Both transistors are able to conduct at voltages therebetween, i.e. a voltage between earth and the supply voltage.

The analog part of the A/D channel, e.g. comparators and operational amplifiers, will often have control signals, for controlling the standing or quiescent current, for instance. These control signals can be used to switch-off the analog part of the A/D channel.

It is conceivable to only switch-off the major part of the circuit for practical reasons. As shown in Figure 2, it is also conceivable to include a common sample and hold unit.

Claims

1. A parallel analog to digital converter (ADC) which comprises : - at least two A/D channels which include a signal input and a signal output, where the analog input signal is converted to a digital output signal, and where each of the signal inputs on the A/D channels is coupled to a sample and hold unit;

- a multiplexing unit which includes at least two inputs and an output, where each of said inputs is coupled to the output of said A/D channel; and

- a time control unit for clocking the computing channels and for controlling the multiplexor unit; characterised in that said analog to digital converter is provided with means for switching between a so-called idle mode and a so-called normal mode.

2. A parallel analog to digital converter according to Claim 1, characterised in that at least one A/D channel is fully or partially switched-off in the idle mode of said converter.

3. A parallel analog to digital converter according to Claim

1, characterised in that the clock frequency of the time control unit is lowered in the idle mode.

4. A parallel analog to digital converter according to Claim

2, characterised in that the current to the A/D channel is reduced or completely switched-off.

5. A parallel analog to digital converter according to any one of the preceding Claims, characterised in that at least one A/D channel in the analog to digital converter is adapted to detect an activating signal and to switch the analog to digital converter from an idle mode to a normal mode.

SUBSTTTUTE SHEET (RULE 26)

6. A parallel analog to digital converter according to Claims 1-4, characterised in that said analog to digital converter is adapted to switch to an idle mode after the lapse of a given signal absence time in at least one of the A/D channels.

7. A method relating to parallel analog to digital conversion, comprising the steps of:

- converting the analog input signal to a digital output signal with the aid of at least two A/D channels that include a signal input and a signal output and where each of the signal inputs on the A/D channels are coupled to a sample and hold unit;

- multiplexing the digital output signals from each of the A/D channels together in a multiplexing unit; and clocking and controlling the A/D channels and the multiplexing unit with the aid of a time control unit; characterised by the further step of switching the analog to digital converter between a so-called idle mode and a so-called normal mode .

8. A method relating to parallel analog to digital conversion in accordance with Claim 7, characterised by switching-off at least one A/D channel in the idle mode, either completely or partially.

9. A method relating to parallel analog to digital conversion in accordance with Claim 7, characterised by lowering the clock frequency of the time control unit in said idle mode.

10. A method relating to parallel analog to digital conversion in accordance with Claim 9, characterised by reducing or completely switching-off the current to said A/D channel.

11. A method relating to parallel analog to digital conversion according to any one of Claims 7-10, characterised by detecting an activating signal by at least one A/D channel in the analog to digital converter; and by switching the analog to digital converter from an idle mode to a normal mode. O 00/44099

12. A method relating to parallel analog to digital conversion according to any one of Claims 7-10, characterised by switching the digital converter from its normal mode to its idle mode when a certain period of signal absence is noted in at least one of the A/D channels.