EP1133732A4 - Architecture d'ordinateur fractionnee - Google Patents

Architecture d'ordinateur fractionnee

Info

Publication number
EP1133732A4
EP1133732A4 EP99960160A EP99960160A EP1133732A4 EP 1133732 A4 EP1133732 A4 EP 1133732A4 EP 99960160 A EP99960160 A EP 99960160A EP 99960160 A EP99960160 A EP 99960160A EP 1133732 A4 EP1133732 A4 EP 1133732A4
Authority
EP
European Patent Office
Prior art keywords
input
module
output
interface
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP99960160A
Other languages
German (de)
English (en)
Other versions
EP1133732A1 (fr
Inventor
Remigius G Shatas
Robert R Asprey
Christopher L Thomas
Greg O'bryant
Greg Luterman
Jeffrey E Choun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avocent Huntsville LLC
Original Assignee
Cybex Computer Products Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cybex Computer Products Corp filed Critical Cybex Computer Products Corp
Publication of EP1133732A1 publication Critical patent/EP1133732A1/fr
Publication of EP1133732A4 publication Critical patent/EP1133732A4/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/329—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the application layer [OSI layer 7]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Saccharide Compounds (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Computer And Data Communications (AREA)
  • Debugging And Monitoring (AREA)
EP99960160A 1998-10-30 1999-10-29 Architecture d'ordinateur fractionnee Ceased EP1133732A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10625598P 1998-10-30 1998-10-30
US106255P 1998-10-30
PCT/US1999/025290 WO2000026796A1 (fr) 1998-10-30 1999-10-29 Architecture d'ordinateur fractionnee

Publications (2)

Publication Number Publication Date
EP1133732A1 EP1133732A1 (fr) 2001-09-19
EP1133732A4 true EP1133732A4 (fr) 2003-01-22

Family

ID=22310393

Family Applications (2)

Application Number Title Priority Date Filing Date
EP99960160A Ceased EP1133732A4 (fr) 1998-10-30 1999-10-29 Architecture d'ordinateur fractionnee
EP99957481A Expired - Lifetime EP1125210B1 (fr) 1998-10-30 1999-10-29 Ordinateur fractionne

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP99957481A Expired - Lifetime EP1125210B1 (fr) 1998-10-30 1999-10-29 Ordinateur fractionne

Country Status (7)

Country Link
EP (2) EP1133732A4 (fr)
AT (1) ATE332531T1 (fr)
AU (2) AU1708800A (fr)
DE (1) DE69932252T2 (fr)
ES (1) ES2267303T3 (fr)
HK (2) HK1041530B (fr)
WO (2) WO2000026796A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030033450A1 (en) * 2000-07-20 2003-02-13 John Appleby-Alis System, method, and article of manufacture for remote updating of hardware
AU2001270874A1 (en) * 2000-07-20 2002-02-05 Celoxica Limited System, method and article of manufacture for controlling the use of resources
CN102929756A (zh) * 2012-10-28 2013-02-13 中国电子科技集团公司第十研究所 通用型高速并、串行总线开发验证平台

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4384327A (en) * 1978-10-31 1983-05-17 Honeywell Information Systems Inc. Intersystem cycle control logic
US4959833A (en) * 1989-03-08 1990-09-25 Ics Electronics Corporation Data transmission method and bus extender
EP0395416A2 (fr) * 1989-04-26 1990-10-31 Dubner Computer Systems Inc. Liaison de données pour bus SCSI
EP0844567A1 (fr) * 1996-11-21 1998-05-27 Hewlett-Packard Company Passerelle de PCI-bus à grande distance

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ZA883232B (en) * 1987-05-06 1989-07-26 Dowd Research Pty Ltd O Packet switches,switching methods,protocols and networks
US5430848A (en) * 1992-08-14 1995-07-04 Loral Fairchild Corporation Distributed arbitration with programmable priorities
US5812534A (en) * 1993-01-08 1998-09-22 Multi-Tech Systems, Inc. Voice over data conferencing for a computer-based personal communications system
US5664223A (en) * 1994-04-05 1997-09-02 International Business Machines Corporation System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
US5659707A (en) * 1994-10-07 1997-08-19 Industrial Technology Research Institute Transfer labeling mechanism for multiple outstanding read requests on a split transaction bus
US5799207A (en) * 1995-03-28 1998-08-25 Industrial Technology Research Institute Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device
US5586121A (en) * 1995-04-21 1996-12-17 Hybrid Networks, Inc. Asymmetric hybrid access system and method
EP0834134B1 (fr) * 1995-06-07 2005-02-16 Samsung Electronics Co., Ltd. Reduction du retard dans le transfert de donnees mises en memoire tampon entre deux bus mutuellement asynchrones
US5781747A (en) * 1995-11-14 1998-07-14 Mesa Ridge Technologies, Inc. Method and apparatus for extending the signal path of a peripheral component interconnect bus to a remote location
US5764479A (en) * 1996-09-23 1998-06-09 International Business Machines Corporation Split system personal computer having floppy disk drive moveable between accessible and inaccessible positions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4384327A (en) * 1978-10-31 1983-05-17 Honeywell Information Systems Inc. Intersystem cycle control logic
US4959833A (en) * 1989-03-08 1990-09-25 Ics Electronics Corporation Data transmission method and bus extender
EP0395416A2 (fr) * 1989-04-26 1990-10-31 Dubner Computer Systems Inc. Liaison de données pour bus SCSI
EP0844567A1 (fr) * 1996-11-21 1998-05-27 Hewlett-Packard Company Passerelle de PCI-bus à grande distance

Also Published As

Publication number Publication date
EP1125210A4 (fr) 2002-08-07
AU1517800A (en) 2000-05-22
HK1043409A1 (zh) 2002-09-13
ES2267303T3 (es) 2007-03-01
HK1041530A1 (en) 2002-07-12
AU1708800A (en) 2000-05-22
WO2000026797A9 (fr) 2000-10-19
DE69932252T2 (de) 2007-06-06
DE69932252D1 (de) 2006-08-17
ATE332531T1 (de) 2006-07-15
EP1125210B1 (fr) 2006-07-05
EP1125210A1 (fr) 2001-08-22
EP1133732A1 (fr) 2001-09-19
WO2000026796A1 (fr) 2000-05-11
WO2000026797A1 (fr) 2000-05-11
HK1041530B (zh) 2007-01-19
WO2000026796A9 (fr) 2000-11-30

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