EP1095458A1 - Systeme de production d'un signal periodique precis a faible bruit - Google Patents

Systeme de production d'un signal periodique precis a faible bruit

Info

Publication number
EP1095458A1
EP1095458A1 EP99930808A EP99930808A EP1095458A1 EP 1095458 A1 EP1095458 A1 EP 1095458A1 EP 99930808 A EP99930808 A EP 99930808A EP 99930808 A EP99930808 A EP 99930808A EP 1095458 A1 EP1095458 A1 EP 1095458A1
Authority
EP
European Patent Office
Prior art keywords
signal
digital
delta
noise
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99930808A
Other languages
German (de)
English (en)
Inventor
Daniel Keyes Butterfield
Robert P. Gilmore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP1095458A1 publication Critical patent/EP1095458A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal

Definitions

  • This invention relates to communication systems. Specifically, the present invention relates to systems and techniques for generating accurate low noise periodic signals for use in communication systems.
  • Periodic electronic signals are used in variety of demanding applications including reference oscillators used to modulate and demodulate signals in analog circuits and clocks for digital circuits. Such applications often require very accurate low-noise signals that consume minimal power while maintaining accuracy over a range of frequencies.
  • CDMA code division multiple access
  • signals within a certain range of frequencies must often be translated to a different range or band of frequencies.
  • the accuracy of the clock signal affects the accuracy of the frequency translation.
  • a local oscillator (LO) in a mobile receiver provides a periodic signal that facilitates the translation of incoming radio frequency (RF) signals to an intermediate frequency (IF) band. If the frequency of the local oscillator is inaccurate, the translated signals may be translated outside of the desired IF band.
  • LO local oscillator
  • IF intermediate frequency
  • Digital communications systems may employ one of several methods to demodulate a digitally modulated waveform.
  • Such methods include binary-phase-shift-keying (BPSK), quadrature-phase-shift-keying (QPSK), offset QPSK (OQPSK), m-ary phase-shift-keying (MPSK), or quadrature amplitude modulation (QAM).
  • BPSK binary-phase-shift-keying
  • QPSK quadrature-phase-shift-keying
  • OFQPSK offset QPSK
  • MPSK m-ary phase-shift-keying
  • QAM quadrature amplitude modulation
  • Periodic signals used in digital communications systems are often generated by a crystal oscillator having a special analog tuning circuit for adjusting the frequency of the oscillator in response to a high BER.
  • the accompanying analog tuning circuit is typically expensive and bulky.
  • Another accurate but expensive oscillator is the voltage controlled temperature compensated crystal oscillator.
  • relatively accurate periodic signals are generated with voltage controlled oscillators (VCOs) using one or more phase-locked loops (PLLs).
  • a PLL is a circuit that outputs a signal that is phase locked to an input signal. PLLs improve frequency accuracy and lower any phase noise of a periodic signal output from a VCO and extend the range of possible output frequencies.
  • the input signal to the PLL acts as a reference signal and is often provided by another PLL, a direct digital synthesizer (DDS), a voltage controlled oscillator or a numerically controlled oscillator (NCO).
  • DDS direct digital synthesizer
  • NCO numerically controlled oscillator
  • the output frequency is adjustable in steps.
  • the step size determines the frequency resolution of the PLL and is dependent on certain PLL parameters.
  • PLLs are often used to synthesize a range of periodic signals at precise frequencies from a single periodic signal.
  • a PLL driven by a conventional oscillator typically has numerous limitations.
  • the output of the PLL often contains significant spurious noise.
  • the range of allowable output frequencies is relatively limited due to poor frequency resolution and a PLL by itself is adjustable only in coarse frequency steps due to design limitations.
  • the additional PLL provides the input or reference signal to the primary PLL and improves control over the reference freqtiency. This results in an output periodic signal with greater frequency resolution and accuracy.
  • the second PLL represents additional hardware that occupies valuable circuit board space and consumes power.
  • the additional power consumption is particularly problematic in cellular telephony where the battery life of the mobile unit is an important consideration.
  • such systems often have slow switching times causing the output of the primary PLL to wander significantly between loop corrections.
  • a DDS is often employed in place of the second PLL, to provide the reference signal to the primary PLL.
  • a DDS typically improves the frequency resolution and switching speed of the PLL while improving PLL design flexibility.
  • a typical DDS driven PLL has also significant limitations.
  • a typical DDS employs a multi-bit digital-to-analog converter (DAC).
  • DAC digital-to-analog converter
  • multi-bit DACs have hardware limitations that result in glitches in signals output by circuits employing these devices. Glitches result when less than all of the bits in a DAC change simultaneously. Hence, the output waveform exhibits temporary false values as the bits change to their appropriate values.
  • the glitches cause spurious frequency tones, i.e., glitch noise, to appear at the DAC output very close to the desired output frequency. The spurious tones can degrade PLL performance.
  • the output of the DAC also includes quantization noise that is directly related to the DACs amplitude resolution. Amplitude resolution is determined by the number of bits used in the DAC computations. DACs with excellent amplitude resohition and frequency response tend to consume excess power and are expensive. In addition, spurious tones become more problematic as the frequency of the periodic signal increases, further limiting the range of allowable output frequencies.
  • the inventive system includes a low-bit digital-to-analog converter for converting a first signal at a reference frequency to a digital signal.
  • a delta-sigma converter is included for suppressing noise in the digital signal within a predetermined range of the reference frequency and providing a noise-shaped signal in response thereto.
  • the inventive system further includes a direct digital synthesizer for providing the first signal at the first frequency.
  • An oscillator produces an analog reference signal that is input to the direct digital synthesizer.
  • the direct digital synthesizer converts the oscillator output signal to the first signal.
  • the low-bit digital-to-analog converter is implemented as a delta-sigma digital-to-analog converter.
  • the delta-sigma digital-to-analog converter is a one-bit delta- sigma digital-to-analog converter and includes a delta-sigma modulator with an order greater than two.
  • the noise shaped signal is a digital signal and is filtered with a bandpass filter to remove any remaining undesirable signals such as quantization noise pushed out of band by the delta-sigma analog-to-digital converter.
  • the output of the delta-sigma digital-to-analog converter is input to a phase-locked loop.
  • the digital-to-analog converter is a glitch-free 1- bit digital-to-analog converter. Hence, the glitch noise associated with the use of a traditional multi-bit digital-to-analog converter is eliminated.
  • Use of a direct digital synthesizer provides for more complete control of the range of allowable frequencies for the noise shaped signal and, consequently, the frequency of the output periodic signal.
  • Fig. 1 is a block diagram of a signal generator comprising a direct digital synthesizer (DDS) driven phase-locked loop according to the prior art.
  • DDS direct digital synthesizer
  • Fig. 2 is a block diagram of a phase-locked loop synthesizer (PLL) using a delta-sigma ( ⁇ ) modulator and a 1-bit digital-to-analog converter (DAC) constructed in accordance with the teachings of the present invention.
  • Fig. 3 is a block diagram of the ⁇ modulator of Fig. 2.
  • Fig. 4 is a graph of a signal transfer function and a noise transfer function of the ⁇ modulator of Fig. 3.
  • Fig. 5 is a graph of the frequency spectrum of the periodic signal output from the 1-bit DAC of Fig. 2.
  • Fig. 1 is a block diagram of signal generator 40 according to the prior art.
  • the signal generator 40 has a DDS 42 that is driven by a reference oscillator 44.
  • the DDS 42 synthesizes a digital signal having a frequency dependent on the frequency of its input signal, i.e., the analog signal output from the reference oscillator 44, and its design parameters. Construction of the DDS 42 is well known in the art and described in U.S. Patent No. 4,965,533, entitled DIRECT DIGITAL SYNTHESIZER DRIVEN phase-locked loop FREQUENCY SYNTHESIZER, assigned to the assignee of the present invention and incorporated herein by reference.
  • the synthesized digital signal is converted to an analog signal via a multi-bit DAC 46.
  • the resulting analog signal is then filtered by a DDS filter 48 to remove undesirable signals such as noise and interpolate between samples to remove undesirable spectral images of the reconstructed waveform.
  • the resulting filtered signal is provided as a reference signal input to a PLL 50.
  • the PLL 50 is a feedback loop with a transfer function designed to generate an output signal having a frequency related to the frequency of the filtered reference signal received from the DDS filter 48.
  • the frequency of the PLL 50 output signal is a function of the parameters of the PLL 50 and the DDS 42.
  • the PLL 50 includes a phase detector implemented as a signal subtractor 78, a loop filter 80, a voltage controlled oscillator (VCO) 82, and a loop divider 84 having a divide ratio N.
  • the loop filter 80 filters undesirable signals from the output of the subtractor 78 and then outputs a control voltage 86 to the VCO 82 that then generates the output periodic signal 76 in response to the control voltage 86.
  • the output periodic signal 76 is fed back to the loop divider 84 that adjusts the frequency of the output periodic signal 76 in preparation for a comparison between the reference signal 74 and a divider output 88.
  • the comparison is performed by the subtractor 78 whose output is representative of the difference between the signals 74, 88 and, after filtering, results in the control voltage 86.
  • Fig. 2 is a block diagram of a signal generator 60 constructed in accordance with the teachings of the present invention.
  • the inventive signal generator 60 includes the reference oscillator 44 connected to the DDS
  • ⁇ modulator 62 followed by a ⁇ modulator 62, a 1-bit DAC 68, a bandpass filter 72, and the PLL 50, all connected in series in the order mentioned above.
  • the DDS 42 driven by the oscillator 44 outputs a synthesized digital periodic signal 64 to the ⁇ modulator 62.
  • the ⁇ modulator 62 acts as a noise-shaper that pushes quantization noise in the synthesized periodic signal 64 out of band, and suppresses quantization noise in band.
  • the periodic signal 64 is a digitized sine wave.
  • a resonator circuit the basic building block of the ⁇ modulator 62, is characterized by the following noise transfer function:
  • A(z) and B(z) are functions of z designed to suppress in-band quantization noise, i.e., push the noise out of band or away from the desired periodic signal frequency.
  • Those skilled in the art will appreciate that other functions may be used for A(z) and B(z) without departing from the scope of the present invention.
  • the signal transfer function of the basic building block is:
  • the ⁇ modulator 62 has three basic building blocks 90 cascaded together to produce a sixth order ⁇ modulator 62.
  • ⁇ modulator may be used without departing from the scope of the present invention.
  • the ⁇ modulator 62 outputs a noise shaped signal 66 to a 1-bit DAC 68.
  • the ⁇ modulator 62 in combination with the 1-bit DAC 68 is called a ⁇ DAC.
  • the 1-bit DAC 68 generates considerable quantization noise.
  • the quantization noise is suppressed in-band, i.e., near the desired periodic signal frequency. Since the 1-bit DAC 68 has only one bit, the glitch problems and resulting spurious noise resulting from the use of the multi-bit DAC 46 of Fig. 2 are avoided.
  • the analog output of the DAC 70 includes out-of-band quantization noise that is easily filtered out by a bandpass filter 72.
  • the bandpass filter 72 provides a precise reference periodic signal on line 74 to the PLL 50 which lacks spurious glitch noise.
  • the accurate reference signal allows the PLL 50 to generate accurate output periodic signals 76 over a range of frequencies by varying the PLL 50 parameters.
  • the PLL 50 includes a phase detector, i.e., signal subtractor 78, a loop filter 80, a voltage controlled oscillator (VCO) 82, and a loop divider 84 having a divide ratio N.
  • the PLL components 78, 80, 82, and 84 represent a feedback loop used to tune the frequency of the output periodic signal 76 to a specific synthesized frequency.
  • the loop filter 80 filters undesirable signals from the output of the subtractor 78 and then outputs a control voltage 86 to the VCO 82 that then generates the output periodic signal 76 in response to the control voltage 86.
  • the output periodic signal 76 is fed back to the loop divider 84 that adjusts the frequency of the output periodic signal 76 in preparation for a comparison between the reference signal 74 and a divider output 88.
  • the comparison is performed by the subtractor 78 whose output is representative of the difference between the signals 74, 88 and, after filtering, results in the control voltage 86.
  • F R is frequency of the reference signal 76
  • N R is a frequency control variable of the DDS 42
  • b is the number of bits used in the DDS 42.
  • the ⁇ modulator 62 and the 1-bit DAC 68 facilitates the generation of the highly accurate output periodic signal 76, lacking the spurious noise associated with expensive multi-bit DACs.
  • the spurious noise generated by the multi-bit DAC 46 of Fig. 1 does not limit the frequency of the reference signal 74.
  • the ⁇ modulator 62 and the 1-bit DAC 68 are relatively inexpensive in comparison to the multi-bit DAC 46 if Fig. 1.
  • the PLL 60 is a cost effective, highly accurate clock generation system having a relatively wide range of allowable output frequencies.
  • the 1-bit DAC 68 may be replaced by a low-bit DAC such as a 2 or 3-bit DAC without departing from the scope of the present invention.
  • Fig. 3 is a block diagram of the ⁇ modulator 62 of Fig. 2.
  • the ⁇ modulator 62 is a sixth order ⁇ modulator.
  • the ⁇ modulator 82 has three basic building blocks 90, also termed second order resonators, cascaded together.
  • Each basic building block 90 includes a combination of digital delays (z "1 ) 94, amplifiers 96 having voltage gains oq (where i is an integer index ranging from 0 to 5), an adder 98, and a subtractor 100.
  • the adder 98 receives as parallel inputs, outputs from the amplifiers 96.
  • One of the amplifiers 96 has an input provided by a digital delay 94 whose input is also the input of the other amplifier 96. This input is provided by a digital delay 94 in a subsequent resonator 90, or, in the case of the output basic block 90, provided by the noise-shaped output 66 of the ⁇ modulator 82.
  • the first basic building block 90 receives the noise shaped signal 66 as a third input to the adder 98. Subsequent building blocks 90 receive outputs of the previous basic building blocks 90 as third inputs to the adders 98.
  • the output of the adder 98 provides an input to the subtractor 100.
  • the output of the adder 98 is sent through a digital delay 94, providing the output of the resonator 90.
  • the output of the resonator 90 is sent through another digital delay 94 and provides a second input to the adder 98 forming a feedback loop.
  • Quantization noise is modeled as a linear noise element 92 and occurs before the noise shaped output 94.
  • the voltage gains of the amplifiers 96 are picked to provide a noise transfer function and signal transfer function that enable the ⁇ modulator
  • Fig. 4 is a graph 102 of a signal transfer function 104 and a noise transfer function 106 implemented by the ⁇ modulator 62 of Fig. 3.
  • the graph has an ordinate 108 representing 20*log(V), i.e., decibels (dB) and an abscissa 110 representing frequency.
  • the noise transfer function 106 significantly suppresses noise within a range of frequencies 112 (in-band) known as the operating region, while the signal transfer function 104 allows the signal to pass un-suppressed or even amplified.
  • the noise transfer function 106 and the signal transfer function 104 represent noise and signal gain profiles respectively.
  • Fig. 5 is a graph of a frequency spectrum 120 of the DAC output 70 of Fig. 2.
  • the graph has an ordinate 122 corresponding to signal power and an abscissa 124 corresponding to signal frequency.
  • the spectrum 120 includes quantization noise 126 on either side of a frequency spike 128 centered at a desired output frequency 130 of the DAC output 70 of Fig. 2.
  • the noise 126 is suppressed in-band, i.e., near the desired output frequency 130 and pushed out of band.
  • the bandpass filter 72 of Fig. 2 can then easily remove the noise 126, leaving the signal spike 128 at the desired output frequency 130. Signal energy will then be concentrated at the desired frequency 130, representing a periodic signal with excellent frequency accuracy.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

Selon un mode de réalisation caractéristique, le système selon l'invention concerne un dénumériseur à voie binaire étroite (68) permettant de convertir un premier signal généré à une fréquence de référence en un signal numérique. Un convertisseur delta-sigma supprime le bruit dans le signal numérique à l'intérieur d'une plage prédéterminée de fréquences de référence et génère en retour un signal en forme de bruit. Un filtre passe-bande (72 )filtre le bruit hors bande et génère un signal périodique précis sans déformation. Selon un mode de réalisation particulier, le système comporte un synthétiseur numérique direct (42) qui produit le premier signal à la première fréquence et le signal périodique précis de référence comme signal de référence pour la boucle à phase asservie (50).
EP99930808A 1998-06-30 1999-06-29 Systeme de production d'un signal periodique precis a faible bruit Withdrawn EP1095458A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10786898A 1998-06-30 1998-06-30
US107868 1998-06-30
PCT/US1999/014655 WO2000001072A1 (fr) 1998-06-30 1999-06-29 Systeme de production d'un signal periodique precis a faible bruit

Publications (1)

Publication Number Publication Date
EP1095458A1 true EP1095458A1 (fr) 2001-05-02

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EP99930808A Withdrawn EP1095458A1 (fr) 1998-06-30 1999-06-29 Systeme de production d'un signal periodique precis a faible bruit

Country Status (7)

Country Link
EP (1) EP1095458A1 (fr)
JP (1) JP2002519924A (fr)
CN (1) CN1308789A (fr)
AU (1) AU4726099A (fr)
BR (1) BR9911733A (fr)
CA (1) CA2336383A1 (fr)
WO (1) WO2000001072A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10019487A1 (de) * 2000-04-19 2001-11-08 Siemens Ag Frequenzsynthesizer
US7130327B2 (en) * 2003-06-27 2006-10-31 Northrop Grumman Corporation Digital frequency synthesis
US7482885B2 (en) * 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7782017B2 (en) * 2006-02-28 2010-08-24 Linear Technology Corporation Apparatus and method for producing signal conveying circuit status information
JP2010219756A (ja) * 2009-03-16 2010-09-30 Canon Inc 信号処理装置
JP2015128220A (ja) 2013-12-27 2015-07-09 セイコーエプソン株式会社 発振回路、発振器、電子機器、移動体及び発振器の周波数調整方法
US9397675B1 (en) * 2015-07-31 2016-07-19 Shure Acquisition Holdings, Inc. Hybrid frequency synthesizer and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965533A (en) * 1989-08-31 1990-10-23 Qualcomm, Inc. Direct digital synthesizer driven phase lock loop frequency synthesizer

Non-Patent Citations (1)

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Title
See references of WO0001072A1 *

Also Published As

Publication number Publication date
BR9911733A (pt) 2001-04-03
WO2000001072A1 (fr) 2000-01-06
JP2002519924A (ja) 2002-07-02
CA2336383A1 (fr) 2000-01-06
AU4726099A (en) 2000-01-17
CN1308789A (zh) 2001-08-15

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