MXPA01000175A - System for generating an accurate low-noise periodic signal - Google Patents

Abstract

In the illustrative embodiment, the inventive system includes a low-bit digital-to-analog converter (68) for converting a first signal at a reference frequency to a digital signal. A delta-sigma converter is included for suppressing noise in the digital signal within the predetermined range of the reference frequency and providing a noise-shaped signal in response thereto. A bandpass filter (72) filters out the out-of-band noise and provides an accurate periodic signal which lacks glitch noise. In a particular embodiment, the inventive system further includes a direct digital synthesizer (42) for providing the first signal at the first frequency and the accurate reference periodic signal is supplied as reference signal to a phase-locked loop (50).

Description

SYSTEM TO GENERATE AN EXACT PERIODIC SIGNAL OF LOW NOISE Field of the Invention The present invention relates to communication systems. Specifically, the present invention relates to systems and techniques for generating accurate periodic low noise signals for use in communication systems.

Antecedents of the Invention. Periodic electronic signals are used in a variety of demanding applications including reference oscillators, used to modulate and demodulate signals in analog circuits and clocks for digital circuits. Such applications often require very accurate low noise signals that consume a minimal amount of energy, while maintaining their accuracy over a range of frequencies. The accuracy of said signals is particularly important in digital communication systems, such as code division multiple access (CDMA) communication systems. In CDMA systems, signals within a certain range of frequencies must often be moved to a different range or frequency band. The accuracy of the clock signal affects the accuracy of the frequency translation. For example, in a CDMA cellular telephone network, a local oscillator (LO) in a mobile receiver provides a periodic signal that facilitates the translation of the input of the radio frequency (RF) signals to an intermediate frequency band ( IF). If the frequency of the local oscillator is not accurate, the translated signals can be moved outside the desired IF band. Digital communication systems can use one of several methods to demodulate a modulated waveform in digital form. Such methods include binary phase change switching (BPSK), quadrature phase shift switching (QPSK), QPSK compensation (OQPSK), m-ary phase change commutation (MPSK), or quadrature amplitude modulation (QAM). It is often necessary for the system to close to a received RF signal. The ability of the modulator to close the signal, and therefore its performance as indicated by the degradation in the measured bit error (BER) range, against the theoretical BER, is influenced by the phase noise of the signals of the clock generated.

Periodic signals used in digital communication systems are often generated by a crystal oscillator that has a special analog tuning circuit to adjust the frequency of the oscillator in response to a higher BER. The analog tuning circuit that accompanies it, is usually expensive and bulky. Another precise but costly oscillator is the compensated temperature glass oscillator and controlled volume. These oscillators, however, used by themselves, tend to have limited frequency ranges. This often limits the signal closure capacity of a mobile receiver. Alternatively, relatively accurate periodic signals are generated with controlled voltage oscillators (VCOs), using one or more phase locked circuits (PLLs). A PLL is a circuit that generates a signal that is hooked to the phase for an input signal. PLLs improve frequency accuracy and decrease any phase noise from a periodic signal that leaves a VCO, and extend the range of possible output frequencies. The input signal to the PLL acts as a reference signal and is often produced by another PLL, a direct digital synthesizer (DDS), a controlled voltage oscillator or a numerically controlled oscillator (NCO).

By changing the specific parameters of the PLL, such as the proportion of feedback division of the circuit, the output frequency is adjustable in steps. The size of the step determines the resolution of the frequency of the PLL, and depends on certain parameters of the PLL. Often, several different frequencies must be generated from a single periodic signal, to operate different local oscillators within a circuit. PLLs are often used to synthesize a range of periodic signals at precise frequencies, from a single periodic signal. However, a PLL operated through a conventional oscillator usually has numerous limitations. For example, the output of the PLL often contains significant undue noise. In addition, the range of the permissible output frequencies is relatively limited due to the poor frequency resolution and to a PLL that by itself is adjustable only in wide frequency steps due to design limitations. In order to reduce undue noise and increase frequency resolution, two PLLs are often used. The additional PLL provides the output or reference signal to the primary PLL and improves control over the reference frequency. This results in a periodic output signal with higher frequency resolution and accuracy. However, the second PLL represents the additional hardware that occupies a valuable space on the circuit board and consumes energy. The additional energy consumption is particularly problematic in cellular telephony, where the battery life of the mobile unit is an important consideration. In addition, such systems often have low switching times, causing the output of the primary PLL to deviate significantly between circuit corrections. To overcome the limitations associated with the use of two PLLs, a DDS is often used instead of the second PLL, to provide the reference signal for the primary PLL. Normally, a DDS improves the frequency resolution and the switching speed of the PLL, while improving the flexibility of the PLL design. However, a typical DDS that operates a PLL also has significant limitations. A typical DDS uses a digital to multi-bit analog converter (DAC). As is known in the art, multiple bit DACs have hardware limitations that result in small faults in signal output, through the circuits used by these devices. Small faults are the result of not simultaneously changing all the bits of a DAC. Hence, the output waveform exhibits temporary false values as the bits change to their appropriate values. Small faults cause undue frequency tones, for example, noise with small faults, which appear in the DAC output very close to the desired output frequency. Undue tones can degrade the performance of the PLL. The output of the DAC also includes the quantization noise that is directly related to the amplitude resolution of the DAC. The amplitude resolution is determined by the number of bits used in DAC computerizations. DACs with excellent amplitude resolution and frequency response tend to consume excessive energy, and are very expensive. In addition, undue tones become more problematic as the frequency of the periodic signal increases, also limiting the permissible range of output frequencies. Therefore, the need remains within the art of a system to produce very accurate periodic signals over a wide range of frequencies with minimal noise and fast switching speed.

Summary of the Invention. The need for art is focused on the system to generate an exact periodic signal of the present invention. In the illustrative embodiment, the system of the present invention includes a digital to low bit analog converter, for converting a first signal into a reference frequency in a digital signal. A delta-sigma converter is included to suppress the noise in the digital signal within a certain range of the reference frequency, and to provide in response thereto, an adjusted noise signal. In a particular embodiment, the system of the present invention additionally includes a direct digital synthesizer to provide the first signal at the first frequency. An oscillator produces an analog reference signal that is input to the direct digital synthesizer. The direct digital synthesizer converts the output signal of the oscillator into the first signal. The converter of digital to analog of low bits, is implemented in the form of a converter of digital to analog delta-sigma. In the preferred embodiment, the digital-to-analog delta-sigma converter is a digital-to-analog delta-sigma one-bit converter and includes a delta-sigma modulator with an order greater than two. The adjusted noise signal is a digital signal and is filtered with a bandpass filter to eliminate any remaining undesirable signals, such as the quantization noise extracted from the band through the analog-to-digital delta converter. sigma. The output of the converter from digital to analog delta-sigma is input to the circuit with phase lock. In the preferred embodiment, the digital-to-analog converter is a 1-bit analog to digital converter free of small faults. Therefore, noise with small faults associated with the use of a traditional digital to analog multi-bit converter is eliminated. The use of a direct digital synthesizer provides a more complete control of the range of permissible frequencies for the signal formed by noise and, therefore, the frequency of the periodic output signal.

Brief Description of the Drawings. Figure 1 is a block diagram of a signal generator comprising a direct digital synthesizer (DDS) operated by a phase locked circuit according to the prior art. Figure 2 is a block diagram of a phase locked circuit synthesizer (PLL) using a delta-sigma modulator (? S) and a 1-bit analog-to-digital converter (DAC), constructed in accordance with the teachings of the present invention. Figure 3 is a block diagram of the? Modulator of Figure 2. Figure 4 is a graph of a signal transfer function and a noise transfer function of the modulator? S of Figure 3. Figure 5 is a graph of the frequency spectrum of the output of the periodic signal from the 1-bit DAC of Figure 2.

Detailed Description of the Invention. Although the present invention is described with reference to illustrative embodiments for particular applications, it should be understood that the present invention is not limited thereto. Those skilled in the art having access to the teachings provided by the present invention will recognize modifications, applications and additional modalities within the scope thereof, as well as additional fields in which the present invention would be of significant utility. The following review of the operation of a PLL operated by a traditional DDS, is intended to facilitate the understanding of the present invention.

Figure 1 is a block diagram of the signal generator 40 according to the prior art. The signal generator 40 has a DDS 42 that is operated by a • reference oscillator 44. The DDS 42 synthesizes a digital signal 5 having a frequency that depends on the frequency of its input signal, for example, the output of the analog signal of the reference oscillator 44 and its design parameters. The construction of DDS 42 is well known in the art, and is described in the Patent North American No. 4,965,533 entitled FREQUENCY SYNTHESIZER circuit with phase latch OPERATED BY A DIRECT DIGITAL SYNTHETIZER, assigned to the assignee of the present invention and incorporated therein as reference. The synthesized digital signal is converted into an analog signal through a multi-bit DAC 46. Subsequently, the resulting analog signal is filtered through a DDS filter 48, to eliminate undesirable signals, such as noise and interpolated between the signals. samples, to eliminate undesirable images of the spectrum of the reconstructed waveform. The resulting filtered signal is produced in the form of a reference input signal to a PLL 50. The PLL 50 is a feedback loop with a transfer function designed to generate an output signal having a frequency related to the frequency of the filtered reference signal, received from the DDS filter 48. The frequency of the output signal of the PLL 50, is a function of the parameters of the PLL 50 and the DDS 42. The PLL 50 includes a phase detector implemented in the form of a signal subtracter 78, a filter of the circuit 80, a controlled voltage oscillator (VCO) 82 and a circuit divider 84 which it has a division N ratio. The PLL components 78, 80, 82, and 84 represent a feedback circuit used to tune the frequency of the periodic output signal 76 with a specific frequency synthesized. The filter of the circuit 80, filters the undesirable signals from the output of the subtracter 78, and subsequently, generates a control voltage 86 to the VCO 82 which, subsequently, generates the periodic output signal 76 in response to the control voltage 86. The signal Periodic output 76 is fed back to the circuit divider 84 which adjusts the frequency of the periodic output signal 76, in preparation for a comparison between the reference signal 74 and a divider output 88. The comparison is carried out by means of of the subtracter 78, whose output is representative of the difference between the signals 74, 88 and, after filtering, results in the control voltage 86. The DDS 42 provides an improved frequency resolution with respect to the previously designed PLLs, through the addition of additional design parameters provided by the DDS 42. However, as previously mentioned, the multi-bit DAC 46 is susceptible to small flaws and undue noise that is difficult to remove by filtration. The undue noise and quantization noise from the DAC 46 can corrupt the output of the PLL 50. Figure 2 is a block diagram of a signal generator 60 constructed in accordance with the teachings of the present invention. The signal generator 60 of the present invention includes the reference oscillator 44 connected to the DDS 42, followed by a modulator? S 62, a 1-bit DAC 68, a bandpass filter 72, and the PLL 50, all connected in series in the order mentioned above. The DDS 42 driven by the oscillator 44 generates a synthesized digital periodic signal 64 to the modulator? 62. The modulator? S 62, acts as a noise adjuster that pushes the quantization noise in the synthesized periodic signal 64 out of the band, and suppresses the band quantization noise. The periodic signal 64 is a digitized sine wave. As will be explained later in greater detail, a resonator circuit, the basic building block of the modulator? S 62, is characterized by the following noise transfer function: Y (z) / Q (z) = (1 + A (z) B (z)) [1] where z is a complex variable related to the signal frequency, Y (z) is the output of the z-field of the basic construction block, Q (z) is representative of the quantization noise, and A (z) and B ( z) are z functions designed to suppress band quantization noise, for example, pushing the noise out of band or away from the frequency of the desired periodic signal. In the present specific embodiment, A (z) = z_1 (l + z '2)' 1 and B (z) = -z "1. Those skilled in the art will appreciate that other functions can be used for A (z) and B (z) without departing from the scope of the present invention.The signal transfer function of the basic building block is: Y (z) / X (z) = A (z) (1 + A (z) B (z)) [2] where X (z) is the entry of the z-field of the basic construction block. As will be described below in more detail with respect to Figure 3, in the illustrative embodiment, the modulator? S 62 has three basic building blocks 90 placed together in cascade to produce a sixth order modulator? S. in the art, they will appreciate that a? modulator of different order can be used, without departing from the scope of the present invention. Returning now to Figure 2, the modulator? S 62 generates a signal formed by noise 66 to a 1-bit DAC 68. The modulator? S 62, in combination with the 1-bit DAC 68, is ca a DAC? S. As will be mentioned in more detail below, the DAC of a bit 68 generates a considerable quantization noise. The quantization noise is suppressed in band, for example, close to the frequency of the desired periodic signal. Since the DAC of a bit 68 has only one bit, problems with respect to small faults and undue noise resulting from the use of the multi-bit DAC 46 of Figure 2 are avoided. The analog output of the DAC 70 includes the out-band quantization noise, which is easily filtered outward by the bandpass filter 72. Therefore, the bandpass filter 72 produces a precise periodic reference signal on line 74 to PLL 50, the which lacks undue noise with small flaws. The exact reference signal allows the PLL 50 to generate exact periodic output signals 76, in a frequency range varying the PLL 50 parameters. According to FIG. 1, the PLL 50 includes a phase detector, for example, subtracter of signal 78, a filter of circuit 80, a contro voltage oscillator (VCO) 82, and a circuit divider 84 having a division N ratio. The PLL components 78, 80, 82, and 84 represent a feedback circuit used to tune the frequency of the periodic output signal 76 to a specific synthesized frequency. The filter of the circuit 80 filters the undesirable signals from the output of the subtracter 78 and subsequently generates a control voltage 86 to the VCO 82, which subsequently generates the periodic output signal 76 in response to the control voltage 86. The signal Periodic output 76 is fed back to the divider of the circuit 84 which adjusts the frequency of the periodic output signal 76, in the preparation of a comparison between the reference signal 74 and a divider output 88. The comparison is carried out at through the subtracter 78, whose output is representative of the difference between the signals 74, 88 and, after filtering, results in the control voltage 86. In the North American patent application series number 08 / 893,267 filed on July 8 of 1997, entitled CIRCUIT WITH PHASE COUPLING WITH NOISE ADJUSTER, assigned to the assignee of the present invention and incorporated therein as reference, a description is provided. alternative ion of a circuit with phase coupling. The frequency of the periodic output signal Fvco is related to the reference frequency by the following relationship: = FR * NR / (2b) [3] wherein FR is the frequency of the reference signal 76, NR is a variable frequency control of the DDS 42, and b is the number of bits used in the DDS 42. Therefore, the accuracy of the frequency FR of the signal of reference 74, directly affects the accuracy of the Fvco frequency of the output signal 76. The use of the modulator? S 62 and the 1-bit DAC 68, facilitates the generation of the periodic signal output with superior accuracy 76, which lacks the undue noise associated with expensive multi-bit DACs. Furthermore, the undue noise generated by the multi-bit DAC 46 of Figure 1 does not limit the frequency of the reference signal 74. In addition, the modulator? S 62 and the 1-bit DAC 68 are relatively inexpensive in comparison with the multiple bit DAC 46 of Figure 1. Hence,, the PLL 60 is a clock generation system with superior accuracy, cost effective that has a relatively wide range of permissible output frequency. Those skilled in the art will appreciate that the 1-bit DAC 68 can be replaced by a low bit DAC, such as a 2 or 3 bit DAC, without departing from the scope of the present invention. Figure 3 is a block diagram of the modulator? S 62 of Figure 2. The modulator? S 62 is a sixth order modulator. The modulator? S 82 has three basic building blocks 90, also called second-order resonators, installed in cascade as a whole. Each basic building block 90 includes a combination of digital delays (z "1) 94, amplifiers 96 having voltage gains OI-L (where i is an integer index in the range of 0 to 5), an adder 98 and a subtracter 100. The adder 98 receives the outputs from the amplifier 96 in the form of parallel inputs.An amplifier 96 has an input provided by a digital delay 94, whose input is also the input of the other amplifier 96. This input is provided by a digital delay 94 in a subsequent resonator 90, or, in the case of the basic output block 90, provided by the output with the set noise 66 of the modulator? S 82. The first basic construction block 90, receives the signal with set noise 66 in the form of a third input to adder 98. Subsequent building blocks 90, receive the outputs of the previous basic building blocks 90 in the form of third inputs to the adders 98. Those skilled in the art will appreciate that methods for building the basic building blocks 90, which can be implemented, are well known in the art and methods can be implemented, through the use of any signal processing hardware. digital The output of the adder 98, provides an input to the subtracter 100. The output of the adder 98 is sent through a digital delay 94, providing the output of the resonator 90. The output of the resonator 90 is sent through another digital delay 94 and it provides a second input to the adder 98, forming a feedback loop.

The quantization noise is designed in the form of a linear noise element 92 and occurs before the adjusted noise output 94. The voltage gains of the amplifiers 96, are collected to provide a noise transfer function and a function of signal transfer that makes it possible for the? 82 modulator to meet the stability and noise formation requirements for a particular application. The methods for collecting the gains a for the amplifiers 96 are well known in the art. In the specific embodiment of the present invention, the gains are: ao = 0, oi? = 3/2, a2 = 0, a3 = -3/4, a4 = 0, OI5 = 1/8. Figure 4 is a graph 102 of a signal transfer function 104 and a noise transfer function 106, implemented by the modulator? S 62 of the Figure 3. The graph has an ordinate 108 representing 20 * log (V), for example, decibels (dB) and an abscissa 110 representing the frequency. The noise transfer function 106, significantly suppresses noise within a frequency range 112 (in band), known as the operating region, while the signal transfer function 104 allows the signal to pass without being suppressed or even amplified. The noise transfer function 106 and the signal transfer function 104, represent the noise and signal gain profiles, respectively. Figure 5 is a graph of a frequency spectrum 120 of the DAC output 70 of Figure 2. The graph has an ordinate 122 corresponding to the signal energy and an abscissa 124 corresponding to the signal frequency. The spectrum 120 includes the quantization noise 126 on either side of a frequency peak 128 centered at a desired output frequency 130 of the DAC output 70 of Figure 2. The noise 126 is suppressed in band, for example, close to the desired output frequency 130 and sent out of band. The bandpass filter 72 of FIG. 2 can subsequently eliminate the noise 126 in an easy manner, leaving the signal peak 128 at the desired output frequency 130. Subsequently, the energy of the signal will be concentrated at the desired frequency. 130, representing a periodic signal with excellent frequency accuracy. Although the present invention has been described with reference to a particular embodiment for a particular application. Those skilled in the art who have access to the teachings of the present invention will recognize modifications, applications and additional modalities within the scope thereof.

Therefore, it is intended that the appended claims cover any and all of said applications, modifications and embodiments that are within the scope of the present invention.

Claims (31)

CLAIMS Having described the present invention, it is considered as a novelty, and therefore, the content of the following CLAIMS is claimed as property:

1. - A system for generating an exact periodic signal at a predetermined frequency, which comprises: a digital converter to low bit analog to convert a first signal at a reference frequency to a digital signal; and delta-sigma means to suppress the noise in said digital signal, within a predetermined range of said reference frequency and to produce a signal with noise adjusted in response thereto.

2. - The invention as described in claim 1, further characterized in that it includes a direct digital synthesizer to produce said first signal at said reference frequency.

3. - The invention as described in claim 2, further characterized in that it additionally includes a reference oscillator to provide an input to said direct digital synthesizer.

4 The invention as described in Claim 1, further characterized in that said converter from digital to analog of low bits, is a converter from digital to analog delta-sigma.

5. - The invention as described in claim 4, further characterized in that said digital-to-analog converter delta-sigma operates with less than four bits.

6 The invention as described in Claim 5, further characterized in that said digital-to-analog converter delta-sigma is a digital-to-analog converter delta-sigma of one bit.

7 The invention as described in Claim 4, further characterized in that said digital-to-analog converter delta-sigma includes a delta-sigma modulator with an order greater than two.

8. - The invention as described in claim 1, further characterized in that it additionally includes synthesizing means for generating a periodic output signal from said signal with adjusted noise.

9. - The invention as described in Claim 1, further characterized in that said synthesizing means is a circuit with phase locking.

10. - A system for generating a periodic signal of low noise, which comprises: digital means for generating a digital signal having a first central frequency; filter means for adjusting the noise, said digital signal suppressing the noise around said central frequency and producing a digital output signal in response thereto; converter means, for converting said digital output signal into an analogous signal; and circuit means for tuning said analog signal at a predetermined frequency and producing said periodic low-noise signal in response thereto.

The invention as described in Claim 10, further characterized in that said digital media includes a direct digital synthesizer.

12. The invention as described in Claim 11, further characterized in that said digital means additionally includes an oscillator to produce an input to said direct digital synthesizer.

13 The invention as described in Claim 12, further characterized in that said oscillator is a controlled voltage oscillator.

14. - The invention as described in Claim 10, further characterized in that said converter means is a digital to analogous delta-sigma converter.

15. The invention as described in Claim 10, further characterized in that said digital-to-analog converter delta-sigma operates with less than four bits.

16 The invention as described in Claim 15, further characterized in that said digital-to-analog converter delta-sigma is a digital-to-analog converter delta-sigma of one bit.

17. The invention as described in Claim 10, further characterized in that said filter means include a delta-sigma modulator.

18 The invention as described in Claim 17, further characterized in that said delta-sigma modulator includes a delta-sigma modulator circuit characterized by the following signal transfer function: Y (z) / Q (z) = (1 + A (z) B (z) r1 where Y (z) represents an output signal of said delta-sigma modulator circuit in the z-field, Q (z) represents the quantization noise in the z-field, and A (z) and B (z) are functions of z, designed to suppress band quantization noise.

19. The invention as described in Claim 18, characterized further because B (z) =

20. - The invention as described in Claim 18, further characterized in that A (z (1 + z-2) "1.

The invention as described in Claim 18, further characterized in that said delta-sigma modulator is characterized by the following noise transfer function: Y (z) / X (z) = A (z) (1 + A (z) B (z)) _1 in where X (z) represents an input signal of said delta-sigma modulator circuit in the z-field.

22. - The invention as described in Claim 17, further characterized in that said delta-sigma modulator has an order greater than two.

23. The invention as described in Claim 22, further characterized in that said delta-sigma modulator is a delta-sigma modulator of sixth order.

The invention as described in Claim 23, further characterized in that said delta-sigma modulator includes an amplifier with a gain of about 3/2.

The invention as described in Claim 23, further characterized in that said delta-sigma modulator includes an amplifier with a gain of about -3/4.

26. The invention as described in Claim 23, further characterized in that said delta-sigma modulator includes an amplifier with a gain of about 1/8.

27. The invention as described in Claim 10, further characterized in that said circuit means includes a circuit with phase lock.

28. - A system for synthesizing periodic signals in any of a plurality of frequencies, wherein said system comprises; an oscillator to generate a signal of a first frequency; a direct digital synthesizer to convert said signal into a digital signal; a delta-sigma modulator connected to receive the output of said direct digital synthesizer in the form of an input to it; a converter from digital to analog of low bits to convert an output of said delta-sigma modulator into an analogous signal; a filter to reduce the noise in said analog signal and to provide a clean reference signal in response thereto; and a phase locked circuit having said reference signal in the form of an input to generate said one of a plurality of frequencies.

29. - A system for generating a periodic signal having a specific frequency, wherein said system comprises: an oscillator for generating a reference signal having a frequency within a specific frequency band; noise adjusting means for suppressing noise within said frequency band in said oscillator signal, and for producing a noise signal adjusted in response thereto; converter means for converting said signal formed by noise to an analogous signal having low noise at a predetermined frequency; and phase locked circuit means for generating said periodic signal based on said analogous signal.

30. - A system for generating a periodic signal having a specific frequency, wherein said method comprises: a direct digital synthesizer; a sigma-delta digital-to-analog converter connected to receive the output of said synthesizer in the form of an input to it; and a phase locked circuit connected to the output of said digital to analog sigma-delta converter.

31. - A method for generating an exact periodic signal at a predetermined frequency, which includes the steps of: generating a digital periodic signal having a component at a desired reference frequency; suppressing the noise in said periodic signal within a predetermined range of said desired reference frequency, and providing a noise signal adjusted in response thereto; and synthesizing a periodic signal at said specific frequency based on said adjusted noise signal.