EP1081705A2 - Détecteur de synchronisation assisté par phase - Google Patents

Détecteur de synchronisation assisté par phase Download PDF

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Publication number
EP1081705A2
EP1081705A2 EP00118360A EP00118360A EP1081705A2 EP 1081705 A2 EP1081705 A2 EP 1081705A2 EP 00118360 A EP00118360 A EP 00118360A EP 00118360 A EP00118360 A EP 00118360A EP 1081705 A2 EP1081705 A2 EP 1081705A2
Authority
EP
European Patent Office
Prior art keywords
preamble
phase
mod
detector
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00118360A
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German (de)
English (en)
Other versions
EP1081705A3 (fr
EP1081705B1 (fr
Inventor
Jonathan Ashley
Isaiah Carew
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Marvell International Ltd
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Infineon Technologies North America Corp
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Publication date
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Publication of EP1081705A2 publication Critical patent/EP1081705A2/fr
Publication of EP1081705A3 publication Critical patent/EP1081705A3/fr
Application granted granted Critical
Publication of EP1081705B1 publication Critical patent/EP1081705B1/fr
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Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/22—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing distortions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
    • G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
    • G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G11B5/09—Digital recording
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/20—Disc-shaped record carriers

Definitions

  • the present invention relates to magnetic recording and, particularly, to an improved synchronization detector.
  • Sampled amplitude detectors used in magnetic recording require timing recovery in order to correctly extract the digital sequence.
  • data sectors 100 on magnetic disks are formatted to include an acquisition preamble 102, a sync or synchronization mark 104, and user data 106.
  • Timing recovery uses the acquisition preamble 102 to acquire the correct sampling frequency and phase before reading the user data 106.
  • the synchronization mark 104 demarcates the beginning of the user data.
  • the preamble 102 is written using the periodic non-return-to-zero (NRZ) sequence 001100110011...which causes the pattern of magnetization SSNNSSNNSSNN ...to be written on the magnetic medium.
  • the pattern is periodic, having period 4T , where T is the bit period.
  • the pattern is sometimes called a 2T pattern because the interval between successive magnetic field direction transitions is 2T .
  • the sequence of samples [ x i , x i+1 , ..], produced by the preamble is also of period 4T .
  • PR4 partial response
  • the sequence is ideally [1, 1, -1, -1, 1, 1, -1, -1, 1, 1,...,].
  • EPR4 extended partial response
  • E n PR4 it is the convolution [1, 1] n * [1, 1, -1, -1, 1, 1, -1, -1, 1, 1,,...].
  • the preamble 102, the sync mark 104, and the user data 106 are read in succession. Reading the preamble 102 establishes bit synchronization. Reading the sync mark 104 establishes the absolute bit index of the first bit of the user data 106. Once bit synchronization is established, the sync mark 104 is searched for beginning at each possible bit index (i.e., at each possible start value in the sequence) within a predetermined qualification window, the onset and time-out of which are a priori parameters.
  • this search is done by calculating a distance metric between the ideal sequence of signal samples [ s 0 , s 1 ,..., s L-1 ] expected at the synchronization mark 104 and each block of received samples [ x i , x i+1 , ..., x i+L-1 ], where the index i runs through all the bit indices in the qualification window.
  • the first index i for which the metric does not exceed a qualification threshold is asserted to be the location of the synchronization mark 104.
  • the prior art suffers from disadvantages in that a period T clock is required to clock the synchronization detector. In addition, a relatively long synchronization mark is required.
  • a synchronization detector uses the periodicity of the preamble to limit the search for the synchronization mark.
  • the search is limited to one bit phase in each block of four (4) bits.
  • the search is limited to one bit phase per block of two (2) bits.
  • the synchronization mark is written beginning at a known, fixed phase of the periodic preamble pattern.
  • the signal phase estimate obtained in the course of reading the preamble is used to limit the search for the synchronization marks to the bit positions whose phase matches the estimate of the fixed, known phase.
  • a synchronization detector includes a phase detector and a distance metric calculator.
  • the phase detector uses the preamble readback signal to estimate the bit periods and outputs a signal indicative of this estimate. This signal is used by the distance metric calculator to limit its search for the synchronization mark to every m th bit position, where m is a predetermined integer greater than one (1).
  • the present invention allows the synchronization detector to operate on a period mT clock.
  • the synchronization detector may use a lower speed, less expensive clock.
  • FIGS. 2- 6 illustrate an improved synchronization detector according to an implementation of the present invention.
  • the synchronization detector according to an embodiment of the invention uses phase information from the immediately preceding preamble to restrict the search for the synchronization mark to a particular bit phase.
  • FIG. 2 a block diagram of a sampled amplitude read channel according to an embodiment of the invention is shown and identified by the reference numeral 200.
  • data are written onto the media.
  • the data are encoded in an encoder 202, such as an RLL or other encoder.
  • a precoder 204 precodes the sequence to compensate for the transfer function of the magnetic recording channel 208 and equalizing filters.
  • the write circuitry 206 modulates the current in the recording head coil to record a binary sequence onto the medium.
  • a reference frequency f ref provides a write clock to the write circuitry 206.
  • the bit sequence is then provided to a variable gain amplifier 210 to adjust the amplitude of the signal.
  • DC offset control 212 and loop filter/gain error correction 214 may be provided to control the adjustment of the VGA 210.
  • an asymmetry control unit 215 including an asymmetry adjustment unit 216 and asymmetry control 218 may be provided to compensate for magneto-resistive asymmetry effects.
  • the signal is then provided to a continuous time filter 220, which may be a Butterworth filter, for example, to attenuate high frequency noise and minimize aliasing into baseband after sampling.
  • the signal is then provided to an analog to digital converter 222 to sample the output of the continuous time filter 220.
  • a finite impulse response filter 224 provides additional equalization of the signal to the desired response.
  • the output of the FIR 224 is provided to an interpolated timing recovery unit 228 which is used to recover the discrete time sequence.
  • the output of the interpolated timing recovery unit is used to provide a feedback control to the DC offset control 212, the gain error 214, the asymmetry control 218 and the FIR 224 control 226.
  • the output of the interpolated timing recovery 228 is provided to a Viterbi detector 232 to provide maximum likelihood detection.
  • the ITR output is provided to a sync detector 234 according to the present invention. As will be described in greater detail below, the sync detector 234 detects the sync mark using phase information gleaned from having read the immediately preceding preamble. This information is then provided to the Viterbi detector 232 for use in sequence detection.
  • the Viterbi detector output is then provided to the decoder 236 which decodes the encoding provided by the encoder 202.
  • the sync mark detector After acquiring the preamble, the sync mark detector searches for the sync mark which marks the beginning of the data field. When the sync mark is detected, the sync mark detector enables the Viterbi detector 232 and decoder 236.
  • an exemplary synchronization detector 234 has two primary components: a modulo 4 phase detector 250 and a distance metric calculator 252.
  • the modulo 4 phase detector 250 and the distance metric calculator 252 receive as inputs the equalized signal.
  • the modulo 4 phase detector 250 uses the preamble readback signal to estimate the phase modulo 4 bit periods.
  • the period 4 modulo 4 phase detector 250 outputs a signal indicating this estimate to enable the distance metric calculator 252. This signal is used by the distance metric calculator 252 to limit its search for the synchronization mark to every m -th bit position, where m is either 2 or 4.
  • the phase detector 250 accumulates phase information during a phase accumulation window. This window is timed to be near the end of the preamble and is typically 20 bits in length.
  • the index i is restricted to the phase accumulation window.
  • each of the two accumulators can operate on a half-speed clock. In effect, a correlation is performed between the the preamble and a pair of preamble signals, delayed from one another.
  • phase detector PR4 [x i0,..., x i0+3 ] C 0 C 1
  • Comparison result Phase estimate [1,1,-1,-1] L L (C 0 ⁇ 0) and (C 1 ⁇ 0) 0 [1,-1,-1,1] L -L (C 0 ⁇ 0) and (C 1 ⁇ 0) 1 [-1,-1,1,1] -L -L (C 0 ⁇ 0) and (C 1 ⁇ 0) 2 [-1,1,1,-1] -L L (C 0 ⁇ 0) and (C 1 ⁇ 0) 3
  • Table 1 shows the expected values of c 0 and c 1 after reading the samples in the phase accumulator window in the case of PR4 equalized data.
  • L is a positive number whose exact value depends on the width of the accumulator window and the gain of the signal. The comparisons of c 0 and c 1 , with zero determine the corresponding phase estimate given in the last column.
  • Phase detector EPR4 [x i0,..., x i0+3 ] c 0 c 1 Comparison result Phase estimate [2, 0, -2, 0] 2L 0 (C 0 ⁇ C 1 ) and (C 0 ⁇ - C 1 ) 0 [0, -2, 0, 2] 0 -2L (C 0 ⁇ C 1 ) and (C 0 ⁇ - C 1 ) 1 [-2, 0, 2, 0] -2L 0 (C 0 ⁇ C 1 ) and (C 0 ⁇ -C 1 ) 2 [0, 2, 0, -2] 0 2L (C 0 ⁇ C 1 ) and (C 0 ⁇ -C 1 ) 3
  • the phase estimate made by the phase detector is communicated to the distance metric calculator via a phase estimate signal. More particularly, FIG. 4A shows the phase estimate signals corresponding to the four phases, in one embodiment.
  • the phase estimate signal is high at each bit index at a fixed phase modulo four bit periods.
  • the distance metric calculator calculates the distance between the received sample sequence [ x I , x I+1 , ..., x I+L-1 ] and the ideal sample sequence [ s 0 , s 1 , ..., s L-1 ] expected at the synchronization mark.
  • the first index i (in the qualification window) at which this distance does not exceed a qualification threshold is asserted to be the location of the synchronization mark.
  • the NRZ version of the sync mark is seven bits in length and follows the preamble as...1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0. This results in the EPR4 equalized sequence [...0 2 0 -2 0 2 0 -2 -1 0 1 2 1 -1 -2].
  • FIG. 4B depicts the EPR4 equalized signal, the corresponding phase signal, and the corresponding phase estimate signal. In this example, the phase estimate signal is high during bit periods at phase 3.
  • the distance metric calculator calculates metrics for those data sequences [x i , x i+1 ,...,x i+6 ] where i has phase 3. More generally, for each index i at a fixed offset from a rising edge of the phase offset signal, the distance metric calculator 252 calculates the squared Euclidean distance between the sample-by-sample slicer estimates of the received sample sequence and the ideal sample sequence [ s 0 , s 1 ,...,s L-1 ] expected at the synchronization mark. The first index i (in the qualification window) at which this metric does not exceed a qualification threshold is asserted to be the location of the synchronization mark.
  • the symbols of the data sequence and the expected data sequence are EPR4 symbols of the set ⁇ -2, -1, 0, 1, 2, ⁇ .
  • the symbols of the squared distance sequence are of the set ⁇ 0, 1, 4, 9, 16 ⁇ .
  • One embodiment of the invention uses a look up table to produce the symbols of the squared distance sequence and uses an adder to sum these symbols to produce the total squared distance.
  • FIG. 5 shows the squared Euclidean distance between the synchronization mark and shifts of the synchronization mark into the preamble by multiples of four bits for the example discussed above. Assuming the phase estimator correctly estimates the phase of the preamble, these are the shifts at which the distance metric calculator computes the squared distance between the sequence of seven (7) slicer estimates of the signal and the sequence of seven (7) samples expected at the synchronization mark.
  • the period-two implementation of the distance metric calculator according to the present invention is appropriate when the relative polarity of the write and read signals is unknown.
  • the period-two version determines the polarity as a by-product of determining the location of the synchronization mark.
  • the NRZ version of the synchronization mark is fourteen bits in length, and follows the preamble pattern as ...11001100 00111000001111 . This results in the EPR4 equalized sequence [...,0,2,0,-2,0,2,0,-2,-1,0,1,2,1,-1,-2,-1,0,0,1,2,1,0].
  • FIG. 6 shows the squared Euclidean distance between the synchronization mark and shifts of the synchronization mark into the preamble by multiples of two bits.
  • the shift is by an odd multiple of two, the polarity of the expected synchronization mark is flipped.
  • the phase estimator correctly estimates the phase of the preamble, these are the shifts at which the distance metric calculator computes the squared distance between the sequence of fourteen (14) slicer estimates of the signal and the sequence of fourteen (14) samples expected at the synchronization mark.
  • the minimum squared distance between the synchronization mark and any of its (polarity adjusted) shifts into the preamble is 37. If the qualification threshold to 9 (meaning that synchronization is determined to exist at the first time the metric does not exceed 9), then the minimum noise squared-amplitude that could cause early synchronization would be at least ( 37 - ⁇ 9) 2 > 9
EP00118360A 1999-09-03 2000-08-24 Détecteur de synchronisation assisté par phase Expired - Lifetime EP1081705B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15239099P 1999-09-03 1999-09-03
US152390 1999-09-03
US435333 1999-11-05
US09/435,333 US6657802B1 (en) 1999-04-16 1999-11-05 Phase assisted synchronization detector

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EP1081705A2 true EP1081705A2 (fr) 2001-03-07
EP1081705A3 EP1081705A3 (fr) 2004-06-23
EP1081705B1 EP1081705B1 (fr) 2011-07-20

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SG (1) SG92737A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270481A (zh) * 2010-05-28 2011-12-07 Lsi公司 基于极限距离度量的位置检测同步标记的方法与装置

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6961397B2 (en) * 2001-07-12 2005-11-01 Lucent Technologies Inc. Symbol synchronizer for impulse noise channels
US6912099B2 (en) * 2003-05-13 2005-06-28 Agere Systems Inc. Maximum likelihood detection of asynchronous servo data employing interpolation
US7307807B1 (en) * 2003-09-23 2007-12-11 Marvell International Ltd. Disk servo pattern writing
US7180693B2 (en) * 2004-04-14 2007-02-20 Agere Systems Inc. Method and apparatus for maximum likelihood detection of data employing interpolation with compensation of signal asymmetry
US7561649B2 (en) * 2004-04-30 2009-07-14 Agere Systems Inc. Method and apparatus for synchronization mark detection with DC compensation
US7403351B1 (en) * 2004-05-14 2008-07-22 Marvell International, Ltd. Sequence-permutation control information detection and signal polarity determination
US7158338B2 (en) * 2004-05-24 2007-01-02 Quantum Corporation Servo track having periodic frames of tone field and embedded synchronization marks
US7583459B1 (en) 2004-11-18 2009-09-01 Marvell International Ltd. Method and apparatus for write precompensation in a magnetic recording system
US7193801B2 (en) * 2004-11-18 2007-03-20 Agere Systems, Inc. Method and apparatus for testing a servo circuit of a read/write head system
US7167328B2 (en) * 2004-12-17 2007-01-23 Agere Systems Inc. Synchronizing an asynchronously detected servo signal to synchronous servo demodulation
US7230783B2 (en) * 2005-06-16 2007-06-12 International Business Machines Corporation Mitigation of MR read head distortion
US7362525B2 (en) * 2005-07-22 2008-04-22 Quantum Corporation PRML based magnetic servo position demodulator
US7428118B2 (en) * 2005-11-28 2008-09-23 Quantum Corporation LTM compensation methods and systems for magnetic servo writing
US7738200B2 (en) * 2006-05-01 2010-06-15 Agere Systems Inc. Systems and methods for estimating time corresponding to peak signal amplitude
US7974034B1 (en) * 2006-06-07 2011-07-05 Marvell International Ltd. Systems and methods for sync mark detection using correlation
US8358566B1 (en) 2006-07-13 2013-01-22 Marvell International Ltd. Method and device for detecting a sync mark
US8264933B1 (en) 2007-07-09 2012-09-11 Marvell International Ltd. Timing loop with large pull-in range
US8254049B2 (en) * 2007-08-20 2012-08-28 Agere Systems Inc. Systems and methods for improved synchronization between an asynchronously detected signal and a synchronous operation
US8054931B2 (en) 2007-08-20 2011-11-08 Agere Systems Inc. Systems and methods for improved timing recovery
US8174784B2 (en) * 2007-10-30 2012-05-08 Agere Systems Inc. Systems and methods for inter-location control of storage access
US8154818B2 (en) 2007-12-14 2012-04-10 Lsi Corporation Systems and methods for adaptive CBD estimation in a storage device
JP5216100B2 (ja) * 2007-12-14 2013-06-19 エルエスアイ コーポレーション サーボアドレスマークデータを用いたフライングハイト制御のためのシステム及び方法
WO2009079093A1 (fr) 2007-12-14 2009-06-25 Lsi Corporation Système et procédé de réglage de la hauteur de survol à l'aide de données d'asservissement
US7768437B2 (en) * 2008-04-29 2010-08-03 Agere Systems Inc. Systems and methods for reducing the effects of ADC mismatch
US7813065B2 (en) * 2008-04-29 2010-10-12 Agere Systems Inc. Systems and methods for acquiring modified rate burst demodulation in servo systems
US8300342B2 (en) * 2008-04-30 2012-10-30 HGST Netherlands B.V. Multi-bit phase alignment for synchronization mark pattern matching
US7929237B2 (en) * 2008-06-27 2011-04-19 Agere Systems Inc. Modulated disk lock clock and methods for using such
CN101821808B (zh) 2008-07-28 2014-03-19 艾格瑞系统有限公司 用于确定头组件与存储介质之间的飞行高度的系统和方法
US8705673B2 (en) 2008-09-05 2014-04-22 Lsi Corporation Timing phase detection using a matched filter set
US8976913B2 (en) 2008-09-17 2015-03-10 Lsi Corporation Adaptive pattern dependent noise prediction on a feed forward noise estimate
US8243381B2 (en) 2008-11-13 2012-08-14 Agere Systems Inc. Systems and methods for sector address mark detection
US9305581B2 (en) 2008-12-04 2016-04-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for memory efficient repeatable run out processing
US8154972B2 (en) 2009-06-24 2012-04-10 Lsi Corporation Systems and methods for hard disk drive data storage including reduced latency loop recovery
US8174949B2 (en) * 2009-07-02 2012-05-08 Lsi Corporation Systems and methods for format efficient timing recovery in a read channel
CN101964654A (zh) 2009-07-22 2011-02-02 Lsi公司 用于高阶非对称性校正的系统和方法
US8456775B2 (en) * 2009-12-31 2013-06-04 Lsi Corporation Systems and methods for detecting a reference pattern
US8576969B1 (en) * 2010-06-16 2013-11-05 Marvell International Ltd. Method and apparatus for detecting sync mark
US8566381B2 (en) 2010-08-05 2013-10-22 Lsi Corporation Systems and methods for sequence detection in data processing
US8237597B2 (en) 2010-09-21 2012-08-07 Lsi Corporation Systems and methods for semi-independent loop processing
US8566378B2 (en) 2010-09-30 2013-10-22 Lsi Corporation Systems and methods for retry sync mark detection
US8614858B2 (en) * 2010-11-15 2013-12-24 Lsi Corporation Systems and methods for sync mark detection metric computation
US20120124241A1 (en) * 2010-11-15 2012-05-17 Lsi Corporation Systems and Methods for Sync Mark Detection
US8498072B2 (en) 2010-11-29 2013-07-30 Lsi Corporation Systems and methods for spiral waveform detection
US8526131B2 (en) 2010-11-29 2013-09-03 Lsi Corporation Systems and methods for signal polarity determination
US8411385B2 (en) 2010-12-20 2013-04-02 Lsi Corporation Systems and methods for improved timing recovery
US8325433B2 (en) 2011-01-19 2012-12-04 Lsi Corporation Systems and methods for reduced format data processing
US8261171B2 (en) 2011-01-27 2012-09-04 Lsi Corporation Systems and methods for diversity combined data detection
US8930344B2 (en) * 2011-02-04 2015-01-06 Hewlett-Packard Development Company, L.P. Systems and methods for holding a query
US8749908B2 (en) * 2011-03-17 2014-06-10 Lsi Corporation Systems and methods for sync mark detection
US8565047B2 (en) 2011-04-28 2013-10-22 Lsi Corporation Systems and methods for data write loopback based timing control
US8665544B2 (en) 2011-05-03 2014-03-04 Lsi Corporation Systems and methods for servo data detection
US8874410B2 (en) 2011-05-23 2014-10-28 Lsi Corporation Systems and methods for pattern detection
US8498071B2 (en) 2011-06-30 2013-07-30 Lsi Corporation Systems and methods for inter-track alignment
US8669891B2 (en) 2011-07-19 2014-03-11 Lsi Corporation Systems and methods for ADC based timing and gain control
US8780476B2 (en) 2011-09-23 2014-07-15 Lsi Corporation Systems and methods for controlled wedge spacing in a storage device
US8773811B2 (en) 2011-12-12 2014-07-08 Lsi Corporation Systems and methods for zone servo timing gain recovery
US8681444B2 (en) 2012-06-07 2014-03-25 Lsi Corporation Multi-zone servo processor
US8625216B2 (en) 2012-06-07 2014-01-07 Lsi Corporation Servo zone detector
US8564897B1 (en) 2012-06-21 2013-10-22 Lsi Corporation Systems and methods for enhanced sync mark detection
US9019641B2 (en) * 2012-12-13 2015-04-28 Lsi Corporation Systems and methods for adaptive threshold pattern detection
US9053217B2 (en) 2013-02-17 2015-06-09 Lsi Corporation Ratio-adjustable sync mark detection system
US9196297B2 (en) 2013-03-14 2015-11-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for enhanced sync mark mis-detection protection
US9275655B2 (en) 2013-06-11 2016-03-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Timing error detector with diversity loop detector decision feedback
US10152999B2 (en) 2013-07-03 2018-12-11 Avago Technologies International Sales Pte. Limited Systems and methods for correlation based data alignment
US9129650B2 (en) 2013-07-25 2015-09-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Array-reader based magnetic recording systems with frequency division multiplexing
US9129646B2 (en) 2013-09-07 2015-09-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Array-reader based magnetic recording systems with mixed synchronization
US9323625B2 (en) 2013-11-12 2016-04-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for lost synchronization data set reprocessing
US9224420B1 (en) 2014-10-02 2015-12-29 Avago Technologies General Ip (Singapore) Pte. Ltd. Syncmark detection failure recovery system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661760A (en) * 1995-10-23 1997-08-26 Quantum Corporation Wide biphase digital servo information detection, and estimation for disk drive using servo Viterbi detector
US5793548A (en) * 1995-05-12 1998-08-11 Cirrus Logic, Inc. Fault tolerant sync mark detector for comparing a sign and magnitude of a detected sequence to a target sync mark in sampled amplitude magnetic recording
US5867331A (en) * 1993-02-01 1999-02-02 Cirrus Logic, Inc. Synchronous read channel processing more than one channel sample at a time to increase throughput

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1105093A (fr) 1977-12-21 1981-07-14 Roland F. Drew Deposition au laser de metaux sur un substrat transparent
US4743463A (en) 1986-02-21 1988-05-10 Eastman Kodak Company Method for forming patterns on a substrate or support
JP2523509B2 (ja) 1986-06-30 1996-08-14 株式会社東芝 磁気記録再生装置
JPH04243063A (ja) 1991-01-18 1992-08-31 Matsushita Electric Ind Co Ltd 磁気ディスク装置
US5363360A (en) 1993-09-27 1994-11-08 Eastman Kodak Company Method and apparatus for detecting and processing synchronization marks extracted from a prerecorded wobbled groove on a compact disk
FI103396B (fi) 1994-03-24 1999-06-30 Laserplus Oy Menetelmä ja laite merkkausten tekemiseksi lasipintaan
US5572558A (en) 1994-11-17 1996-11-05 Cirrus Logic, Inc. PID loop filter for timing recovery in a sampled amplitude read channel
US5696639A (en) 1995-05-12 1997-12-09 Cirrus Logic, Inc. Sampled amplitude read channel employing interpolated timing recovery
US5729396A (en) 1995-05-12 1998-03-17 Cirrus Logic, Inc. Fault tolerant sync mark detector enabled relative to a frequency of an acquisition preamble for sampled amplitude recording
US5796535A (en) * 1995-05-12 1998-08-18 Cirrus Logic, Inc. Sampled amplitude read channel employing a user data frequency synthesizer and a servo data frequency synthesizer
US5760984A (en) 1995-10-20 1998-06-02 Cirrus Logic, Inc. Cost reduced interpolated timing recovery in a sampled amplitude read channel
US5726818A (en) 1995-12-05 1998-03-10 Cirrus Logic, Inc. Magnetic disk sampled amplitude read channel employing interpolated timing recovery for synchronous detection of embedded servo data
US5892632A (en) 1996-11-18 1999-04-06 Cirrus Logic, Inc. Sampled amplitude read channel employing a residue number system FIR filter in an adaptive equalizer and in interpolated timing recovery
US5835295A (en) 1996-11-18 1998-11-10 Cirrus Logice, Inc. Zero phase restart interpolated timing recovery in a sampled amplitude read channel
US6023386A (en) * 1997-10-31 2000-02-08 Cirrus Logic, Inc. Fault tolerant sync mark detector for synchronizing a time varying sequence detector in a sampled amplitude read channel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867331A (en) * 1993-02-01 1999-02-02 Cirrus Logic, Inc. Synchronous read channel processing more than one channel sample at a time to increase throughput
US5793548A (en) * 1995-05-12 1998-08-11 Cirrus Logic, Inc. Fault tolerant sync mark detector for comparing a sign and magnitude of a detected sequence to a target sync mark in sampled amplitude magnetic recording
US5661760A (en) * 1995-10-23 1997-08-26 Quantum Corporation Wide biphase digital servo information detection, and estimation for disk drive using servo Viterbi detector

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CIDECIYAN R D ET AL: "A PRML SYSTEM FOR DIGITAL MAGNETIC RECORDING" IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, IEEE INC. NEW YORK, US, vol. 10, no. 1, 1992, pages 38-56, XP000457625 ISSN: 0733-8716 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270481A (zh) * 2010-05-28 2011-12-07 Lsi公司 基于极限距离度量的位置检测同步标记的方法与装置
EP2390880A3 (fr) * 2010-05-28 2015-05-13 LSI Corporation Procédé et appareil pour détecter une marque de synchronisation sur la base d'une position d'une distance extrême
CN102270481B (zh) * 2010-05-28 2016-09-14 安华高科技通用Ip(新加坡)公司 基于极限距离度量的位置检测同步标记的方法与装置

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