Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q1/00—Details of selecting apparatus or arrangements
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
  • G06K7/0008—General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
  • G07C9/00—Individual registration on entry or exit
  • G07C9/20—Individual registration on entry or exit involving the use of a pass
  • G07C9/28—Individual registration on entry or exit involving the use of a pass the pass enabling tracking or indicating presence
• • G—PHYSICS
  • G08—SIGNALLING
  • G08G—TRAFFIC CONTROL SYSTEMS
  • G08G1/00—Traffic control systems for road vehicles
  • G08G1/01—Detecting movement of traffic to be counted or controlled
  • G08G1/017—Detecting movement of traffic to be counted or controlled identifying vehicles

Definitions

• This invention relates generally to RFID systems and in particular, to RFID systems including tags having different memory sizes.
• RFID systems are well known, and find numerous uses.
• RFID systems are used in access control applications where employees use RFID "proximity" cards or tags to gain access to authorized areas, or tags are bolted to the undercarriage of transport trucks and other types of vehicles to allow them access to a facility.
• RFID systems are used in animal identification applications where individualized tags are placed on the ears of livestock to identify each animal.
• RFID systems are used in container tracking applications where individualized tags are fixed to reusable containers to facilitate accurate records of their use.
• RFID tags also referred to as “transponders” or “labels”
• the number and size of the data blocks transmitted may be different among tags, however, due to differences in application requirements or differences in the memory structures storing such data within the tags. Differences in memory or data structures result from different numbers of data blocks or different numbers of bits in each data block being transmitted. Different manufacturers of the tags or the memories employed in the tags are one cause for the different memory structures being used in the tags. Advancements in manufacturing techniques are another cause.
• one aspect of the invention is a synchronization method for an RFID system including tags having different memory sizes, comprising the steps of: storing a sync word in a first area in a tag memory, and storing data bits and sync bits in a second area in the tag memory such that the sync word cannot occur in the data bits and the sync bits.
• a synchronization method for an RFID system including tags having different memory sizes, comprises the steps of: transmitting a sync word serially modulated on an RF signal, and transmitting data bits and sync bits serially modulated on the RF signal such that the sync word cannot occur in the data bits and the sync bits.
• a synchronization method for an RFID system including tags having different memory sizes, comprises the steps of: receiving an RF signal serially modulated by repetitions of contents of a tag memory storing a sync word, data bits, and sync bits such that the sync word cannot occur within the data bits and the sync bits; identifying one of the repetitions of the sync word serially modulated on the RF signal; and reading data bits following the one of the repetitions of the sync word serially modulated on the RF signal, until a next one of the repetitions of the sync word is received serially modulated on the RF signal.
• an RFID tag for an RFID system including tags having different memory sizes, comprises a tag memory, a control circuit and a modulator circuit.
• the tag memory has a sync word stored at one end of the tag memory, and data bits and sync bits stored in a remainder of the tag memory such that the sync word cannot occur in the
• an RFID reader for an RFID system including tags having different memory sizes comprises a receiver circuit and a processor.
• the receiver circuit is coupled to an RF signal serially modulated by repetitions of a sync word, data bits, and sync bits organized such that the sync word cannot occur within the data bits and the sync bits.
• the processor is coupled to the receiver circuit.
• an RFID system including tags having different memory sizes, comprises a plurality of tags and an RFID reader.
• the plurality of tags individually include a tag memory, a control circuit and a modulator circuit.
• the tag memory has a sync word stored at one end of the tag memory and data bits and sync bits stored in a remainder of the tag memory such that the sync word cannot occur in the data bits and the sync bits.
• the control circuit provides address and control signals to the tag memory so as to read out contents of the tag memory.
• the modulator circuit generate an RF signal serially modulated by repetitions of the contents of the tag memory.
• the RFID reader includes a receiver circuit and a processor.
• the receiver circuit is coupled to the RF signal, and the processor.
• the processor includes a memory storing a program causing the processor to identify one of the repetitions of the sync word serially modulated on the RF signal, and to read data bits following the one of the repetitions of the sync word until a next one of the repetitions of the sync word is received on the
• FIG. 1 is a block diagram of an RFID system including tags having different sizes, utilizing aspects of the present invention.
• FIG. 2 is an example of a tag memory organization including a 32- bit sync word, utilizing aspects of the present invention.
• FIG. 3 is an example of a tag memory organization including a 24- bit sync word, utilizing aspects of the present invention.
• FIG. 4 is an example of a tag memory organization including a 16- bit sync word, utilizing aspects of the present invention.
• FIG. 5 is an example of a tag memory organization including a 9-bit sync word, utilizing aspects of the present invention.
• FIG. 6 is an example of a tag memory organization including a 16- bit sync word beginning at a beginning address of the tag memory, utilizing aspects of the present invention.
• FIG. 7 is an example of a tag memory organization including a 16- bit sync word ending at an ending address of the tag memory, utilizing aspects of the present invention.
• FIG. 8 is a first example of a prior art tag memory organization.
• FIG. 9 is a second example of a prior art tag memory organization.
• FIG. 10 is a third example of a prior art tag memory organization.
• FIG. 1 1 is an example of repetitions of the contents of any one of the first, second, or third examples of a prior art tag memory organization.
• FIG. 12 is a flow diagram of a synchronization method for an RFID system including tags having different memory sizes, utilizing aspects of the present invention.
• FIG. 1 is a block diagram of an RFID system 10 including tags having different memory sizes. Included in the RFID system 10 are a host computer 20, an RFID reader 30, and a plurality of RFID tags 40-1 to 40-n having different memory sizes.
• RFID tag 40-1 is representative of the RFID tags 40-1 to 40-n, and for the purposes of the following discussion, RFID tag 40-1 is assumed to be proximate to the RFID reader 30 so that its one or more antenna elements 401 receive an exciter signal 301 transmitted through corresponding one or more antenna elements 302 of the RFID reader 30.
• An exciter circuit 303 of the RFID reader 30 generates the exciter signal 301.
• a power circuit 402 on the RFID tag 40-1 rectifies the received exciter signal 301 to generate an internal supply voltage Vdd for other circuitry on the RFID tag 40-1. If commands or data are superimposed or modulated onto to a carrier signal of the exciter signal 301 , the power circuit 402 passes the exciter signal 301 to a decode circuit 403.
• the decode circuit 403 demodulates the exciter signal 301 and performs an analog-to-digital conversion to produce the command or data in digital form, which it provides to a control circuit 404.
• the power circuit 402 also passes the exciter signal 301 to a clock generator circuit 405.
• the clock generator circuit 405 generates two clock signals.
• One clock signal has the same frequency as the exciter carrier signal, and is provided to the control circuit 404.
• the other clock signal has a different frequency than the exciter carrier signal, and is provided to a modulator circuit 406 to serve as a tag carrier signal for an RF signal 408 transmitted from the RFID tag 40-1.
• the frequency of the tag carrier signal is approximately half that of the exciter carrier signal to distinguish the two carrier signals.
• the control circuit 404 includes an address counter (not shown) which increments the address to a tag memory 407.
• the control circuit 404 In response to the exciter signal 301 , the control circuit 404 generates appropriate control signals to cause information to be repetitively read out of the tag memory 407 in a serial fashion at the rate of the exciter carrier signal. The information is then provided to the modulator circuit 406.
• the modulator circuit 406 superimposes or modulates the information onto the tag carrier signal to generate the RF signal 408 serially modulated by repetitions of the contents of the tag memory 407.
• the RF signal 408 is serially modulated by repetitions of a sync word, data bits, and sync bits oganized such that the sync word cannot occur within the data bits and the sync bits.
• a transmitting antenna 409 coupled to the modulator circuit 406 transmits the RF signal 408 to a receiving antenna 304 on the RFID reader 30.
• a receiver circuit 305 is coupled to the RF signal 408 through the receiving antenna 304, to receive and amplify the RF signal 408.
• the receiver circuit 305 preferably also converts the frequency of the RF signal 408 to an intermediate frequency for further amplification and bandpass filtering before providing it to a detector circuit 306.
• the detector circuit 306 detects information serially modulated on the RF signal 408, and provides the information to a processor 307, which produces an output in a format usable by the host computer 20.
• the processor 307 includes a memory (not shown) storing a program to be executed by the processor 307.
• the host computer 20 processes the information passed to it by the processor 307.
• the tag memory 407 may be different sizes by being configured in various memory or data structures having different numbers of blocks and/or different numbers of bits per block.
• FIG. 2 illustrates a data structure for tag memory 407 having 7 blocks of 32 bits each
• FIG. 6 illustrates a data structure having 7 blocks of 16 bits each
• FIG. 8 illustrates a data structure having 3 blocks of 5 hexadecimal characters each (or 20 bits each, since each hexadecimal character is 4 bits).
• the RFID reader 30 Since the contents of the tag memory 407 are read out repetitively to be serially modulated on the RF signal 408, it may be difficult or impossible for the RFID reader 30 to determine the repetitive pattern (i.e., contents of the tag memory 407) without prior knowledge of the data structure.
• the pattern "0123456789ABCDE'' is stored in a first example of a prior art tag memory organization
• the pattern "56789ABCDE01234" is stored in a second example of a prior art tag memory organization
• the pattern in FIG. 8, the pattern "0123456789ABCDE'' is stored in a first example of a prior art tag memory organization;
• the pattern "56789ABCDE01234" is stored in a second example of a prior art tag memory organization; and in FIG. 10, the pattern
• ABSOR0123456789 is stored in a third example of a prior art tag memory organization. Yet problematically, each of these patterns generate the same repetitive or recursive pattern depicted in FIG. 11 , as information is read out of the tag memory 407 starting in the top left comer, reading to the right along each block, reading blocks from top to bottom, and ending in the bottom right comer. As another example, in certain repetitive patterns such as all 1 's, all O's, or alternating 1 's and O's, it is also virtually impossible for the RFID reader 30 to determine the length of the recurring pattern without prior knowledge of the data structure.
• sync bits are interspersed at appropriate bit locations in the recurring pattern. The RFID reader 30 may then determine the recurring pattern by first finding the sync word, then reading the data following the sync word until a next
• a sync word 52 is shown as "1000000000000001" beginning at a beginning address of the tag memory 407, sets of sync bits of "01” such as the set of sync bits 54 in the seventh block of the memory structure are interspersed among data bits "x" such as data bits 56 such that the sync word cannot occur within the data bits and sync bits.
• the sync word and sync bits are also referred to as “system bits”, and the data bits as "user data bits”.
• Successive data bits between the sync word and a set of sync bits, or between sets of sync bits, are referred to as "data words” such as data word 58 in the second block of the tag memory 407.
• the sync word is predefined as a bit pattern in which the largest number of O's are sandwiched between two 1's within the contents of the data structure.
• sets of sync bits of "01" are periodically inserted among the data bits such that the number of data bits between adjacent sets of sync bits is less than or equal to four (4) bits less than the number of bits in the sync word.
• a single sync bit of "1" may be used instead of the pair of sync bits "01". In this case, the number of data bits between adjacent sync bits would be less than or equal to three (3) bits less than the number of bits in the sync word.
• the number of data bits between adjacent sets of sync bits "01" may be less than four bits less than the number of bits in the sync word, preferably the number of data bits between adjacent sets of sync bits is set equal to four bits less than the number of bits in the sync word so that the maximum number of bits are made available in the data structure for data bits. Also, by following this convention, the locations of the sync bits are thus readily determinable after the RFID reader 30 has identified the sync word, making it easier for the RFID reader 30 to mask out or strip off the sync bits while reading the data bits serially modulated on the RF signal 408.
• the data structure of the tag memory 407 is also readily determinable by the RFID reader 30.
• This convention may not be practical for data structures including a relatively small number of blocks.
• a shorter sync word such as shown in FIG. 3 sometimes allows more data bits to be available in the tag memory 407 than a sync word using up the entire first block.
• FIG. 4 and FIG. 5 this is not generally the case.
• the RFID reader 30 may readily determine the contents or repetitive pattern stored therein from information modulated on a received RF signal 408.
• FIG. 12 illustrates a flow diagram of a synchronization method for the RFID system 10 including tags 40-1 to 40-n having different memory sizes.
• a first step 1201 comprises the step of storing a sync word in a first area in a tag memory.
• the first area is preferably successive bit locations beginning at a beginning address of the tag memory such as depicted in FIG. 6.
• the step of storing a sync word comprises the step of storing a sync word in successive bit locations beginning at a beginning address of said tag memory.
• the first area may be successive bit locations ending at an ending address of the tag memory such as depicted in FIG. 7.
• the step of storing a sync word comprises the step of storing a sync word in successive bit locations
• the step of storing a sync word comprises the steps of: storing one bit of a first binary state, storing a plurality of bits of a second binary state, and storing one bit of said first binary state.
• the storing of the sync word is preferably performed by programming the tag memory by conventional methods and means after manufacture. However, the storing of the sync word can be alternatively performed with similar benefit during the manufacturing process of the tag memory or the tag by conventional methods and means.
• a second step 1202 comprises the step of storing data bits and sync bits in a second area in said tag memory such that said sync word cannot occur in said data bits and said sync bits.
• the second area is a remainder of the tag memory after storing the sync word in the tag memory.
• the sync bits are interspersed among said data bits such that said sync word cannot occur in said remainder of said tag memory.
• the step of storing data bits and sync bits comprises the steps of: organizing data bits into data words individually having a number of data bits at least four less than a number of bits in said sync word; organizing sync bits into sets of sync bits individually having at least one bit of said first binary state; and storing said data words and said sets of sync bits in said tag memory by interleaving said sets of sync bits with said data words.
• the storing of the data bits and sync bits is preferably performed by programming the tag memory by conventional methods and means after manufacture. However, the storing of the data bits and sync bits can be alternatively performed with similar benefit during the manufacturing process of the tag memory or the tag by conventional methods and means.
• a third step 1203 comprises the step of transmitting a sync word serially modulated on an RF signal.
• said step of transmitting said sync word comprises the steps of: transmitting one bit of a first binary state; transmitting a plurality of bits of a second binary state; and transmitting one bit of said first binary state.
• the control circuit 404 in the tag memory 407 generates appropriate control signals to cause information to be repetitively read out of the tag memory 407 in a serial fashion, and provided to the modulator circuit 406 which generates an RF signal 408 serially modulated by contents of the tag memory 407.
• a transmitting antenna 409 coupled to the modulator circuit 406 thereupon transmits the RF signal 408.
• a fourth step 1204 comprises the step of transmitting data bits and sync bits serially modulated on said RF signal such that said sync word cannot occur in said data bits and said sync bits.
• said step of transmitting data bits and sync bits comprises the step of transmitting data bits organized into data words individually having a number of data bits at least four less than a number of bits in said sync bit, and sync bits organized into sets of sync bits individually having at least one bit of said first binary state, such that said sets of sync bits are interleaved with said data words.
• control circuit 404 in the tag memory 407 generates appropriate control signals to cause information to be repetitively read out of the tag memory 407 in a serial fashion, and provided to the modulator circuit 406 which generates an RF signal 408 serially modulated by contents of the tag memory 407.
• a transmitting antenna 409 coupled to the modulator circuit 406 thereupon transmits the RF signal 408.
• a fifth step 1205 comprises the step of receiving an RF signal serially modulated by repetitions of contents of a tag memory storing a sync word, data bits, and sync bits such that said sync word cannot occur within said data bits and said sync bits.
• receiver 305 is coupled to the receiving antenna 304, to receive and amplify the RF signal 408, as described in reference to FIG. 1.
• a sixth step 1206 comprises the step of identifying one repetition of said sync word serially modulated on said RF signal.
• the step of identifying one repetition of said sync word comprises the step of finding a longest sequence of bits of said second binary state serially modulated on said RF signal. Since the sync word is organized as one bit of a first binary state, a plurality of bits of a second binary state, and one bit of said first binary state, this entails finding the longest sequence of bits of the second binary state serially modulated on the RF signal.
• the processor 307 includes a memory (not shown) storing a program which causes the processor 307 to identify one repetition of said sync word by finding a maximum number of consecutive bits in the second binary state, using conventional programming methods.
• a seventh step 1207 comprises the step of reading data bits following said one of said repetitions of said sync word serially modulated on said RF signal, until a next repetition of said sync word is received serially modulated on said RF signal.
• said step of reading data bits comprises the steps of: (a) reading a number of successive data bits, said number being four bits less than the number of bits of said sync word;
• the processor 307 includes a memory (not shown) storing a program which causes the processor 307 to perform such steps, using conventional programming methods.
• One advantage of the present invention is an RFID system capable of reading data transmitted from tags having different memory sizes, allowing compatibility among existing and future commercially available
• Another advantage is an RFID system capable of reading data transmitted from tags having different memory sizes, allowing intersystem operability and reduction in the overall cost of such system.

Applications Claiming Priority (5)

Publications (2)

Family

ID=26759922

Family Applications (1)

Country Status (9)

Families Citing this family (12)

Citations (4)

Family Cites Families (4)

• 1999
  • 1999-03-04 CN CN99803980A patent/CN1313011A/zh active Pending
  • 1999-03-04 BR BR9908714-6A patent/BR9908714A/pt not_active IP Right Cessation
  • 1999-03-04 IL IL13774999A patent/IL137749A0/xx unknown
  • 1999-03-04 WO PCT/US1999/004860 patent/WO1999046940A1/en active IP Right Grant
  • 1999-03-04 EP EP99909858A patent/EP1068738A4/de not_active Withdrawn
  • 1999-03-04 JP JP2000536204A patent/JP2003532935A/ja active Pending
  • 1999-03-04 AU AU28966/99A patent/AU2896699A/en not_active Abandoned
  • 1999-03-04 KR KR1020007010095A patent/KR20010052206A/ko active IP Right Grant
  • 1999-03-04 CA CA002322152A patent/CA2322152A1/en not_active Abandoned

Patent Citations (4)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events