EP1046194A1 - Interrupteur bidirectionnel a semi-conducteur et circuit de commutation pour equipements alimentes par batterie - Google Patents

Interrupteur bidirectionnel a semi-conducteur et circuit de commutation pour equipements alimentes par batterie

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Publication number
EP1046194A1
EP1046194A1 EP99969847A EP99969847A EP1046194A1 EP 1046194 A1 EP1046194 A1 EP 1046194A1 EP 99969847 A EP99969847 A EP 99969847A EP 99969847 A EP99969847 A EP 99969847A EP 1046194 A1 EP1046194 A1 EP 1046194A1
Authority
EP
European Patent Office
Prior art keywords
switch
body region
gate
trench
battery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99969847A
Other languages
German (de)
English (en)
Inventor
Raymond J. Grover
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1046194A1 publication Critical patent/EP1046194A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Definitions

  • This invention relates to bi-directional semiconductor switches, and more particularly to three-terminal trench-gate switches suitable for connecting and disconnecting a battery in a battery-powered equipment, for example a portable computer or an electric razor.
  • the invention also relates to switch circuits comprising such trench-gate bi-directional semiconductor switches and to battery-powered equipment comprising such switches and switch circuits.
  • a battery In portable applications, a battery is used to power electrical equipment and becomes discharged in normal use.
  • the expression "battery” as generally used nowadays, and as specifically used in the present text, is understood as including within its scope a single power cell, as well as relating to combinations of power cells.
  • a re-chargeable battery When a re-chargeable battery is used, it may be re-charged from an external power source, during which time it may be disconnected from the load power line in the equipment.
  • Semiconductor power switches are normally used for connecting and disconnecting the battery. The switch has to block in both directions, for example to prevent overcharging and/or to prevent operation into a short-circuited load under a fault condition. It may also have to conduct in both directions, for example depending on whether the cell is being charged or discharged.
  • the normal solution is to use as the switch a back-to-back arrangement of two low voltage MOSFETs (insulated-gate field-effect transistors) in series connection.
  • This solution requires a large semiconductor area (for the layout of two separate MOSFETS) and has four external terminals (or six terminals if the two MOSFETs are not in a single packaged device).
  • United States patent specification US-A-5,682,050 discusses such background situations for the switch circuits and devices, together with the difficult requirements in different circuit conditions. It also proposes a particular bi-directional semiconductor switch as an improvement over a back-to-back arrangement of two MOSFET devices. This bi-directional switch is a four-terminal MOSFET in which there is no source-body short.
  • It comprises a semiconductor body in which a channel-accommodating body region of a first conductivity type is present between first and second regions (source and drain regions) of an opposite second conductivity type.
  • the body region may have a substantially uniform doping concentration of the first conductivity type which is of smaller magnitude than the doping concentrations of the second conductivity type of the source and drain regions.
  • the source and drain regions form p-n junctions with the body region and separate these p-n junctions from respective first and second main electrodes (source and drain electrodes) in electrical contact with the source and drain regions, i.e. the p-n junctions are not shorted by these electrodes.
  • a gate is capacitively coupled to the body region for inducing therein a conduction channel of charge carriers of the second conductivity type between the source and drain regions in an on-state of the switch.
  • the fourth terminal of this switch is an electrode connection to the body region.
  • WO 97/44828 discloses a three-terminal bi-directional semiconductor switch in the form of a trench-gate device, comprising a semiconductor body in which the channel-accommodating body region forms plane p-n junctions with the first and second regions of the second conductivity type.
  • the first and second regions separate the p-n junctions from respective first and second main electrodes in electrical contact with the first and second regions.
  • the first region and first main electrode are present adjacent a first major surface of the body from which a trench-gate extends through the first region and through the channel-accommodating region and into the second region.
  • This trench-gate is capacitively coupled to the channel- accommodating region for inducing therein a conduction channel of charge carriers of the second conductivity type between the first and second regions in an on-state of the switch.
  • the channel-accommodating region has a substantially uniform doping concentration of the first conductivity type which is of smaller magnitude than the doping concentrations of the second conductivity type of the first and second regions.
  • the whole contents of both US-A-5,682,050 and WO 97/44828 are hereby incorporated herein as reference material.
  • the thickness, width and uniform doping concentration of the body region in the switch of WO 97/44828 are chosen such that the body region is fully depleted by the combined effects of the gate and of the p-n junctions in an off-state of the switch.
  • the uniform doping concentration of the body region is sufficiently high to avoid punch-through of the depletion layers from the p-n junctions.
  • WO 97/44828 teaches (for example at page 4 line Iff) that, first and foremost, the body region must have a well-defined potential in order to prevent the threshold voltage of the MOSFET from drifting upward and downward uncontrollably. In the absence of a shorting electrode connection or separate electrode connection to the body region, WO 97/44828 teaches (for example at page 6 line 4ff, and page 7 lines 3 to 34 ) that this is achieved by fully depleting the body region so that it does not float in potential.
  • the width of the body region (as determined by the mesa width of its cellular trench-gate structure) is made sufficiently narrow that the added effect of the gate potential in the off-state of the switch effectively depletes the entirety of the body region.
  • the relevant criteria for the dimensions and doping concentration of the body region are taught at page 10 line 15 to page 13 line 18. These criteria are not easy to implement in a high-volume manufacturing context.
  • a trench-gate bi-directional semiconductor switch having the features set out in Claim 1, and there are also provided switch circuits having the features set out in Claims 5 and 6.
  • the dimensions and doping concentration of the body region are sufficiently large that an area of the body region remains undepleted (retaining its first conductivity type as an area of floating potential) in all bias conditions of the first and second main electrodes and of the trench-gate.
  • the realisation of this switch structure (in terms of the relevant criteria for the dimensions and doping concentration of the body region) is easier to implement in a high-volume manufacturing context, than that of the switch of WO 97/44828.
  • the body region does not need to be made so narrow, and its precise width does not have to correspond exactly with the laterally depleting effect of the gate.
  • the resulting undepleted area of the body region of a switch in accordance with the invention does float in potential, its potential does not drift uncontrollably. Its potential moves between well-defined states, which the Applicant finds to be acceptable for use in switch circuits for battery-powered equipment.
  • the present invention permits the realisation of a three- terminal switch with an advantageous structure for manufacture.
  • the blocking voltage capability of the switch in the off-state is determined by breakdown voltages of the plane p-n junctions (together with the gain of the parasitic bipolar transistor formed by these two p-n junctions). These breakdown voltages can be reproducibly controlled in a high-volume manufacturing context.
  • Figure 1 is a cross-sectional view of an active central part of a trench- gate bi-directional semiconductor switch in accordance with the invention
  • Figure 2 is a circuit diagram of the switch of Figure 1 in a switch circuit of a battery-powered equipment in accordance with the invention
  • Figure 3A is a simplified cross-sectional view of the region structure of the switch part of Figure 1 , when the trench-gate bi-directional semiconductor switch is in an on-state;
  • Figure 3B is a simplified cross-sectional view of the region structure of the switch part of Figure 1 , when the trench-gate bi-directional semiconductor switch is in an off-state;
  • Figure 4A depicts a change in gate voltage Vg with time t, when switching the trench-gate bi-directional semiconductor switch in a switch circuit; and Figure 4B illustrates the corresponding variation in potential Vf of the channel-accommodating body region of the trench-gate bi-directional semiconductor switch.
  • the trench-gate bi-directional semiconductor switch 101 of Figure 1 is a low-voltage 3-terminal device comprising a semiconductor body 10 which accommodates an array of parallel device ceils between first and second main electrodes 11 and 12. These electrodes 11 and 12 provide the terminals S/D and D/S of the current-carrying path through the switch.
  • Each cell of the switch comprises a channel-accommodating body region 3 of a first conductivity type (p-type in this example) which is sandwiched between first and second regions
  • first and second regions 1 and 2 separate the p-n junctions 31 and 32 from the respective first and second main electrodes 11 and 12 (hereinafter termed “source and drain electrodes” respectively) which are in electrical contact with the regions 1 and 2.
  • the source region 1 and source electrode 11 are present adjacent a first major surface 10a of the body 10.
  • the source electrode 11 is common to all the device cells of the array and connects in common the individual source regions 1 of the cells.
  • the switch 101 has a trench-gate 13 present in a trench 33 which extends from the surface 10a through the source region 1 and through the body region 3 and into the drain region 2.
  • the trench-gate 13 is insulated from the source electrode 11 by an intermediate insulating layer 20 on the trench-gate 13 and is contacted outside the plane of the Figure 1 drawing to provide the control, third terminal G of the switch.
  • the plane p-n junctions 31 and 32 terminate at the sidewalls of the trench 33.
  • the trench-gate 13 is capacitively coupled to the portion of the body region 3 adjacent the sidewall (across a gate insulating layer 23 in the Figure 1 embodiment).
  • This capacitive coupling serves in known manner for inducing in the body region 3 of the first conductivity type a conduction channel 12 of charge carriers of the second conductivity type (electrons in the Figure 1 example) between the source and drain regions 1 and 2 in an on-state of the switch, as illustrated in Figure 4A.
  • the control voltage Vg applied on the trench-gate 13 serves in known manner for controlling current flow in this conduction channel 12 between the main terminals S and D of the switch.
  • the body region 3 has a substantially uniform doping concentration (P) of the first conductivity type which is of smaller magnitude than the doping concentrations (N+) of the second conductivity type of the source and drain regions 1 and 2.
  • this undepleted area 3a retains its first-conductivity-type characteristics in all bias conditions Vs/d, Vd/s, Vg of the source and drain terminals S/D and D/S and of the trench-gate terminal G, and it has a floating potential Vf.
  • this floating undepleted area 3a gives the switch a blocking voltage capability between the source and drain electrodes 11 and 12 that is determined by breakdown voltages of the plane p-n junctions 31 and 32 and the gain of the parasitic N+/P/N+ transistor 1 ,3,2.
  • This floating undepleted area 3a gives the switch an important distinction as compared with the switch in WO 97/44828.
  • the body 10 is of monocrystalline silicon
  • the trench-gate 13 is of conductively doped polycrystalline silicon on a gate insulating layer 23 of silicon dioxide
  • the electrodes 11 and 12 are of, for example, aluminium.
  • the doped trench-gate 13 is usually of opposite conductivity type (i.e. n-type in the Figure 1 example) to the conductivity type of the body region 3 in order to achieve a low threshold voltage.
  • the switch typically comprises many thousands of parallel device cells in the semiconductor body 10 adjacent to the body surface 10a. The number of cells is dependent on the desired current-carrying capability of the switch.
  • Switches in accordance with the invention may have any one of a variety of known cell geometries, for example an hexagonal close-packed geometry, or a square geometry, or an elongate stripe geometry.
  • the trench-gate 13 extends laterally around the boundary of each cell, as a common insulated-gate electrode of the array. Thus, the trench-gate 13 laterally bounds the regions 1 and 3 in these cells, and part of the drain region 2.
  • the drain region 2 is common to all the cells.
  • Figure 1 shows a vertical switch configuration in which the drain region 2 may be a silicon substrate of high conductivity, on which the body region 3 is epitaxially deposited. In this vertical configuration, the substrate (which forms the drain region 2) is contacted at the bottom major surface 10b of the device body 10 by the drain electrode 12.
  • the device structure of the Figure 1 switch in accordance with the present invention is similar to that of a conventional trench-gate MOSFET and may be manufactured using known MOSFET technologies, except that there no epitaxial drain-drift region, and no source-body region short, and the body region 3 is an epitaxial layer.
  • the active cellular area of the switch may be bounded around the periphery of the body 10 by any one of a variety of known MOSFET peripheral termination schemes, which are not shown in Figure 1.
  • Such termination schemes normally include the formation of a thick field-oxide layer around the peripheral area of the body surface 10a, before the cell fabrication steps.
  • both the n-type regions 1 and 2 will have much higher donor doping concentratrations than the acceptor doping concentration of the p-type body region 3 and preferably substantially the same doping concentrations as each other, at least adjacent to their p-n junctions 31 and 32 with the body region 3.
  • the switch can have a substantially symmetrical blocking voltage capability between its first and second main electrodes 11 and 12.
  • the electrode 11 has been described as the source electrode and the electrode 12 as the drain electrode, it will be clear that these terms “source” and “drain” are interchangeable, particularly in this case of symmetrical characteristics. For this reason, in Figure 1 , the "source” terminal is designated S/D and the “drain” terminal is designated D/S. Similarly in Figures 3 and 4, the "source” voltage is designated Vs/d and the “drain” voltage is designated Vd/s.
  • FIG. 2 illustrates a specific example of a switch circuit for a battery-powered equipment, for example a portable computer.
  • the circuit includes a trench-gate bi-directional switch 101 which comprises a semiconductor body 10 with the Figure 1 device structure.
  • the switch 101 is represented by a special compound symbol of an insulated gate controlling conduction through back-to-back diodes, the insulated gate being the trench-gate 13 and the back-to-back diodes being the p-n junctions 31 and 32 formed with the p-type base region 3, at least the part 3a of which remains undepleted.
  • the compound symbol also includes a third diode corresponding to the p-n junction which the p-type base region 3 also forms with the induced n-type channel 12 as a floating "back gate" of the switch.
  • the switch circuit also comprises a rechargeable battery 103, a connectable battery charger 104, a control circuit 105, a power line 106 for powering a load 107 forming part of the equipment, and a return
  • the output line 111 is coupled to the trench-gate 13 (terminal G) of the switch 101 so as to apply a control signal Vg to the switch 101 for powering the power line 106 from the battery 103 when the conduction channel 12 is induced between the first and second regions 1 and 2 in the on-state of the switch 101 and for disconnecting the battery 103 from the power line 106 in the off-state of the switch 101 when the blocking voltage capability between the first and second main electrodes 11 and 12 is determined by the plane p-n junctions 31 and 32.
  • another battery or an alternative power supply may also be coupled to the power line 106 (for example via another switch, not shown), for powering the load 107 when the battery 103 is disconnected.
  • Figure 2 does however show (in broken outline) a battery charger unit 104, which may additionally provide an alternative power supply to the load 107 when the battery 103 is being recharged.
  • the bi-directional switch 101 only has to block about 10 volts in its off-state. In its on-state, the on-resistance through the switch 101 should typically not exceed 40 milliohms. These characteristics are achievable with the device structure of Figure 1 in accordance with the present invention.
  • the switch 101 effectively replaces two back-to-back conventional MOSFETs, so offering at least a factor four reduction in silicon area.
  • the Figure 1 device structure will first be compared with a conventional trench-gate MOSFET not in accordance with the present invention, in which an implanted/diffused p-body region 3' is shorted to the source region 1'.
  • This short ensures that the potential of the p-body region 3' is precisely defined, and that the action of the parasitic transistor formed by the N+ source region 1 ', p-body region 3' and N+ drain region 2' is well suppressed.
  • the shorting of the p-body region 3' to the source region 1' means that the MOSFET can only block in one direction, i.e. with D' (electrode 12') positive with respect to S' (electrode 11'). If the drain region 2' is made negative, then the p-n junction 32' between the body region 3' and the drain region 2' is forward biased and current flows.
  • the trench-gate structure of Figure 1 has a p-body region 3 which is at a floating potential Vf and which is formed as a uniformally doped epitaxial layer rather than by diffusion.
  • the Figure 1 device can therefore block in both directions.
  • the blocking voltage is BVceo, the common-emitter breakdown voltage of the n-p-n parasitic transistor 1,3,2 with open base.
  • the magnitude of BVceo is typically only a third of that of BVces (the collector- emitter breakdown voltage of the n-p-n parasitic transistor with its base shorted to the emitter), but this is not a limitation for a low voltage device such as the switches 101 and 102.
  • the doping level of the p-body region 3 can be chosen to give a value of BVces which is high enough to give an adequate BVceo, without degrading the on-resistance of the switch.
  • the on-resistance is dominated by the channel 12 rather than the source and drain regions 1 and 2.
  • Typical p-body region doping levels and dimensions are now discussed with reference to Figures 3A and 3B for a 10 volt device, assuming the BVceo is a third of the BVces. Assuming a one-sided approximation (in which the N+ doping of the regions 1 and 2 is much higher than the P doping of the region 3), then the P doping concentration should be no more than 3x10 16 cm "3 for the p- body region 3 to withstand 30 volts. Punch-through has to be prevented at the working voltage of 10 volts.
  • the width of the depletion region 30 at 10 volts is 0.6 ⁇ m (micrometres), and so a thickness X of, for example, 1.0 ⁇ m will be quite adequate for the region 3, leaving a floating undepleted area 3a of thickness x of about 0.4 ⁇ m.
  • the specific on-resistance of the switch arising from the channel length will be at least as good as, for example, 50m ⁇ .mm 2 , which is a typical on-resistance achievable for a 30 volt conventional trench-gate MOSFET with a cell pitch H of 9 ⁇ m and a width Y of 6 ⁇ m for the body region 3'.
  • the depth Xs of the source region 1 may be, for example, about 0.2 ⁇ m.
  • the cell pitch H in the bi-directional switch of the present invention can be quite small, as there is no space needed for short-circuiting the source region 1 to p-body region 3. This small cell pitch will also substantially reduce the on-resistance as compared with a conventional trench-gate MOSFET.
  • the base region 3 must be given a sufficient width Y that the area 3a does not become depleted by the effect of the gate potential Vg.
  • the width Y may be about 4 ⁇ m or more (for example up to at most 6 ⁇ m or so), in which case the undepleted width y of the area 3a is at least about 4 ⁇ m in the off-state of the switch.
  • this switch 101 , 102 operates with a floating p-body region 3
  • the switch is operated with a conventional polarity of positive drain voltage Vd/s (for example +10v), with the source voltage Vs/d at zero volts or at a reference voltage, and with a varying gate voltage Vg as illustrated in Figure 4A.
  • Vd/s positive drain voltage
  • Vg the floating potential Vf of the p- body region 3 illustrated in Figure 4B.
  • the polysilicon doping of the trench-gate 13 and the thickness of the gate oxide 23 are such that the threshold voltage for channel conduction would be about 0.8v if the p- body region 3 were shorted to the source region 1 as in a conventional MOSFET device, and that the device would then be turned on hard at 5v. In these circumstances: with Vg at zero voltage.
  • the switch is in the off-state of Figure 3B.
  • the drain to p-body junction 32 is reverse biased with a depletion region 30 over part of the p-body region 3, and only a small leakage current flows across the junction 32.
  • the leakage current has to flow through to the source region 1, so putting a small forward bias on the source to p-body junction 31, for example of 0.4v.
  • the p-body region 3 is therefore slightly more positive than the source region 1, and so the area of the p-body region 3 under the influence of the trench-gate 13 is less depleted than normal. with Vg at 0.8v (the normal threshold voltage for a conventional MOSFET with short).
  • the p-body region 3 is more positive than normal (effectively similar to a "back-bias" situation), and so the gate voltage Vg is not sufficient to form an inversion channel 12, and the device is still in its off-state. • with Vg at about 1.2v.
  • the extra voltage on the trench-gate 13 is now sufficient to counteract the "back-bias" of the p-body region 3 and an inversion channel 12 is formed. with Vg at about 5.0v.
  • the channel 12 is formed and has low resistance.
  • the load 107 would now drop most of the voltage, and the drain terminal D would therefore be at a low potential, given by the IR drop, where I is the current through the switch and R is the on-resistance of the switch.
  • the drain is at 80 mV with a current I of 2 Amps.
  • the floating potential Vf of the p-body region 3 must now be intermediate between the source and drain voltages Vs/d and Vd/s, and so Vf is close to zero.
  • the Figure 1 device is turned on hard, just as it would be if the source region 1 was short-circuited to the p-body region 3.
  • a non-trivial point is how quickly the device can switch, since large capacitative currents flow into and out of the gate terminal G during switching.
  • the device does not have to operate at high frequencies, but will have to be able to respond to fault conditions in, for example, a few microseconds.
  • Vd/s positive voltage
  • the depletion region 30 in the p-body region 3 increases in width.
  • the holes which are released have to escape from the p-body region 3. They do this by flowing across the forward-biased source to p-body junction 31. If the current is large the bias will increase to, for example, 0.7v in this process; but, since a forward-biased junction can carry large current densities, there will be no problem.
  • the channel 12 is formed the extra charge goes into the inversion region which forms the channel 12, rather then into the depletion region 30. This channel 12 has an ohmic connection to the source region 1 , so again there is no problem.
  • the change in the charge comes from the collapsing depletion region 30 in the p-body region 3.
  • This collapse requires holes to flow in to neutralise the acceptors which make up the space charge of the depletion region 30.
  • the p-body region 3 is only coupled by capacitance to the gate 13.
  • the potential Vf of the p-body region 3 will be dragged down by the same amount, since there is no path for the capacitor to discharge. This will take the p-body potential Vf down by e.g.
  • the p-body region 3 will alternate between a clamped positive potential of about 0.7v as the gate/p-body capacitor charges up and a high current flows across to the source, and a negative potential (dependent on the load impedance) of a fraction of 1 volt. Because of this, the "threshold voltage" will show some hysteresis or time constant, but as long as the drive voltage Vg is high, for example 5v, compared to this varying substrate bias, the device will switch satisfactorily. The turn off of the device will show a tail of current as the weak inversion region is approached and the increasing channel resistance R, combined with the capacitance C being discharged, give an increasingly large time constant RC.
  • the present invention permits the construction and use of a very simple switch of small area, and with an on-resistance of one quarter or less of the conventional back- to-back MOSFET pair solution. It may be used in switch circuits for all sorts of portable equipment which uses a low voltage rechargeable battery 103 or single cell for power.
  • the switch is a simple device to drive, since it has only one control terminal G, which may be biased with reference to either of the other two terminals S/D and D/S
  • the conventional back-to-back MOSFET pair has two gate terminals which complicate the drive circuitry.
  • the Figure 1 switch is inherently a high cell density device, since no short between the source and p-body has to be provided in each cell.
  • this device structure of a switch in accordance with the present invention (in terms of the relevant criteria for the dimensions X and Y and doping concentration P of the body region 3) is easier to implement in a high-volume manufacturing context, than that of the switch of WO 97/44828.
  • these dimensions and doping concentration are sufficiently large that the body region 3 retains an undepleted first-conductivity-type area 3a of floating potential in all bias conditions Vs, Vd, Vg of its three terminals S, D, G.
  • the width Y of the body region 3 of a switch in accordance with the invention does not need to be made so narrow as that of WO 97/44828, whose width needs to correspond exactly with the laterally depleting effect of the gate in WO 97/44828.
  • the undepleted inner area 3a of the body region 3 of a switch in accordance with the invention does float in potential, but its potential Vf does not drift uncontrollably. Its potential Vf floats between well-defined states, which the Applicant finds to be acceptable for use in switch circuits for battery-powered equipment.
  • the blocking voltage capability of the switch in the off-state is determined by breakdown voltages of the plane p-n junctions 31 and 32, and these breakdown voltages can be reproducibly controlled in a high-volume manufacturing context.
  • An n-channel switch has been described with reference to Figures 1 to
  • a p-channel switch is also possible in accordance with the invention, in which the regions 1 and 2 are p-type, the base region 3 is n-type and the conduction channel 12 is of holes.
  • the region 2 may be a doped buried layer between a device substrate and the epitaxial body region 3 and may be contacted by electrode 12 at the front major surface 10a via a doped peripheral contact region which extends from the surface 10a to the depth of the buried layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un interrupteur (101) bidirectionnel à semi-conducteur du type tranchée-grille idoine pour connecter/déconnecter la batterie (103) d'un équipement alimenté par batterie, tel qu'un ordinateur portable. L'interrupteur comporte des jonctions planes p-n (31, 32), formées par une région (3) du corps abritant des canaux et située entre une première et une deuxième région (1, 2), et séparées de leur première et deuxième électrode respective (11, 12) par cette première et cette deuxième région (1, 2). La tranchée-grille (13) s'étend dans une tranchée (33) à travers cette structure (1, 3, 2) de régions en sandwich. La région du corps (3) présente une concentration (P) en dopant sensiblement uniforme d'un premier type de conductivité, moindre que la concentration (N +) en dopant d'un deuxième type de conductivité de la première et de la deuxième région (1, 2). Les dimensions (X, Y) et la concentration (P) en dopant de la région (3) du corps sont suffisamment élevées pour que ladite région conserve une région (3a) non appauvrie (3) du premier type de conductivité à potentiel flottant dans toutes les conditions de polarisation de la première et de la deuxième électrode principales (11, 12) et de la tranchée-grille (13), ce qui confère à l'interrupteur (101) en position off une capacité de blocage de tension appliquée entre la première et la deuxième électrode (11, 12) déterminée par les jonctions planes p-n (31, 32).
EP99969847A 1998-09-26 1999-09-08 Interrupteur bidirectionnel a semi-conducteur et circuit de commutation pour equipements alimentes par batterie Withdrawn EP1046194A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9820904 1998-09-26
GBGB9820904.2A GB9820904D0 (en) 1998-09-26 1998-09-26 Bi-directional semiconductor switch and switch circuit for battery-powered equipment
PCT/EP1999/006629 WO2000019540A1 (fr) 1998-09-26 1999-09-08 Interrupteur bidirectionnel a semi-conducteur et circuit de commutation pour equipements alimentes par batterie

Publications (1)

Publication Number Publication Date
EP1046194A1 true EP1046194A1 (fr) 2000-10-25

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EP99969847A Withdrawn EP1046194A1 (fr) 1998-09-26 1999-09-08 Interrupteur bidirectionnel a semi-conducteur et circuit de commutation pour equipements alimentes par batterie

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EP (1) EP1046194A1 (fr)
JP (1) JP2002526930A (fr)
GB (1) GB9820904D0 (fr)
WO (1) WO2000019540A1 (fr)

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US6777745B2 (en) * 2001-06-14 2004-08-17 General Semiconductor, Inc. Symmetric trench MOSFET device and method of making same
JP4961658B2 (ja) * 2003-02-17 2012-06-27 富士電機株式会社 双方向素子および半導体装置
JP5321657B2 (ja) * 2003-02-17 2013-10-23 富士電機株式会社 双方向素子および半導体装置
CN101567373B (zh) 2004-02-16 2011-04-13 富士电机系统株式会社 双方向元件及其制造方法
US9559198B2 (en) 2013-08-27 2017-01-31 Nxp Usa, Inc. Semiconductor device and method of manufacture therefor
US9837526B2 (en) 2014-12-08 2017-12-05 Nxp Usa, Inc. Semiconductor device wtih an interconnecting semiconductor electrode between first and second semiconductor electrodes and method of manufacture therefor
US9472662B2 (en) 2015-02-23 2016-10-18 Freescale Semiconductor, Inc. Bidirectional power transistor with shallow body trench
US10348295B2 (en) 2015-11-19 2019-07-09 Nxp Usa, Inc. Packaged unidirectional power transistor and control circuit therefore
US11004935B2 (en) 2016-03-22 2021-05-11 Wai Yee LIU Solid power semiconductor field effect transistor structure
EP3249815B1 (fr) 2016-05-23 2019-08-28 NXP USA, Inc. Agencement de circuit de mise hors tension rapide de dispositif de commutation bidirectionnel
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CN105915200B (zh) * 2015-02-23 2021-02-02 恩智浦美国有限公司 晶体管体区控制电路和集成电路

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GB9820904D0 (en) 1998-11-18
WO2000019540A1 (fr) 2000-04-06
JP2002526930A (ja) 2002-08-20

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