EP1045359A1 - Überwachungseinrichtung und Steuereinrichtung für Signallampen - Google Patents

Überwachungseinrichtung und Steuereinrichtung für Signallampen Download PDF

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Publication number
EP1045359A1
EP1045359A1 EP00201697A EP00201697A EP1045359A1 EP 1045359 A1 EP1045359 A1 EP 1045359A1 EP 00201697 A EP00201697 A EP 00201697A EP 00201697 A EP00201697 A EP 00201697A EP 1045359 A1 EP1045359 A1 EP 1045359A1
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EP
European Patent Office
Prior art keywords
signal
output
circuit
illumination
lights
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00201697A
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English (en)
French (fr)
Inventor
Yoshitaka c/o The Nippon Signal Co. Ltd. Jinno
Yoshiharu c/o The Nippon Signal Co. Ltd. Ozaki
Norihiro c/o The Nippon Signal Co. Ltd. Okada
Heisaku c/o The Nippon Signal Co. Ltd. Mazawa
Hidetoshi c/o The Nippon Signal Co. Ltd. Fujimoto
Junya c/o The Nippon Signal Co. Ltd. Toda
Koichi c/o The Nippon Signal Co. Ltd. Futsuhara
Norihiro c/o The Nippon Signal Co. Ltd. Asada
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Nippon Signal Co Ltd
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Nippon Signal Co Ltd
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Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority claimed from EP95916024A external-priority patent/EP0786752B1/de
Publication of EP1045359A1 publication Critical patent/EP1045359A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/097—Supervising of traffic control systems, e.g. by giving an alarm if two crossing streets have green light simultaneously

Definitions

  • the present invention relates to a monitoring apparatus for advising if an illumination condition of traffic signal lights is normal or abnormal, and a control apparatus for controlling the signal lights based on an advisory signal from the monitoring apparatus.
  • G lights green lights
  • monitoring for simultaneous illumination of the G lights for the respective directions of the intersecting roads has heretofore mainly involved using a hard logic, for example to detect the terminal voltage of the signal lights via a voltage transformer or the like.
  • the monitoring apparatus for traffic signal lights comprises: a sensor device for detecting an illumination condition of traffic signal lights; and a judgment device for generating an output of logic value 1 corresponding to a high energy condition indicating a normal condition of the signal lights when, based on an output from the sensor device, the number of illuminated or non illuminated signal lights is a predetermined number, and generating an output of logic value 0 corresponding to a low energy condition indicating an abnormal condition of the signal lights when not the predetermined number.
  • the construction may be such that the judgment device generates an output of logic value 1 when the number of illuminated signal lights is a predetermined number, and generates an output of logic value 0 indicating a signal light burn-out fault when not the predetermined number.
  • the construction may be such that the output from the judgment device is output via an on-delay circuit having a delay time which is longer than an illumination period of the signal lights, or via a self-hold circuit with the output from the judgment device as a reset input signal, and a signal light power source switch on signal as a trigger input signal, which self-holds the trigger input signal.
  • the construction may be such that the judgment device generates an output of logic value 1 when the number of non illuminated signal lights is a predetermined number, and generates an output of logic value 0 indicating a signal light simultaneous illumination fault where simultaneous illumination is not permitted, when not the predetermined number.
  • the construction may be such that the output from the judgment device is output via an on-delay circuit having a delay time which is longer than an illumination period of the signal lights, or a self-hold circuit with the output from the judgment device as a reset input signal, and a signal light power source switch on signal as a trigger input signal, which self-holds the trigger input signal.
  • the construction is such that an illumination condition of respective signal lights for respective road directions of a two way intersection where two roads intersect is detected using sensor devices which output a binary logic signal, generating an AC signal and outputting a logic value 1 when a signal light is illuminated, and not generating an AC signal and outputting a logic value 0 when the signal light is not illuminated, and there is provided a judgment device which, based on the output conditions from respective sensor devices for each of the respective signal lights, generates an output of logic value 1 corresponding to a high energy condition when the signal lights are normal, and generates an output of logic value 0 corresponding to a low energy condition at the time of a simultaneous illumination of the signal lights where simultaneous illumination is not permitted.
  • the construction may be such that the judgment device comprises; a first adding circuit for adding the logic signals of the respective sensor devices for detecting an illumination condition of respective green lights indicating permission to proceed in the respective road directions, and a first level detection circuit for level detecting the addition value from the first adding circuit, the construction being such that the first level detection circuit generates an output of logic value 1 when the addition value is 1, and generates an output of logic value 0 when the addition value is 2. Consequently it is possible to monitor for simultaneous illumination of the green lights.
  • the construction may be such that the judgment device comprises the first adding circuit and the first level detection circuit of claim 19, and further comprises: a second adding circuit for adding the logical signals of the respective sensor devices for detecting an illumination condition of respective red lights for the respective road directions; a second level detection circuit for level detecting the addition value from the second adding circuit; a third adding circuit for adding the logical signals of respective sensor devices for detecting an illumination condition of yellow lights for the respective road directions and an output signal from the second level detection circuit; and a first logical sum operation circuit for carrying out a logical sum operation on the addition value from the third adding circuit and an output from the first level detection circuit, and the logical sum operation output is made a judgment output. Consequently, if the signal lights are normal in the illumination period of the signal lights, an output of logic value 1 is continuously generated so that safety can be advised.
  • the construction may be such that the judgment device comprises the second adding circuit and the second level detection circuit of claim 20, and further comprises: a fourth adding circuit for adding the logical signals of respective sensor devices for detecting an illumination condition of green lights and yellow lights for the respective road directions; and a second logical sum operation circuit for carrying out a logical sum operation on the addition value from the fourth adding circuit and an output from the second level detection circuit, and the logical sum operation output is made a judgment output.
  • the judgment device comprises the second adding circuit and the second level detection circuit of claim 20, and further comprises: a fourth adding circuit for adding the logical signals of respective sensor devices for detecting an illumination condition of green lights and yellow lights for the respective road directions; and a second logical sum operation circuit for carrying out a logical sum operation on the addition value from the fourth adding circuit and an output from the second level detection circuit, and the logical sum operation output is made a judgment output.
  • the construction may also be such that the signal lights for the same road of a two way intersection where two roads intersect are made one group, and for each group the illumination condition of a permit signal light indicating permission to proceed is detected using a sensor device which outputs a binary logic signal, generating an AC signal and outputting a logic value of 1 when a signal light is not illuminated, and not generating an AC signal and outputting a logic value 0 when the signal light is illuminated, and there is provided a judgment device which, based on the output conditions from the sensor device for each group, generates an output of logic value 1 corresponding to a high energy condition indicating the signal lights are normal, when at least one group shows a non illuminated condition, and generates an output of logic value 0 corresponding to a low energy condition indicating a simultaneous illumination fault when neither group shows a non illuminated condition.
  • the construction may be such that the judgment device comprises a third logical sum operation circuit for carrying out a logical sum operation on the logical output from the respective sensor devices for each respective group, and the logical sum operation output is made a judgment output.
  • the judgment device may comprise: a fifth adding circuit for adding the logical outputs from the respective sensor devices for each respective group; and a third level detection circuit for level detecting the addition value from the fifth adding circuit, the construction being such that the third level detection circuit generates an output of logic value 1 when the addition value is 1 or more and generates an output of logic value 0 when the addition value is zero.
  • the construction may be such that the judgment device comprises: sixth and seventh adding circuits for respectively adding the logical outputs from the respective sensor devices for each respective group; fourth and fifth level detection circuits for respectively level detecting the addition values from the sixth and seventh adding circuits and outputting a logic value 1 when the addition values are respectively a maximum; and a fourth logical sum operation circuit for carrying out a logical sum operation on both outputs from the fourth level detection circuit and the fifth level detection circuit, and the logical sum operation output is made a judgment output.
  • the judgment device may comprise: eight and ninth adding circuits for respectively adding the logical outputs from the respective sensor devices for each respective group; a fifth logical sum operation circuit for carrying out a logical sum operation on the addition values from the eighth and ninth adding circuits; and a sixth level detection circuit for level detecting the logical sum output from the fifth logical sum operation circuit and outputting a logic value 1 when the logical sum output is a logic value of 2 or more.
  • the sensor device may be a current sensor provided for each permit signal light, with a power supply line for the permit signal light wound around a saturable magnetic core such that an excitation signal for the saturable magnetic core input from a high frequency signal generator is received on an output side at a high level at the time of no power to the power supply line, and is received on the output side at a low level at the time of power supply.
  • the sensor device may be a voltage sensor provided for each permit signal light, which detects a terminal voltage of an illumination switch circuit disposed in a power supply line for the permit signal light.
  • the construction of the voltage sensor may basically involve a series circuit of a first photocoupler for switching an AC current from an illumination power source using a high frequency signal from a high frequency signal generator, and a second photocoupler for receiving an AC signal from the switched illumination power source, connected in parallel across the terminals of a switching circuit for signal light illumination which is connected in series with the signal light.
  • a current sensor is used for the sensor device, with all power supply lines for the permit signal lights of the same group wound around one saturable magnetic core such that an excitation signal for the saturable magnetic core input from a high frequency signal generator is received on an output side at a high level when no current flows in all the power supply lines, and is received on the output side at a low level when a current flows in at least one power supply line, then the number of current sensors can be reduced.
  • the construction may be such that in the case of a voltage sensor for the sensor device, then basically this involves a series circuit of a first photocoupler for switching an AC current from an illumination power source using a high frequency signal from a high frequency signal generator, and a second photocoupler for receiving an AC signal from the illumination power source switched by the first photocoupler, connected in parallel across the terminals of an illumination switching circuit for one permit signal light, together with a plurality of series circuits constituted by photocouplers, each of which connected in parallel across the terminals of an illumination switching circuit for another permit signal light, with the second photocoupler and the series circuits constituted by photocouplers cascade connected, and an output from the final stage series circuit made the sensor output.
  • the signal lights for the same road are made one group, and for each group, the illumination condition of a permit signal light indicating permission to proceed is detected using a sensor device which outputs a binary logic signal, generating an AC signal and outputting a logic value of 1 when a signal light is not illuminated, and not generating an AC signal and outputting a logic value 0 when the signal light is illuminated, and there is provided: tenth, eleventh and twelfth adding circuits for respectively adding the logical signals from the sensor devices for each group: seventh, eight and ninth level detection circuits for respectively level detecting the addition values from the respective adding circuits and generating an output of logic value 1 when the respective addition values are a maximum; a thirteenth adding circuit for adding the logical outputs from the respective level detection circuits; and a tenth level detection circuit for outputting a logic value 1 indicating normal signal lights when the addition value of the thirteenth adding circuit
  • the illumination condition of the respective permit signal lights indicating permission to proceed is respectively detected using sensor devices which output a binary logic signal, generating an AC signal and outputting a logic value 1 when a signal light is not illuminated, and not generating an AC signal and outputting a logic value 0 when the signal light is illuminated, and there is provided: a fourteenth adding circuit for adding the sensor outputs corresponding to the respective permit signal lights for the first direction and second direction roads; a fifteenth adding circuit for adding the sensor outputs corresponding to the respective permit signal lights for the second direction and third direction roads; a sixteenth adding circuit for adding the sensor outputs corresponding to the respective permit signal lights for the third direction and first direction roads; and an eleventh level detection circuit for generating an output of logic value 1 indicating normal signal lights when the addition value of the respective adding circuits is 6, and generating an output of logic value 0 indicating a simultaneous illumination fault when the addition value is 5 or less.
  • the construction may comprise: a signal light monitoring circuit provided with, a sensor device for detecting an illumination condition of respective signal lights, and a judgment device for generating an output of logic value 1 corresponding to a high energy condition indicating a normal condition of the signal lights when, based on an output from the sensor device, the number of illuminated or non illuminated signal lights is a predetermined number, and generating an output of logic value 0 corresponding to a low energy condition indicating an abnormal condition of the signal lights when the number is not the predetermined number; and a signal light power supply control circuit which supplies power to the signal lights when an output of logic value 1 is generated from the signal light monitoring circuit, and which stops power supply to the signal lights when an output of logic value 0 is generated.
  • the illumination control for the signal lights can be carried out in a fail-safe manner.
  • the signal light monitoring circuit may comprise: a sensor device constructed so as to generate an AC signal at the time of non illumination of a signal light, and not to generate an AC signal at the time of illumination; and a judgment device which generates an output of logic value 1 when the number of non illumination outputs from the sensor device is a predetermined number, and generates an output of logic value 0 indicating a signal light simultaneous illumination fault where simultaneous illumination is not permitted, when not the predetermined number.
  • the signal light power supply control circuit may have an electromagnetic relay having relay contact points disposed in series in the power supply lines for the respective signal lights, the construction being such that the electromagnetic relay is placed in a non excited condition with the contact points open, based on an output of logic value 0 indicating simultaneous illumination of the signal light monitoring circuit.
  • the signal light power supply control circuit may incorporate: a first self-hold circuit with a signal light power source switch on signal as a trigger input signal, and an output from the signal light monitoring circuit as a reset input signal, which self-holds the trigger input signal, the construction being such that the electromagnetic relay is excited and the contact points thus closed with an output of logic value 1 from the self-hold circuit when a reset input signal of logic value 1 indicating normal signal lighting from the monitoring circuit, and a trigger input signal of logic value 1 due to the power source switch on signal are input together.
  • the construction may be such that the signal light power supply control circuit incorporates: a signal light flash command circuit which outputs to an illumination control circuit, a flash command for a yellow light and a red light for intersecting roads when an output of logic value 0 indicating simultaneous illumination of the signal lights is generated from the signal light monitoring circuit so that the output from the first self-hold circuit is cancelled; a flash monitoring circuit for monitoring if a flash operation of the yellow light and red light is normal, based on the flash command from the signal light flash command circuit; and an electromagnetic relay control circuit which de-energizes the electromagnetic relay to open the contact points and stop the signal light power supply, based on an output from the flash monitoring circuit when the flash operation for the yellow light and the red light is abnormal.
  • a signal light flash command circuit which outputs to an illumination control circuit, a flash command for a yellow light and a red light for intersecting roads when an output of logic value 0 indicating simultaneous illumination of the signal lights is generated from the signal light monitoring circuit so that the output from the first self-hold circuit is cancelled
  • the electromagnetic relay control circuit may comprise: a second self-hold circuit with a signal for a fall in the output of logic value 1 from the signal light monitoring circuit as a trigger input signal, and a monitoring output from the flash monitoring circuit as a reset input signal, the construction being such that when the flash operation for the yellow light and the red light is normal at the time of signal light simultaneous illumination, the trigger input signal and the reset input signal both become a logic value 1 so that the excitation of the electromagnetic relay is maintained by means of an output from the second self-hold circuit.
  • the construction may comprise: respective saturable magnetic cores with respective signal light power supply lines provided for each of a plurality of signal lights connected in parallel with each other to a common power supply line, wound thereon as primary windings; a transformer with second windings for impedance detection wound on the respective saturable magnetic cores and connected in series with each other, acting as load for a secondary winding thereof and which receives a high frequency signal from a high frequency signal generator in a primary winding thereof; and a level detection circuit which generates an output of logic value 1 indicating normal signal lights when an output signal level of the transformer is equal to or above a predetermined level as a result of an output signal change due to a change in impedance for the transformer, and generates an output of logic value 0 indicating a signal light burn-out fault when lower than the predetermined level.
  • the monitoring apparatus may be one wherein an illumination condition of respective signal lights of an intersection where a plurality of roads intersect is detected using sensor devices which generate an AC signal at the time of non illumination of a signal light and which do not generate an AC signal at the time of illumination of the signal light, and wherein an AC signal level at the time of non illumination from a sensor device for detecting the illumination condition of a vehicle green light and a pedestrian green light, is made different from an AC signal level at the time of non illumination from a sensor device for detecting an illumination condition of a yellow light, and wherein there is provided a judgment device which, based on the outputs from the respective sensor devices, distinguishes and warns between respective simultaneous illumination faults of the vehicle green light pairs, and the vehicle green lights and the pedestrian green lights, and respective simultaneous illumination faults of the vehicle green lights and the yellow lights, and the pedestrian green lights and the yellow lights.
  • the invention provides a monitoring apparatus for traffic signal lights for monitoring for simultaneous illumination faults in traffic signal lights where illumination is controlled with the green, red and yellow signal lights of respective signal units for an intersection where a plurality of roads intersect, connected in parallel with one common power supply line, the construction being such that current sensors are used, each with the power supply line for the signal light wound on a saturable magnetic core such that an excitation signal for the saturable magnetic core input from a high frequency signal generator is received on an output side at a high level at the time of no power to the power supply line, and is received on the output side at a low level at the time of power supply, and the common power supply lines for the signal units and the red light power supply lines are wound in opposite directions to each other on the saturable magnetic cores of the respective current sensors provided for each signal unit for the respective road directions, and the AC signal level of the respective current sensors is added by an adding circuit, and the added signal level is detected by a level detection circuit, the level detection circuit generating an output of logic value 1 indicating normal when the
  • the construction may be such that the illumination condition of respective permit signal lights for permitting traffic to proceed in the respective road directions is detected using sensor devices which generate an AC signal at the time of non illumination of the signal lights and which do not generate an AC signal at the time of illumination, and there is provided: a first electromagnetic relay which is excited by an output signal from a first sensor device for detecting an illumination condition of a permit signal light on one road; and a second electromagnetic relay which is excited by an output signal from a second sensor device for detecting an illumination condition of a permit signal light on the other road, and wherein relay contact points for closing a circuit at the time of excitation of the second electromagnetic relay are disposed in series in a power supply line for the permit signal light for the one road, and relay contact points for closing a circuit at the time of excitation of the first electromagnetic relay are disposed in series in a power supply line for the permit signal light for the other road.
  • the illumination current for the green light for the other road direction can be shut off. Moreover, since a time difference exists between the reciprocal illuminations of the green lights, then the illumination current for the signal lights is not shut off by the on and off switching of the electromagnetic relay contact points.
  • FIGS. 1 (a) ⁇ (d) illustrate structural examples of a voltage sensor.
  • FIGS. 1 (a) and (b) illustrate examples using a transformer T 1
  • FIGS. 1 (c) and (d) illustrate examples using a photocoupler comprising a light emitting element PT and a light receiving element PD.
  • a voltage sensor enclosed by the dashed line in the figures is connected across the terminals of an illumination switch SW for a signal light L
  • an output signal OUT from the sensor is generated at a high level when the switch SW is off.
  • FIGS. 2 (a) and (b) illustrate structural examples of a current sensor.
  • a transformer T 2 is a current transformer.
  • a power supply line for a signal light L is wound on a core Cor of the transformer T 2 as a primary winding N a1 , and an AC output signal OUT1 is generated in a secondary winding N a2 wound on the core Cor, when a switch SW is switched on so that a current flows in the power supply line.
  • FIG. 2. (b) the presence of a power supply current is produced as a modulation signal from a high frequency signal generator SG (referred to hereunder simply as a signal generator).
  • a power supply line is wound on a ring shape saturable magnetic core Cor of a transformer T 3 as a winding Nb 1 , and a current (saturable magnetic core excitation signal) is supplied to a winding Nb 3 from the signal generator SG via a resistor R 3 .
  • a current flows in the power supply line for the signal light L
  • the saturable magnetic core Cor becomes saturated due to the winding Nb 1 .
  • a high frequency signal from the winding Nb 3 is not transmitted to an output winding Nb 2 via the saturable magnetic core Cor. That is to say, when the switch SW is on, the output signal OUT2 becomes a low level high frequency signal, while when the switch SW is off, the output signal OUT2 becomes a high level high frequency signal. In particular, if the power supply current is large, then when the switch SW is on, the output signal OUT2 becomes an extremely low level. In the following discussion this is treated as an approximately zero level condition.
  • FIG. 2 (c) illustrates processing for the case where a large change in the output signals OUT1, OUT2, of FIG. 2 (b) can not be obtained by on and off switching with the switch SW.
  • a voltage doubler rectifying circuit REC and a fail-safe window comparator WC both to be described later
  • FIG. 4 (a) shows a structural example of a signal generator SG to prevent the occurrence of this intermittent high frequency signal in the output signal OUT2.
  • CMOS inverters Q 1s . Q 2s , resistors R s1 , R s2 and a capacitor C S constitute an oscillator OSC.
  • a high frequency output signal from the oscillator OSC is supplied to the winding Nb 3 as the output from the signal generator SG.
  • the output signal from the oscillator OSC is amplified by a known amplifier.
  • Power for the oscillator OSC is supplied from a full wave rectifying circuit rec which is supplied from a signal light power source (AC power source) via a transformer T S .
  • a transistor Q S , a zener diode ZD, and a resistor R S constitute a known constant voltage circuit which limits the upper limit voltage of the output from the full wave rectifying circuit rec.
  • the oscillator OSC oscillates when the output from the constant voltage circuit is equal to or greater than a predetermined level (normally a low value of a few volts at which the CMOS can operate). Since the power source output to the signal generator SG is synchronized with the power source of the power supply line for the signal lights, then the output signal from the signal generator SG is produced as shown in FIG. 4 (b) relative to the change in the power supply current, with an output signal from the signal generator SG not produced close to the zero point of the power supply current. Therefore, the intermittent high frequency signal shown in FIG. 3 does not occur.
  • AC input signals can be added using a voltage doubler rectifying circuit.
  • the portion enclosed by the dashed line in FIG. 5 indicates a voltage doubler rectifying circuit REC, comprising a coupling capacitor C 1 , a smoothing capacitor C 2 , a clamping diode D 1 , and a rectifying diode D 2 , which outputs a DC output signal e out clamped at a power source potential E.
  • An input signal e in is switched at a level of the power source potential E by a transistor Q.
  • a resistor R has a small value. In the case where a disconnection fault occurs in the capacitor C 1 or C 2 , or a short circuit fault occurs in the diode D 1 or D 2 , then a DC output signal is not produced.
  • the level of the output signal e out is the level of the power source potential E or a lower level. If a disconnection fault occurs in the diode D 1 , the electrical discharge route for the charge stored in the capacitor C 1 is lost, and hence the input signal e in is not transmitted to the output side via the capacitor C 1 . If a short circuit fault occurs in the diode D 2 , then the input signal e in is short circuited by the capacitor C 2 so that the DC output signal e out is not produced. If a disconnection fault occurs in the capacitor C2, then the output signal e out becomes an AC signal (if a four terminal capacitor is used for the capacitor C 2 , then the output signal e out becomes zero).
  • the voltage doubler rectifying circuit REC of FIG. 5 has the characteristic that if a single fault occurs in the constituent elements of the circuit, a DC output signal of a higher level than the power source potential E never occurs. Moreover it has the characteristic that when the input signal e in is not input, an output signal e out of a higher potential than the power source potential E is never produced even with a circuit fault.
  • the output signal can be treated as the following binary logical output signal x.
  • FIG. 6 (a) and (b) are examples of adding circuits made up using the voltage doubler rectifying circuit of FIG. 5.
  • the output signal for input signal e 2 is clamped and added to the rectified output signal for the input signal e 1
  • the output signal for the input signal e 3 is clamped and added to the added value of the input signals e 1 and e 2
  • the output signal for the input signal e n is clamped and added to the added value of input signals e 1 ⁇ e n-1 . Consequently, the output signal e out is output as the added value of the input signals e 1 ⁇ e n .
  • FIG. 6 (b) shows the adding circuit for where the input signals e 1 ⁇ e n are synchronized, with e 1 , e 3 , e 5 , whereas and e 2 , e 4 , e 6 , « having opposite phases to each other.
  • the input signals e 1 , e 2 , e 3 , e 4 and e 5 are input, since when the input signals e 1 , e 3 are input at a positive voltage, the input signals e 2 , e 4 are input at a negative voltage, then the charge for the input signals e 1 , e 3 is stored in the capacitors C 12 , C 14 via the respective capacitors C 11 , C 13 .
  • the clamping diodes D 12 ⁇ D 1n for the input signals e 2 ⁇ e n of FIG. 6 (b) also perform the role of rectifying diodes (diodes D 21 ⁇ D 2n of FIG. 6(a)) for the immediately preceding respective input signals e 1 ⁇ e n-1
  • the coupling capacitors C 12 ⁇ C 1n for the input signals e 2 ⁇ e n also perform the role of smoothing capacitors (capacitors C 22 ⁇ C 2n in FIG . 6 (a)) for the immediately preceding respective input signals e 1 ⁇ e n-1
  • the diode D 2n is the rectifying diode for the input signal e n
  • the capacitor C 2n is the smoothing capacitor for the input signal e n .
  • the construction may be as shown in FIG. 7 using the current sensor of FIG. 2 (b).
  • FIG. 7 shows the case where the signal level for the secondary winding Nb 2 is small, and hence an amplifier AMP is provided before the voltage doubler rectifying circuit REC shown in FIG. 2(c).
  • FIG. 8 shows a structural example of an AC amplifier for use as the amplifier AMP.
  • a capacitor C 193 corresponds to the coupling capacitor (in FIG. 5, the capacitor C1) for the subsequent voltage doubler rectifying circuit REC.
  • Such a fail-safe AC amplifier is known for example from prior International Patent Publication No. WO 94/23303.
  • the signal light currents i 1 , i 2 , i 3 must be equal.
  • the signal lights deteriorate with age so that the currents i 1 , i 2 , i 3 are reduced. Consequently, this addition method is limited to use in special cases where the signal lights are comparatively new and all of the signal lights are replaced at the same time, or where the threshold values of the window comparator are adjusted periodically.
  • a device which can be used for the fail-safe threshold value logical operation is the fail-safe window comparator/AND gate.
  • This device is known for example from U.S. Pat. No. 4,661,880, U.S. Pat. No. 4,667,184, U.S. Pat. No. 5,027,114, and from IEICE Trans. Electron, Vol. E76-C, No. 3, March 1993, pp. 419-427.
  • FIG. 9 shows a structural example of this device.
  • a feedback circuit comprising transistors Q 1 ⁇ Q 7 constitutes an oscillator (referred to as an operational oscillator), transistors Q 8 , Q 9 constitute an amplifier coupled by a diode D, while diodes D 10 , D 20 and capacitors C 10 , C 20 constitute the beforementioned voltage doubler rectifying circuit for superimposing on the power source potential E.
  • an operational oscillator referred to as an operational oscillator
  • transistors Q 8 , Q 9 constitute an amplifier coupled by a diode D
  • diodes D 10 , D 20 and capacitors C 10 , C 20 constitute the beforementioned voltage doubler rectifying circuit for superimposing on the power source potential E.
  • circuit of FIG. 9 gives a fail-safe window comparator / AND gate, which will not produce an output signal when there is no input signal.
  • the output signal from the output terminal OUT is fed back for example to the input terminal 2, then this gives a fail-safe self-hold circuit with the input terminal 1 as a reset input terminal and the input terminal 2 as a trigger input terminal.
  • a self-hold circuit using such a window comparator is known for example from U.S. Pat. No. 5,207,114.
  • FIG. 11 illustrates a threshold value operation circuit which uses an adding circuit and a two input fail-safe window comparator.
  • the logical product output Y is;
  • the upper limit threshold value V H is set between the logical level for and the logical level for while the lower limit threshold value V L is set between the logical level for and the logical level for Provided that k and h are positive integers of 1, 2, 3 .... n.
  • FIG. 13 shows an example of this construction.
  • the logical operation using the adding circuit and the threshold value operation circuit shown in FIG. 12 can be replaced by a binary logical operation, except for the operation having a window.
  • Detection types can thus involve two types; one being referred to as a danger detection type which involves detecting a dangerous condition when this arises, and handling this in some way, and the other being referred to as a safety verifying type which involves first verifying safety and then executing practices involving danger (for example before crossing an intersection, first verifying that the abovementioned two signal lights G 1 , G 2 are not illuminated simultaneously and that only one is on).
  • a danger detection type which involves detecting a dangerous condition when this arises, and handling this in some way
  • a safety verifying type which involves first verifying safety and then executing practices involving danger (for example before crossing an intersection, first verifying that the abovementioned two signal lights G 1 , G 2 are not illuminated simultaneously and that only one is on).
  • FIG. 14 (a) where a provisional detection for danger is carried out (G 1 and G 2 illuminated simultaneously) and if there is no danger, safety is indicated.
  • This construction is based for example as shown in FIG. 14 (b), on verification that the signal lights G 1 , G 2 at an intersection are not illuminated simultaneously.
  • g 1 and g 2 show a logic value of 1 when the respective signal lights G 1 and G 2 are illuminated, and a logic value of 0 when not illuminated.
  • these are signals obtained by rectifying in a voltage doubler rectifying circuit, the output signal OUT1 from the current sensor in FIG. 2 (a) or in FIG. 2 (b) (to be described later).
  • letter N indicates a NOT circuit.
  • Letter y indicates a binary signal, being a logic value of 1 for safety and a logic value of 0 for danger.
  • the implication with FIG. 14 (a) is that danger is detected (G 1 , G 2 illuminated simultaneously), and safety is then shown as the negative of this.
  • FIG. 15 (a) shows a situation for where safety is sampled directly by a sensor.
  • FIG. 14 (b) and FIG. 15 (b) illustrate a logic equivalent to that of the De Morgan theorem.
  • the signal light illumination condition is detected using the current sensor of FIG. 2 (b).
  • the sensor output signal is level detected to be made binary using a voltage doubler rectifying circuit and a lower limit threshold value of a window comparator (one where in the upper limit threshold value is set sufficiently high so as to be unrelated) as shown in FIG. 2 (c).
  • a detection signal of logic value 1 for when an illumination current flows for example in the signal light 1G and of logic value 0 for when this does not flow is represented by a logical variable x g1
  • a detection signal of logic value 1 for when the illumination current does not flow and of logic value 0 for when the current does flow is represented by a logical variable x g1 .
  • a proviso is that the output signal from the window comparator WC is an oscillating output signal (AC signal), and the amplitudes are the same magnitude.
  • g 1 in x g1 and x g1 indicate the respective signal lights G 1 .
  • FIG. 17 is a schematic diagram of a first embodiment of a simultaneous illumination detection circuit according to the present invention.
  • the first embodiment is one which detects simultaneous illumination of the G lights indicating permission to proceed for first and second directions at a two way intersection as shown in FIG. 18 (b) (the case where there are two intersecting roads).
  • REC1 and REC2 are the voltage doubler rectifying circuits of FIG. 5, and constitute a first adding circuit for adding an illumination signal x g1 for the green light 1G for the first direction, and an illumination signal x g2 for the green light 2G for the second direction.
  • the addition output is level detected using the beforementioned fail-safe two input window comparator WC1 serving as a first level detection circuit.
  • FIG. 18 (a) the illumination sequences for the signal lights of the two way intersection shown in FIG. 18 (b) are represented on time axes, the full lines being the illumination intervals and the dashed lines being the non illumination intervals.
  • the horizontal axis numerals show one period for signal light illumination in 10 equal increments. Hence in the case where the period for the signal light illumination is 100 seconds, the horizontal axis becomes 10 secs / div.
  • Symbols 1G, 1Y, and 1R indicate the respective signal lights namely; green (G), yellow (Y), and red (R) for a signal unit S1 for a first direction of the intersection, while symbols 2G, 2Y, and 2R indicate the respective signal lights namely; green (G), yellow (Y), and red (R) for a signal unit S2 for a second direction of the intersection.
  • the green light 1G for the first direction is illuminated over intervals 1 through 3
  • the yellow light 1Y is illuminated over interval 4
  • the red light 1R is illuminated over the other intervals (intervals 5 through 10).
  • the green light 2G for the second direction is illuminated over intervals 6 through 8
  • the yellow light 2Y is illuminated over interval 9
  • the red light 2R is illuminated over the other intervals (intervals 1 through 5, and 10).
  • the lower limit threshold value V L shown in FIG. 19 is a threshold value for judging this condition, and is set between a logical level of logic value 1 and a logical level of logic value 0 relative to the sum of the rectified output signals for the output signals x g1 and x g2 .
  • x g1 + x g2 has the meaning of the sum of the rectified output signals for the AC input signals x g1 and x g2 .
  • FIG. 20 illustrates a second embodiment of the present invention, being a simultaneous illumination detection circuit for the green lights 1G and 2G, which compensates for this defect. Components the same as for the first embodiment are indicated by the same symbols.
  • x y1 denotes an output signal from a sensor which produces an AC signal of logic value 1 when a yellow light 1Y for one direction is illuminated, and gives a logic value 0 for no AC signal when the yellow light 1Y is not illuminated.
  • Voltage doubler rectifying circuits REC6 and REC7 constitute a second adding circuit
  • a window constitutes a window
  • comparator WC2 constitutes a second level detection circuit
  • voltage doubler rectifying circuits REC4, REC5, and REC8 constitute a third adding circuit
  • a first logical sum operation circuit is constituted by a wired OR connection.
  • Signals x r1 and x r2 are added by the second adding circuit and then level detected by the window comparator WC2.
  • the signal Y3 and the illumination signals x y1 and x y2 for the yellow lights 1Y and 2Y are added by the respective voltage doubler rectifying circuits REC8, REC 4 and REC 5.
  • the signal Y DC2 generated as the sum of x y1 and x y2 and the output signal Y 3 from the window comparator WC2 is always 1, except for during the illumination interval for the green lights 1G and 2G. Since the rectified signal Y DC1 for the output signal Y1 from the window comparator WC1 becomes a logic value 1 during the illumination interval for the green lights 1G and 2G as shown in FIG.
  • FIG. 21 is a circuit illustrating a third embodiment of a simultaneous illumination detection circuit, being a circuit which detects not only simultaneous illumination of the green lights 1G and 2G but also simultaneous illumination between the signal lights 1G and 1Y, and 2G and 2Y. Components the same as for the second embodiment are indicated by the same symbols.
  • the construction is such that the output signals x g1 , x g2 , x y1 and x y2 from the current sensors are added.
  • Voltage doubler rectifying circuits REC1, REC2, REC4 and REC5 constitute a fourth adding circuit.
  • a second logical sum operation circuit is constituted by a wired OR connection.
  • the addition output ( x g1 + x g2 + x y1 + x y2 ) is always a logical value 1. Furthermore, if any two of the four signal lights are simultaneously illuminated, then the addition output become a logic value 2, while if three are simultaneously illuminated, this becomes a logic value 3, and if four are simultaneously illuminated, this becomes a logic value 4.
  • the upper limit threshold value V H of the window comparator WC1 is set to a level between the logical levels for logic values 1 and 2
  • the lower limit threshold value V L is set to a level between the logical levels for logic values 1 and 0,
  • the output signal Y 1 is generated as follows.
  • the voltage doubler rectifying circuits REC as mentioned before do not erroneously produce an output signal with a fault while there is no input signal.
  • the window comparator WC also, a similar situation with a fault does not arise. Consequently, the output signals from the respective circuits of FIG. 20 and FIG. 21, which are based on the output signals from the adding circuits, err towards a drop in the logic value at the time of a fault.
  • a fault occurs in the sensors for generating the signals x g1 , x g2 , x y1 , x y2 , x r1 and x r2 , or a fault occurs in the voltage doubler rectifying circuits for rectifying these signals, then at the time when the addition values x g1 + x g2 , or x y1 + x y2 , or x g1 + x g2 + x y1 + x y2 , or x r1 + x r2 should be a logic value 1, a logic value 0 is produced.
  • FIG. 22 shows a circuit example for a simultaneous illumination detection circuit of the safety verifying type.
  • an input signal x g1 is the signal obtained from the output signal OUT2 of the current sensor of FIG. 2 (b). As shown in FIG. 16, this is the AC output signal x g1 obtained via the voltage doubler rectifying circuit and the window comparator.
  • the construction is such that the input signals x g1 and x g2 are rectified by means of voltage doubler rectifying circuits REC9 and REC10, and subjected to a logical sum operation in a logical sum operation circuit constituted by a wired OR connection (corresponding to a third logical sum operation circuit).
  • FIG. 23 shows a simultaneous illumination detection circuit with a construction wherein both input signals x g1 and x g2 are added by a fifth adding circuit comprising voltage doubler rectifying circuits REC11 and REC12, and the addition output is level detected by a window comparator WC3 serving as a third level detection circuit to thereby obtain an output signal Y4.
  • FIG. 24 shows the current sensor output signals x g1 and x g2 for the green lights 1G and 2G, and the logical values for the rectified output signal addition value x g1 + x g2 for these two input signals.
  • the output signal Y 4 is always a logic value 1.
  • the output signal Y 4 becomes a logic value 0 (the condition where an AC signal is not output).
  • FIG. 25 and FIG. 26 show respective embodiments of simultaneous illumination detection circuits of the safety verifying type, which takes into consideration simultaneous illumination between the yellow lights Y, in addition to simultaneous illumination of the green lights G.
  • the section enclosed by dashed line A and the section enclosed by dashed line B have respective input signals x g1 and x y1 for section A, and x g2 and x y2 for section B, with circuit constructions the same as for FIG. 23.
  • the window comparators WC4 and WC5 serving as fourth and fifth level detection circuits, when the input level is logic value 2, an output signal of logic value 1 is produced, while when the input level is logic value 1 or logic value 0, an output signal of logic value 0 results.
  • the construction is such that after respective addition by voltage doubler rectifying circuits REC19 and REC20 constituting an eighth adding circuit, and voltage doubler rectifying circuits REC21 and REC22 constituting a ninth adding circuit, a logical sum operation is first carried out by a wired OR connection serving as a fifth logical sum operation circuit, after which the level is detected by a window comparator WC6 serving as a sixth level detection circuit.
  • AC output signals Y 5 and Y 6 from the window comparators WC4 and WC5 of FIG. 25 are represented by the following equations.
  • the output signals from the window comparators WC4, WC5 are rectified by the respective voltage doubler rectifying circuits REC15, REC18 and output as a logical sum operation output signal Y DC5 /Y DC6 by means of a wired OR connection serving as a fourth logical sum operation circuit.
  • the voltage doubler rectifying circuits REC13, REC14 constitute a sixth adding circuit, while the voltage doubler rectifying circuits REC16, REC17 constitute a seventh adding circuit.
  • FIG. 27 is an operational time chart for the circuit of FIG. 25, with the illumination relationship of FIG. 18.
  • the threshold values V L and V H for the window comparators WC4 and WC5 as shown in FIG. 27, the upper limit threshold value V H is set to a level higher than the logical level of logic value 2 for the sum of the respective input signals, while the lower limit threshold value V L is set between the logical levels of logic value 2 and logic value 1 for the sum of the respective input signals.
  • section A and section B that is, whether or not there is signal light illumination for the first and second directions, is carried out by identical circuit constructions, with the upper and lower limit threshold values for the window comparators WC4 and WC5 at the same levels.
  • the construction can therefore be such that the addition of the two input signals, that is, the logical sum operation of x g1 + x y1 and x g2 + x y2 , is carried out first as with the embodiment of FIG. 26, after which level detection is carried out with the window comparator WC6.
  • REC19 through REC22 are voltage doubler rectifying circuits.
  • FIG. 28 is an example of a simultaneous illumination detection circuit for an intersection provided with signals 1PG, 2PG for indicating permission to proceed for pedestrians, as shown in FIG. 29 (b).
  • x pg1 indicates a non illumination signal for a pedestrian signal light 1PG.
  • REC23 through REC28 indicate voltage doubler rectifying circuits, while WC7 indicates a window comparator.
  • the construction is such that six input signals are separated in a similar manner to FIG. 26, into x pg1 , x g1 and x y1 (non illumination signals related to first direction signal lights 1PG, 1G, 1Y) and x pg2 , x g2 and x y2 (non illumination signals related to second direction signal lights 2PG, 2G, 2Y), which are then respectively added.
  • FIG. 29 (a) shows the illumination relationship for the respective signal lights at this intersection, with the time axes the same as in FIG. 18 (a) divided into ten equal increments within one period for the first direction signal lights 1G, 1Y, 1PG, and the second direction signal lights 2G, 2Y, 2PG, the illumination intervals being shown by the full lines.
  • the dashed lines show the non illumination intervals.
  • the non illumination signals x g1 , x y1 and x pg1 , and x g2 , x y2 and x pg2 for the respective signal lights are respectively generated in the dashed line intervals as logic value 1.
  • the signal lights 1PR, 1R and 2PR, 2R are respectively the red lights for pedestrians and traffic in the first direction, and the red lights for pedestrians and traffic in the second direction.
  • FIG. 30 shows the logic values for the addition results of the input signals in the respective first direction and second direction.
  • the intervals 5 through 10 for the first direction, enclosed by the dashed line, and the intervals 1 through 5 and 10 for the second direction, enclosed by the dashed line, are the intervals where the addition results show a logic value 3. Since the intervals 1 through 4 are the intervals where permission to proceed in the first direction is given to pedestrians as well as to traffic, then here the addition value x pg2 + x g2 + x y2 for the second direction input signals must be a logic value 3.
  • the intervals 6 through 9 are the intervals where permission to proceed in the second direction is given to pedestrians as well as to traffic, then here the addition value x pg1 + x g1 + x y1 for the first direction input signals must be a logic value 3.
  • the intervals 5 and 10 are intervals wherein none of the above signals are generated for the first direction or the second direction. Consequently, the logical sum of the sum of the input signals for both directions in one period, that is ( x pg1 + x g1 + x y1 ) ⁇ ( x pg2 + x g2 + x y2 ) , is continuously at a logic value 3 provided that the signal lights are operating normally.
  • the upper limit threshold value V H is set to a higher logical level than logic value 3 while the lower limit threshold value V L is set between a logical level of logic value 3 and a logical level of logic value 2.
  • the output signal Y 8 from the window comparator WC7 is a logic value 1
  • the output signal Y 8 becomes a logic value 0.
  • FIG. 31 shows an embodiment for the case where the second direction pedestrian signal light 2PG is not provided.
  • the level detection for the addition values x pg1 + x g1 + x y1 for the input signals of the first direction is carried out with a window comparator WC8, and the level detection for the addition values x g2 + x y2 for the input signals of the second direction is carried out with a window comparator WC9, and the logical sum output signal for the rectified output signals Y DC9 and Y DC10 for both window comparators WC8 and WC9 is made the detection signal for no simultaneous illumination of the signal lights.
  • the window comparator WC8 has the same upper and lower limit threshold values as the window comparator WC7 of FIG. 28, while the window comparator WC9 has the same upper and lower limit threshold values as the window comparator WC5 of FIG. 25.
  • the plurality of travel permit signal lights (1PG, 1G, 1Y, and 2PG, 2G, 2Y) for the first direction and the second direction are separated into two groups which are never illuminated simultaneously, and the logical sum operation output signal for the signals indicating non illumination for both groups is made a high level, that is to say when a high logical value is indicated, illumination conditions are normal.
  • the logical sum operation output signal becomes a low level, that is to say, when a low logical value is indicated conditions are not normal.
  • the signal lights being investigated are 1G, 1Y, 1PG and 2G, 2Y, 2PG and the maximum value is 3, while with FIG. 31, the signal lights being investigated are 1G, 1Y, 1PG and 2G, 2Y and the maximum value in the first direction is 3 and in the second direction is 2.
  • the signal lights are illuminated for a direction to give traffic (including pedestrians) permission to proceed, and so that there is no conflict between the first direction and the second direction.
  • a current sensor may be used as in FIG. 7.
  • a signal generator SG is one based on the construction of FIG. 4.
  • the signal from the winding N b3 is not transmitted to the winding N b2 so that the output level from the voltage doubler rectifying circuit REC36 drops.
  • the output signal Y 11 for the winding N b2 always drops.
  • the window comparator WC10 in FIG. 32 serves the role of a fail-safe window comparator for level detecting whether or not an output voltage is generated in the voltage doubler rectifying circuit REC36.
  • FIG. 33 shows a structural example of a simultaneous illumination detection circuit for a first direction and second direction corresponding to FIG. 28, for the case with such highly sensitive current sensors.
  • the case of all non illumination signals for the signal lights 1PG, 1G, 1Y in FIG. 28 is generated as an output signal X 11 (voltage signal) from the voltage doubler rectifying circuit REC37, while the case of all non illumination signals for the signal lights 2PG, 2G, 2Y is generated as an output signal X 21 (voltage signal) from the voltage doubler rectifying circuit REC38.
  • the construction may be such that the rectified outputs for a non illumination signal x a1 for the arrow light 1A, and a non illumination signal x a2 for the arrow light 2A respectively obtained from current sensors via voltage doubler rectifying circuits, are appended to the respective groups and added.
  • the logical sum of the rectified output signals for the first direction and the second direction becomes ( x pg1 + x g1 + x y1 + x a1 ) ⁇ ( x pg2 + x g2 + x y2 + x a2 ) .
  • the setting of the threshold values for the window comparator WC7 may be such that an output signal of logic value 1 is generated when the logical sum output signal is an addition value of 4, and a logical value of 0 results when the addition value is 3 or less.
  • FIG 34 (a) shows the illumination relationship for the signal lights in the case where the arrow lights 1A, 2A are added.
  • FIG. 35 shows an embodiment of a simultaneous illumination detection circuit applicable to the case of a three way intersection (three roads intersecting with each other) with an illumination relationship as shown in FIG. 36.
  • the construction is such that a logical sum output for: an addition value for non illumination signals for a first direction and a second direction; an addition value for non illumination signals for the second direction and a third direction; and an addition value for non illumination signals for the third direction and the first direction, is level detected by a window comparator WC k .
  • numerals 600, 601 and 602 indicate respective fourteenth, fifteenth and sixteenth adding circuits.
  • Methods of monitoring the illumination condition of a signal light using a current sensor involve; the method as shown in FIGS. 1 (a) and (c) where a voltage sensor is connected across the terminals of a light switch SW for a signal light L, and the method as shown in FIGS. 1 (b) and (d) wherein a voltage sensor is connected across the terminals of a signal light L.
  • FIG. 39 shows an embodiment of a simultaneous illumination detection circuit according to the safety verification type, for signal lights at a three way intersection having an illumination relationship as shown in FIG. 38.
  • the non illumination signals x pg1 , x g1 , x y1 , and x pg2 , x g2 , x y2 , and x pg3 , x g3 , x y3 for the signal lights of the respective signal units are added by respective tenth, eleventh and twelfth adding circuits 700, 701 and 702 which use voltage doubler rectifying circuits respectively, and the addition values are then level detected with window comparators WC a , WC b and WC c serving as respective seventh, eighth and ninth level detection circuits.
  • FIG. 38 showing a step diagram for signal light illumination for three aspects of signal light illumination at a three way intersection, none of the signal lights 1PG, 1G, or 1Y illuminated is represented by 1R, none of the signal lights 2PG, 2G, or 2Y illuminated is represented by 2R, and none of the signal lights 3PG, 3G, or 3Y illuminated is represented by 3R.
  • the logical outputs of 1R, 2R and 3R (AC output signals) are added, and 2 or more is taken as no simultaneous illumination and 1 or less is taken as simultaneous illumination, then simultaneous illumination of the lights can be monitored in exactly the same way as for the case with current detection.
  • FIG. 40 shows a structural example for the case where the voltage signal V S across the terminals of the switch SW is sampled as an AC signal, using the voltage sensor of FIG. 1 (c) which utilizes a photocoupler.
  • photocouplers PI1, PI2, and PI7, PI8 are connected across the terminals of a switch circuit SW (for example a bi-directional thryistor) for respective signal lights (represented in FIG. 40 by PG, the pedestrian proceed permit light) via terminals 1, 4 and a resistor Ra. Also in a similar manner with signal lights Y, photocouplers PI3, PI4 and PI7, PI8 are connected via terminals 2, 4, and a resistor Rb. Similarly with signal lights G, photocouplers PI5, PI6 and PI7, PI8 are connected via terminals 3, 4, and a resistor Rc.
  • a switch circuit SW for example a bi-directional thryistor
  • the terminal 4 is connected as a common line for the signal lights PG, Y and G, to the side of the switch circuit opposite the signal light side.
  • the photocouplers PI1 and PI2, PI3 and PI4, PI5 and PI6 sample from photodiodes a current flowing in both directions, and correspond to second photocouplers.
  • the photocouplers PI7, PI8 have supplied to their respective light emitting elements from a signal generator SG, a high frequency switch current higher than the frequency of the AC power source for the signal lights, and correspond to first photocouplers for switching an AC current from the AC power source for the signal lights, according to the high frequency signal.
  • the current flowing in the resistors Ra, Rb and Rc is switched by the respective light receiving elements of the photocouplers PI7, PI8, and the respective light emitting elements of the photocouplers PI1, PI2, PI3, PI4, PI5 and PI6 pass this switch current.
  • the current switched by the photocoupler PI7 is passed by the respective light emitting elements of the photocouplers PI2, PI4 and PI6, so that an AC output signal is generated in the respective light receiving elements corresponding to these.
  • the current switched by the photocoupler PI8 is passed through the respective light emitting elements of the photocouplers PI1, PI3 and PI5, so that an AC output signal is produced in the respective light receiving elements corresponding to these.
  • this current is not passed.
  • the lower limit threshold value of the window comparator WCd is set to a logical level between 1 and 2, so that when the addition value of the logical outputs from the window comparators WCa, WCb and WCc is 2 or more, the logical output from the window comparator WCd becomes 1, and an output indicating normal (no simultaneous illumination) is generated.
  • the construction for the second photocouplers as shown in FIG. 40 (a) with two photocouplers connected in parallel in opposite directions to each other so as to match the direction of the AC current flowing via the resistors Ra, Rb and Rc the construction may be as shown in FIG. 40 (b) where the current flowing in the resistors Ra, Rb and Rc is rectified by a full wave rectifying circuit 801, and the light emitting element side of a photocoupler PI20 is connected to the rectified output side.
  • the construction for the first photocoupler with two photocouplers connected in parallel in opposite directions to each other the construction may be as shown in FIG.
  • FIG. 40(b) shows only a voltage sensor portion for detecting the voltage across the terminals of the signal light G. However the construction can also be the same for the other signal lights PG and Y.
  • FIG. 41 shows a circuit example for sampling without addition, the AC voltage signals for the signal lights G, PG and Y, as logical product signals of the voltage sensor outputs.
  • Photocouplers PI7,PI8 corresponding to a first photocoupler are switched by a switch output signal from a signal generator SG in the same way as in FIG. 40, switching the current flowing in a resistor Ra when there is a voltage at terminal 1.
  • This switch current is detected by photocouplers PI1, PI2, corresponding to a second photocoupler.
  • This switch current is then supplied to photocouplers PI3, PI4 which are cascade connected to the photocouplers PI1, PI2.
  • the switch signal is transmitted to photocouplers PI9, PI10 which are cascade connected to photocouplers PI3 and PI4.
  • the prior stage voltage doubler rectifying circuits and the window comparators WCa ⁇ WCc in the circuit of FIG. 39 are not necessary, and the sensor output can be input directly to the respective voltage doubler rectifying circuits in the succeeding stage.
  • Setting of the threshold values for the window comparator WCd is the same.
  • the method of monitoring the voltage V L across the terminals of the signal lights has an advantage over the method of monitoring the voltage V S across the terminals of the switch circuit, from the point that a current does not flow in the signal light when the switch circuit is off.
  • the non illumination condition is made the safe condition in order to ensure an even greater level of fail-safety
  • the resistors Ra, Rb and Rc in FIG. 40 and FIG. 41 are for this reduction.
  • the method for current detection involves detecting whether or not a transducer is passing a current, and when not (non illumination of the signal light), a high level AC signal results. Therefore, in the case as shown by the dashed line in FIG. 42, where a short circuit fault occurs between the two signal light terminals due for example to a construction works error, then at the time of illumination, a signal indicating non illumination is produced. For example, in FIG. 42, in the case where a short circuit occurs between the signal light terminals A, B while the switch circuit S G is off, then with switching on the switch circuit S R , the signal light G also comes on. With the method where the current across the terminals of the switch circuit is detected, if a current does not flow in the switch circuit S G , this will be detected as a non illumination condition, irrespective of whether or not the signal light G is illuminated.
  • FIG. 43 shows a structural diagram of an embodiment of a control apparatus for traffic signal lights, based on simultaneous illumination detection of proceed permit signal lights.
  • This embodiment illustrates a control apparatus example for a case with pedestrian proceed permit signal lights 1PG, 2PG, for the respective directions at a two way intersection.
  • an illumination control circuit 311 is for illumination control of the intersection signal lights in a predetermined sequence. As well as controlling the signal lights 1G, 2G, 1Y, 2Y, 1PG, 2PG, and 2R in FIG. 43, it also controls the illumination of a signal light 1R (not shown in the figure).
  • G indicates a green light
  • Y indicates a yellow light
  • R indicates a red light.
  • a simultaneous illumination detection circuit 312 serving as a signal light monitoring circuit is constructed for example as shown in FIG. 33, with the power supply lines for the first direction signal lights 1G, 1Y, 1PG and the second direction signal lights 2G, 2Y, 2PG, wound around respective saturable magnetic ring cores, or simply passed through the ring cores (passed through corresponds to one turn).
  • An R/Y flash monitoring circuit 313 serving as a flash monitoring circuit also, as shown in subsequent FIG. 44 (a) or FIG. 45 (a), incorporates a similar saturable magnetic ring core or cores, with the power supply lines for the signal lights 2R and 1Y wound around a single or separate saturable magnetic ring cores.
  • the power supply line for the signal light 1Y is wound around the saturable magnetic ring core of the simultaneous illumination detection circuit 312, and at the same time is wound around the saturable magnetic ring core for the R/Y flash monitoring circuit 313.
  • FIG. 44 (a) shows an embodiment of an R/Y flash monitoring circuit constructed with the power supply lines for the signal lights 2R and 1Y wound around separate saturable magnetic ring cores.
  • C orY and C orR indicate the saturable magnetic ring cores.
  • a power supply line for the signal light 1Y is wound around the saturable magnetic core C or1 of the simultaneous illumination detection circuit 312 (FIG. 33), and then the portion between this and the signal light 1Y is wound around the core C orY .
  • a power supply line for the signal light 2R is wound around the core C orR .
  • Output signals e Y and e R as shown in FIG. 44 (b), are respectively output from the output windings N bY and N bR of the saturable magnetic ring cores C orY and C orR when the alternately flashing signal lights 1Y and 2R are respectively not illuminated.
  • These high frequency output signals are then rectified by respective voltage doubler rectifying circuits REC39, REC40, the rectified output signals then supplied via respective coupling capacitors C Y , C R to clamp diodes D Y1 , D R1 and thereby clamped at a power source potential E, and then input from diodes D Y2 , D R2 via a wired OR connection to a window comparator WC12.
  • the upper limited threshold value V H of the window comparator WC12 is set to a sufficiently high level.
  • FIG. 45 (a) shows an embodiment of an R/Y flash monitoring circuit constructed with the power supply lines for the signal lights 2R and 1Y wound around a single saturable magnetic ring core.
  • the upper limit threshold value V H for the window comparator WC13 is set lower than the output level of the voltage doubler rectifying circuit REC41 for when the signal lights 1Y and 2R are simultaneously illuminated, and the lower limit threshold value V L is set between the output level of the voltage doubler rectifying circuit REC41 for normal operating conditions and the output level of the voltage doubler rectifying circuit REC41 for when neither of the signal lights 1Y and 2R are illuminated, then only when the signal lights 1Y and 2R are operating normally will the output signal Y 132 from the window comparator WC13 become a logic value 1.
  • SH 1 and SH 2 indicate the beforementioned window comparator type fail-safe first and second self-hold circuits (refer to FIG. 10).
  • the self-hold circuit SH 1 With the self-hold circuit SH 1 , the power source switch on signal for the illumination control circuit 311 is made a trigger input signal.
  • N 1 and N 2 indicate NOT circuits. A structural example of these circuits is given in FIG. 46.
  • an input signal IN corresponds to an AC output signal Y 141 from the self-hold circuit SH 1
  • this corresponds to an AC output signal Y 14 from the simultaneous illumination detection circuit 312.
  • a voltage doubler rectifying circuit comprising capacitors C 341 , C 342 and diodes D 341 , D 342 , corresponds to voltage doubler rectifying circuits REC 44 and REC 45 in FIG. 43.
  • D 343 indicates a level conversion zener diode having a zener potential slightly greater than the power source potential E, for driving a transistor Q 341 which goes off at a potential lower than the power source potential E.
  • R 341 , R 342 and R 343 indicate resistors.
  • the output signal from the NOT circuit N 2 becomes the input signal to the window comparator type self-hold circuit SH 2 . Consequently, this input signal must be of a higher potential than the power source potential E. Therefore, the NOT circuit N 2 is constructed with a capacitor C 343 and a clamp diode D 344 outlined by the dashed line C in FIG. 46 added to the constituent components of the NOT circuit N 1 . Hence, with the transmission of a rising signal for the signal P 1 , the output signal from the transistor Q 341 is generated as an output signal P 2 of a higher level than the power source potential E.
  • the signal lights 1G, 2G, 1Y, 2Y, 1PG, and 2PG which are switched by the illumination control circuit 311, have their illumination condition monitored by the simultaneous illumination detection circuit 312. If these signal lights are operating normally, then the output signal Y 14 is always a logic value 1. When the power source is switched on, since the respective signal lights are not illuminated and there is thus no simultaneous illumination, then the output signal Y 14 1 is input to the reset input terminal of the self-hold circuit SH 1 , and due to the input of the trigger signal with the power source being switched on, the self-hold circuit SH 1 generates an output signal Y 141 of logic value 1.
  • This AC output signal Y 141 is transmitted to an amplifier 318 via a capacitor C 311 so that a relay 321 is excited via a transformer 319 and a rectifying circuit 320, and contact points 322 thereof close, thus connecting the AC power source to the respective signal lights.
  • FIG. 47 (a) shows an example of a trigger input signal generating circuit for inputting a trigger signal to the self-hold circuit SH 1 when the power source is switched on.
  • the potential is stored in a capacitor C 351 via a resistor R 351 and rises.
  • This rising signal is clamped at the potential E with the capacitor C 352 as a coupling capacitor and the diode D 351 as a clamp diode, and then output.
  • This trigger input signal generating circuit may also be constructed as shown in FIG. 47 (b) with a level detection circuit 350 provided between an integrating circuit of the resistor R 351 and the capacitor C 351 , and the coupling capacitor C 352 .
  • FIG. 47 (c) shows the operation of the self-hold circuit SH 1 after switching on the power source potential E.
  • the output signal from the self-hold circuit SH 1 is shown as the output signal from the voltage doubler rectifying circuit REC44.
  • the R/Y flash command generating circuit 314 has a latching function (storage function) so that the falling component of the output signal Y 14 from the simultaneous illumination detection circuit 312 can be stored, then the output signal Y 14 from the simultaneous illumination detection circuit 312 can be input directly to the voltage doubler rectifying circuit REC44, and the voltage doubler rectifying circuit REC42 and the self-hold circuit SH 1 omitted.
  • the circuits of FIG. 47 (a) and (b) for generating a trigger input signal at the time of switching on the power also become unnecessary.
  • the R/Y flash command generating circuit 314, the self-hold circuit SH 2 , the NOT circuits N 1 , N 2 , the voltage doubler rectifying circuits REC44, REC45, REC43, and the capacitor C 312 become unnecessary.
  • the window comparator after the adding circuit can have an upper limit threshold value V H set between addition output signals 2e and 3e, and a lower limit threshold value V L set between addition output signals 2e and e.
  • an upper limit threshold value V H can be set between addition output signals 4e and 5e
  • a lower limit threshold value V L can be set between addition output signals 4e and 3e. If the output signal from the window comparator for the former case is Y 15 and the output signal from the window comparator for the latter case is Y 16 , and the levels of the addition output signals are respectively me and m e, then the logic values of the respective output signals are given by the following equations.
  • FIG. 48 illustrates a case where pedestrian signal lights 1PG, 1PR, 2PG and 2PR are added to the case illustrated in FIG. 18 (a).
  • 1A is for an arrow light, which will be discussed later.
  • the addition level me decreases, and this also decreases in the case where a fault occurs in the sensor or the adding circuit. Consequently, with the method wherein the number of illuminations is added, when a double fault occurs such as a simultaneous illumination error occurring in the signal lights and a fault occurring in the sensor or the adding circuit, this error cannot always be notified. However, a burn-out fault can always be notified.
  • the addition level m e decreases, while if a burn-out fault occurs in the signal lights, the addition level m e increases. Therefore, for the same reason as for the above method where the number of illuminations are added, with the method where the number of non illuminations are added, when a double fault occurs such as a burn-out fault occurring in the signal light and a fault occurring in the sensor or the adding circuit, then the burn-out fault cannot always be notified. However if a simultaneous illumination occurs, this can always be notified.
  • the arrow light 1A in FIG. 48 is for giving permission to travel in a specific travel direction.
  • this signal light is shown as being illuminated at interval 5 (shown by the full line).
  • signals for illumination and non illumination of the arrow light 1A are output as respective output signals x a1 and x a1 from the voltage doubler rectifying circuits REC46 and REC47 which are respectively clamped at zero potential, and changes in these rectified output signals are respectively clamped at the power source potential E and made the input signals x a1 ' and x a1 ' for a window comparator WC14.
  • the output signal from the voltage doubler rectifying circuit REC47 continues to be generated giving a DC output signal, while the output signal from the voltage doubler rectifying circuit REC46 becomes zero.
  • FIG. 50 shows an embodiment for a case where the beforementioned fail-safe self-hold circuit is used.
  • numeral 50 indicates a signal light abnormality detection circuit based on the abovementioned addition, with an output signal Y18 being the output signal from a window comparator which carries out the threshold value operation.
  • a voltage doubler rectifying circuit REC48 rectifies this output signal which then becomes the reset signal for a window comparator type self-hold circuit SH 3 .
  • the trigger signal for the self-hold circuit SH 3 is produced by the circuit of FIGS. 47 (a) or (b).
  • FIG. 51 illustrates a different embodiment.
  • a fail-safe on-delay circuit 51 (having the characteristic that at the time of a fault the delay time is not lengthened) is used.
  • FIG. 52 shows an example of a fail-safe on-delay circuit.
  • FSSH denotes the self-hold circuit shown in FIG. 10, constructed such that an output signal from the fail-safe AND gate is fed back to the input terminal 2.
  • PUT-OSC denotes a PUT oscillator which produces an oscillation pulse at a threshold value (a voltage division ratio for resistors R12 and R13) held by a PUT (programmable unijunction transistor), relative to a charging input determined by a time constant R 11 ⁇ C 11 , when an input signal IN is applied. That is to say, as shown by the time chart of FIG.
  • Such a fail-safe on-delay circuit is known for example from prior International Patent Publication No. WO94/23496.
  • a signal light abnormality detection circuit 50 and a voltage doubler rectifying circuit REC48 are the same as in FIG. 50.
  • FIG. 53 shows the case where three signal lights L1, L2 and L3 are connected to a signal light power supply line AB.
  • respective signal light leads are wound on saturable magnetic ring cores C or1 , C or2 , and C or3 .
  • respective second windings N f1 , N f2 and N f3 are wound on the saturable magnetic cores C or1 , C or2 and C or3 .
  • These are connected in series and connected to a secondary winding N O2 of a transformer T f1 .
  • a high frequency signal is supplied to a primary winding N O1 of the transformer T f1 from a high frequency signal generator SG f1 via a resistor R f1 .
  • the high frequency signal generator SG f1 is constructed as in FIG. 4.
  • a terminal voltage e f of the resistor R f1 is amplified by an amplifier AMP3, rectified by a voltage doubler rectifying circuit REC49, and input to one input terminal 2 of a two input window comparator WC15.
  • An illumination command signal is input to the other input terminal 1 of the window comparator WC15. Instead of the illumination command signal, an illumination signal for the signal lights L1, L2, L3 may be input.
  • the impedances Z 1 , Z 2 and Z 3 of the respective windings N f1 , N f2 and N f3 show a high value. That is to say, the impedance Z f1 seen from the primary side of the transformer T f1 is low at the time of illumination and high at the time of non illumination, and hence the terminal voltage e f of the resistor R f1 , as shown in FIG.
  • FIG. 55 shows an embodiment of a different simultaneous illumination detection circuit.
  • This embodiment is a circuit example for a case with a three way intersection with three roads intersecting with each other as illustrated in FIG. 56 (which is similar to FIG. 36), where danger information is separated into: danger information for when a simultaneous illumination occurs with pedestrian proceed permit lights PG (between 1PG and 2PG, 1PG and 3PG, or 2PG and 3PG), or a simultaneous illumination occurs with vehicle proceed permit lights G (between 1G and 2G, 1G and 3G, or 2G and 3G), or a simultaneous illumination occurs with a pedestrian proceed permit light PG and a vehicle proceed permit light G (excluding simultaneous illumination of the same direction pedestrian and vehicle proceed permit lights); and danger information for when a simultaneous illumination occurs with a green light G and a yellow light Y for different directions.
  • the red light R is omitted.
  • FIG. 55 is a structural example of a signal light simultaneous illumination detection circuit with current sensors using saturable magnetic ring cores.
  • M 11 , M 21 , M 31 , M 41 , M 51 and M 61 indicate excitation windings wound onto respective saturable magnetic ring cores of respective first through sixth current sensors.
  • the excitation current is supplied from a signal generator SG via respective resistors R 210 , R 220 , R 230 , R 240 , R 250 and R 260 .
  • L 1PG , L 1G , L 1Y and L 2PG , L 2G , L 2Y , and L 3PG , L 3G , L 3Y indicate power supply lines for respective signal lights for first, second and third directions, which are passed through the saturable magnetic ring cores.
  • the directions of the current passing through the power supply lines L 1PG , L 1G , and L 2PG , L 2G and L 3PG , L 3G are respectively in the same direction.
  • Windings M 12 , M 13 , and M 22 , M 23 , and M 32 , M 33 , and M 42 , M 43 and M 52 , M 53 , and M 62 , M 63 are windings for sampling the respective non saturated outputs at the time of non illumination. When a current flows in the power supply lines which pass through the saturable magnetic ring cores, the output signal from these windings becomes a low level.
  • 210 through 230 indicate fifteenth, sixteenth and seventeenth adding circuits which are respectively constituted by voltage doubler rectifying circuits REC1-1 through REC1-4, REC2-1 through REC2-4, and REC3-1 through REC3-4.
  • the adding circuit 210 adds the respective winding output signals ( x gp1 ) 1 ,( x y1 ) 1 , ( x gp2 ) 1 and ( x y2 ) 1 for when the first direction signal lights 1PG, 1G, 1Y and the second direction signal lights 2PG, 2G, 2Y shown in FIG. 56 are not illuminated (the interval shown by 1GY and 2GY ).
  • the adding circuit 220 adds the respective winding output signals ( x gp1 ) 2 , ( x y1 ) 2 , ( x gp3 ) 1 and ( x y3 ) 1 for when the first direction signal lights 1PG, 1G, 1Y and the third direction signal lights 3PG, 3G, 3Y are not illuminated (the interval shown by 1GY and 3GY ).
  • the adding circuit 230 adds the respective winding output signals ( x gp2 ) 2 , ( x y2 ) 2 , ( x gp3 ) 2 and ( x y3 ) 2 for when the second direction signal lights 2PG, 2G. 2Y and the third direction signal lights 3PG, 3G, 3Y are not illuminated (the interval shown by 2GY and 3GY ).
  • the addition output signals from the adding circuits 210, 220 and 230 are respectively 18V. Therefore, when for example the output level from the adding circuit 210 is 18V, then if an illumination condition occurs in the signal lights 1G or 1PG, or the signal lights 2G or 2PG, then the output level from the adding circuit 210 becomes 12V, dropping by 6V.
  • the output level from the adding circuit 210 becomes 15V (drops 3V).
  • the fail-safe window comparators WC-GP and WC-GY when the input level is 18V, a high level output signal of logic value 1 is output.
  • the window comparator WC-GP if the input level drops 6V, a low level or a zero level output signal of logic value 0 is output. Therefore, the lower limit threshold value T L of the window comparator WC-GP is set between 15V and 12V (for example 13.5V) (the upper limit threshold value T H is set sufficiently higher than 18V).
  • the window comparator WC-GY if the input level drops 3V, a low level or a zero level output signal of logic value 0 is output. Therefore, the lower limit threshold value T L of the window comparator WC-GY is set between 18V and 15V (for example 16.5V) (the upper limit threshold value T H is set sufficiently higher than 18V)
  • the window comparator WC-GP outputs a logic value 1 even if a simultaneous illumination occurs between a yellow light Y and a green light GP or G, and intermittently produces a logic value 0 only if a simultaneous illumination occurs between green lights GP or G.
  • the window comparator WC-GY intermittently produces a logic value 0 if a simultaneous illumination occurs between green lights GP or G, and also if a simultaneous illumination occurs between a yellow light Y and a green light GP or G.
  • FIG. 57 shows an embodiment for the case where signal light non illumination signals are sampled from a common signal light power supply line.
  • the power supply line for normal traffic signal lights is made up of illumination wires for the green light G, the yellow light Y, and the red light R, and one common lead. Consequently, since an illumination current for any one of the signal lights G, Y or R always flows in the common lead, then the non illumination signals for the green light G and the yellow light Y can not be sampled by a sensor coil for detecting zero current.
  • common leads L C for the respective signal lights pass through the saturable magnetic ring cores C or1 , C or2 and C or3 , and at the same time power supply lines L 1R , L 2R and L 3R for the red lights 1R, 2R and 3R are passed through in the opposite winding direction to the common leads L C .
  • the adding circuits 240, 250 and 260 carry out respective logical sum operations on the sum of the output signals (x 1 ) 1 and (x 2 ) 1 , the sum of the output signals (x 1 ) 2 and (x 3 ) 1 , and the sum of the output signals (x 2 ) 2 and (x 3 ) 2 for when the respective signal lights 1R, 2R and 3R are illuminated.
  • the window comparator WC-GPY if the respective current output signals are 3V, then an output level due to addition of 6V is made normal, while less than 6V is not normal.
  • FIG. 58 shows a circuit example for where the number of output windings for the saturable magnetic ring cores C or1 , C or2 and C or3 is not two windings, but is only the respective output windings M 12 , M 22 and M 32 .
  • the respective output signals (x 1 ) 1 , (x 2 ) 1 and (x 3 ) 1 therefrom are added by adding circuits comprising voltage doubler rectifying circuits, and when the addition value is 6V or above, an output signal of logic value 1 indicating normal is generated from a window comparator WC-GPY, while if less than 6V, an output signal of logic value 0 is generated indicating an abnormal illumination condition.
  • the respective rectified output signal levels are 3V).
  • FIG. 59 With the circuit configuration of FIG. 57 or FIG. 58, simultaneous illumination detection is possible even in a worst case situation as shown in FIG. 59, where for some reason a short circuit as shown by the dashed line in FIG. 59 occurs between junction connection terminals for the power supply lines of for example the first direction signal light 1G and the second direction signal light 2G. Erroneous illumination due to this often occurs due to lack of care with the connections during construction work, or due to rain permeating into the junction box.
  • C indicates a common wiring terminal.
  • the non illumination signals x g1 , x g2 correspond to the output signal x g1 from the current sensor shown in FIG. 16. As shown in FIG. 60 (b) these are respectively amplified by amplifiers 301, 302, rectified by rectifying circuits 303, 304, and then supplied to electromagnetic relays R g1 , R g2 .
  • the signal light 1G is illuminated when, with non illumination of the signal light 2G, the electromagnetic relay R g2 is excited so that the contact points S g2 come on, while the signal light 2G is illuminated when, with non illumination of the signal light 1G, the electromagnetic relay R g1 is excited so that the contact points S g1 come on. If with one of the signal lights 1G (or 2G) in the illuminated condition, there is an attempt to illuminate the other signal light 2G (or 1G), this other signal light 2G (or 1G) will not illuminate.
  • the present invention has a fail-safe construction which can monitor the illumination condition of traffic signal lights provided at an intersection or the like and reliably advise when an abnormal illumination condition arises, and which can also warn of an abnormality at the time of a fault in the monitoring apparatus. Safety of a traffic signal light control system can thus be improved, and hence industrial applicability is considerable.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Traffic Control Systems (AREA)
EP00201697A 1995-04-20 1995-04-20 Überwachungseinrichtung und Steuereinrichtung für Signallampen Withdrawn EP1045359A1 (de)

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EP95916024A EP0786752B1 (de) 1995-04-20 1995-04-20 Vorrichtung zur überwachung und steuerung von verkehrssignalen

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2012465A (en) * 1978-01-10 1979-07-25 Philips Nv Monitoring operation of traffic lights
DE2851050A1 (de) * 1978-11-25 1980-06-04 Messerschmitt Boelkow Blohm Schaltungsanordnung zum vergleichen von analogsignalen
DE3415143A1 (de) * 1983-04-25 1984-10-31 N.V. Philips' Gloeilampenfabrieken, Eindhoven Anordnung zum ueberwachen von von einer speisenetzleitung herruehrenden signalen an ausgaengen von steuerschaltungen zur steuerung von signallampen in verkehrssteuersystemen
EP0214692A2 (de) * 1985-09-05 1987-03-18 Koninklijke Philips Electronics N.V. Überwachung eines Konfliktdetektors für Verkehrsampeln
FR2672145A1 (fr) * 1991-01-29 1992-07-31 Electricite De France Dispositif de detection d'un defaut d'une lampe d'un feu tricolore et installation de controle du trafic comportant un tel dispositif.

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2012465A (en) * 1978-01-10 1979-07-25 Philips Nv Monitoring operation of traffic lights
DE2851050A1 (de) * 1978-11-25 1980-06-04 Messerschmitt Boelkow Blohm Schaltungsanordnung zum vergleichen von analogsignalen
DE3415143A1 (de) * 1983-04-25 1984-10-31 N.V. Philips' Gloeilampenfabrieken, Eindhoven Anordnung zum ueberwachen von von einer speisenetzleitung herruehrenden signalen an ausgaengen von steuerschaltungen zur steuerung von signallampen in verkehrssteuersystemen
EP0214692A2 (de) * 1985-09-05 1987-03-18 Koninklijke Philips Electronics N.V. Überwachung eines Konfliktdetektors für Verkehrsampeln
FR2672145A1 (fr) * 1991-01-29 1992-07-31 Electricite De France Dispositif de detection d'un defaut d'une lampe d'un feu tricolore et installation de controle du trafic comportant un tel dispositif.

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