Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/061—Manufacture or treatment of FETs having Schottky gates
  • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P10/00—Bonding of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
  • H10D30/877—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] having recessed gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
  • H10D64/0124—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors
  • H10D64/0125—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors characterised by the sectional shape, e.g. T or inverted T
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/60—Wet etching
  • H10P50/64—Wet etching of semiconductor materials
  • H10P50/642—Chemical etching
  • H10P50/646—Chemical etching of Group III-V materials

Definitions

• the present invention is drawn to a recess etch process with selective chemistry which is advantageous in the manufacture of gallium arsenide-based epitaxial field effect transistors.
• Gallium-arsenide based field-effect transistors utilizing the depletion region formed by a metal- semiconductor junction, commonly known as a Schottky junction, to modulate the conductivity of an underlying channel layer have gained acceptance as a high performance transistor technology owing to inherent physical properties of the gallium arsenide and related ternaries, indium gallium arsenide.
• Such devices are referred to by those of ordinary skill in the art by various names such as metal semiconductor field effect transistors (MESFET) , high electron mobility transistors (HEMT) , psuedomorphic high electron mobility transistor (pHEMT) , two dimensional electron gas field effect transistors (TEGFET) and modulation doped field effect transistors (MODFET) .
• MESFET metal semiconductor field effect transistors
• HEMT high electron mobility transistors
• pHEMT psuedomorphic high electron mobility transistor
• TEGFET two dimensional electron gas field effect transistors
• MODFET modulation doped field effect transistor
• FET field effect transistors
• the function of the device is relatively basic. In logic circuits the devices often function as switches, by virtue of the fact that the gate voltage acts in a manner analagous to a valve in turning off current between the source and the drain in a region well-known as the channel. In analog circuits, a small time-varying voltage on the gate results in a time varying current between the source and the drain. Because the gate current is ideally a pure displacement current, a very small input power can be readily amplified.
• the basic gallium arsenide metal semiconductor field effect transistor known as a MESFET has the source and drain current carried via a relatively thin, highly doped, semiconductor layer, the channel.
• the current is controlled by the gate which forms a Schottky barrier on the semiconductor, and therefore depending upon the applied gate voltage depletes the semiconductor layer of electrons under the gate.
• Other devices enumerated above to include the HEMT, pHEMT, and MODFET are based on the basic principles described above.
• the structure of a basic HEMT is based on the heterojunction between two dissimilar materials, e.g., an AlGaAs (Aluminum Gallium Arsenide) and GaAs (Gallium Arsenide) well-known to one of ordinary skill in the art.
• the essential structure consists of a semi-insulating substrate on which is first grown a buffer layer of nominally unintentionally doped GaAs.
• An nOayer of Al x Ga lx As is disposed on top of the channel layer to form a proper Schottky barrier with the gate metalization.
• the last layer is typically a GaAs contact layer which is doped highly n-type to facilitate the formation of ohmic contacts to the underlying channel layer.
• the two ohmic contacts disposed on this layer are generally referred to as the source and drain contacts. Access resistances associated with these contacts and the underlying semiconductor material to the intrinsic device are typically referred to as R s and R d , the source and drain resistances, respectively.
• gain, noise and total microwave output power are factors which are of prime consideration in the design of GaAs based field effect transistors.
• the transconductance or "gain" for an FET device is defined as the follows:
• I ds is the current between the drain and source
• Vg is the gate voltage
• g m can be estimated for a high-low-high MESFET with relatively thin channel layers for example by the following expression
• ⁇ is the permitivity of GaAs
• V sat is the saturation velocity of electrons in GaAs
• w g is the width of the gate electrode
• t is the gate electrode to channel spacing.
• this layer thin, for a given change in the gate voltage, a greater control is realized over the conductivity of the channel, and therefore a greater change in I ds is realized.
• the transconductance is greater.
• the closer the gate metalization is to the channel the lower is the pinch off voltage, or the voltages required to reduce the drain current to a negligible value.
• the GaAs FET structure of devices of the present disclosure functions by applying a potential to the gate to modulate to conductivity of the underlying channel and thereby to control the source-to-drain current which results from a positive potential applied from drain-to-source.
• the preferred structure of a highly doped channel (n + ) , a lightly doped (n ⁇ ) Schottky layer and a highly doped n + contacting layer is known as a high-low-high structure.
• a material should be chosen to improve the velocity of carriers in a channel, so as to improve the gain of the device by the equation set forth above.
• the contact layers on which the drain and source metalizations are disposed are etched down and reveal the n " layer which provides the surface on which the gate electrode is subsequently disposed.
• This iterative procedure is labor intensive requiring a technician to measure drain-to- source current following each itteration of etch to determine if the target current has been attained. Furthermore, this labor intensive process is often not reproducible in reliable manner. In addition, a certain point will be reached in the etching process where the source-to-drain current reaches an unacceptable value. This condition is referred to as over-etch and results in devices which do not meet performance specifications. Additionally, such iterative processing often results in etch depth variation across the wafer and from wafer-to- wafer. This dimensional variation has a direct impact on the performance variation. For example, a 5% across- wafer variation in pinchoff voltage is often realized. The variation of this parameter across the process can typically exceed 12%. Parameter variation is defined here as standard deviation divided by average.
• access resistance is a general term used to describe what are commonly referred to in the art as the source and drain resistances.
• g —'me is the extrinsic transconductance of the device as measured at its external terminals
• ' g—'mi. is the intrinsic transconductance or that which the device would exhibit if the source resistance were negligible
• R s is the source resistance of the device.
• an increase in the device access resistances will increase the drain-to-source voltage at which the drain current saturates what is often referred to in the art as the knee voltage. The increased knee voltage can limit the power performance of the device.
• the access resistances are often described as being comprised of two primary elements, one associated with the metal- semiconductor interface, the other associated with the semiconductor material outside of the influence of the gate electrode.
• an etch-stop layer into the structure adds an additional resistive component to the device access resistances.
• This component is associated with a tunneling barrier imposed by the offset in the minimum allowed energies of conduction electrons between the two dissimilar materials commonly known as conduction band discontinuity.
• Reported experimental values of the conduction band discontinuity for the AlAs/GaAs materials system is on the order of 500 meV.
• the present invention is drawn to an In x Ga 1.x P etch- stop layer for improving the uniformity of devices across an epitaxial wafer incorporating a high-low-high MESFET structure.
• the range of permissable values of x will vary as a function of the thickness of the etch stop layer.
• x is on the order of 0.5 in order to maintain lattice match with the GaAs substrate.
• a novel process for selective recess etching of GaAs field-effect transistors is disclosed.
• the present invention envisions the use of a relatively thin (10-30 Angstrom) layer of the In x Ga 1 _ x P material to effect the selective recess etching of the material to a point where a relatively uniform thickness of n " material remaining above the channel layer is realized.
• a relatively thin (10-30 Angstrom) layer of the In x Ga 1 _ x P material to effect the selective recess etching of the material to a point where a relatively uniform thickness of n " material remaining above the channel layer is realized.
• etch stop layer has the metalization for the gate electrode deposited directly thereon
• a portion of the In x Ga x _ x P etch stop can be removed and metalization can be effected directly on the underlying n " layer.
• This alternative embodiment has the advantage that higher selectivities can be attained and, hence, improved uniformity in device characteristics can be realized across the wafer and from wafer to wafer. This improved selectivity occurs by virture of the availability of etch chemistries which etch In x Ga 1 x P at a finite rate but exhibit a relatively negligible etch rate for the underlying GaAs layer or effectively an infinite selectivity.
• An example of such a wet chemistry is the HC1 :H 3 P0 4 :HC1 system.
• the material chosen for the etch stop layer of the present invention exhibits a selectivity with respect to etching of the contact layers for the drain and source as well as the ability to etch directly through the In x Ga 1.x P etch stop layer to effect metalization directly on the n " material.
• etch stop material provides for a heterojunction between the etch stop layer and the n " layer GaAs which would enable higher bias voltages and a greater current swing, resulting an increase in the maximum open channel current, I max .
• Figures 1-6 show the device of the present disclosure in various stages of processing, with Figure 6 showing the salient features of the resultant device of the invention of the present disclosure.
• the present invention is drawn to a high-low-high gallium arsenide epitaxial field effect transistor structure. While the focus of the disclosure of the present invention will be on this special class of MESFET, it will be apparent to one of ordinary skill in the art, that the invention of the present disclosure has applicability to epitaxial devices in which a Schottky barrier is used to control current in a channel and that the common substrate material to all such devices is GaAs.
• the use of the In ⁇ a ⁇ P etch-stop of the invention of the present disclosure results in a lower conduction band discontinuity at the interface with the n ⁇ GaAs Schottky layer and results in a lower tunneling barrier to current flow, and accordingly lower access resistances to the device.
• This enables the benefits of the etch-stop while maintaining the performance characteristics of devices fabricated without an etch-stop which suffer the drawbacks of nonuniformity across a wafer as described previously.
• the typical value of x is 0.5 in order to maintain lattice-match with the GaAs substrate material.
• values of x other than 0.5 may be chosen to minimize the misfit dislocation density as described in, J.W. Matthews, A. E. Blakeslee, "Defects in epitaxial multilayers I. Misfit dislocations," J. Crytal Growth, vol. 27, pp. 118-125, 1974, the disclosure of which is specifically incorporated herein by reference.
• the semi-insulating GaAs substrate is shown at 101.
• This layer has a buffer layer of unintentionally doped GaAs 102 epitaxially disposed thereon and an n-doped layer of GaAs layer 103 which is the channel layer.
• This layer has a doping level on the order of 3xl0 17 cm "3 .
• the Schottky barrier layer 104 Disposed on top of the channel layer is the Schottky barrier layer 104 which is layer of GaAs doped lightly n-type. This layer has a doping level on the order of 5xl0 16 cm "3 .
• the Schottky barrier layer 104 has a thickness in the range of 200- 1000 Angstroms with a preferred thickness on the order of 430 Angstroms. As stated above, the distance between the gate metalization and the channel layer 103 is governed by the thickness of the layer 104, and thus this layer plays an important role in device parameters described herein.
• the etch-stop layer of In x Ga 1.x P is shown at 105. This layer is typically on the order of 10-40 Angstroms in thickness.
• One additional advantage of the use of the In x Ga x _ x P layer is described presently.
• 106 is a continuation of the underlying Schottky layer 104.
• the primary purpose of this layer is to spatially separate the gate electrode from the highly doped layer
• the contact layer 107 is highly doped n + to facilitate a good ohmic contact for the drain and source as described herein.
• the Schottky layer 104 is lightly doped to facilitate the formation of a good Schottky barrier. As described previously, the gate-to-channel spacing is chosen to realize, among other parameters, a specific pinch-off voltage v .
• the ohmic contacts are formed by defining the areas to be contacted lithographically, and then evaporating a suitable metal alloy for example AuGeNiAu followed by a subsequent lift off step of the photoresist layer.
• a suitable metal alloy for example AuGeNiAu
• the final ohmic contact is as shown at 201 for the source and 202 for the drain.
• Figure 3 shows the implant isolation which is done. In order to properly isolate one device on a wafer from another device, isolation implantation is performed in regions outside of the device lateral boundaries. These are as shown at 301.
• the regions which are outside the active semiconductor region are rendered electrically inactive by implantation of a species such as Boron, a preferred implant material. Proton implantation (H + ) may also be employed. This implant profile extends into the semi-insulating GaAs substrate 101 and serves to properly isolate the device.
• a species such as Boron, a preferred implant material.
• Proton implantation H +
• This implant profile extends into the semi-insulating GaAs substrate 101 and serves to properly isolate the device.
• An alternative to this method is to perform a mesa isolation, in which the required layers of the device are disposed in mesa form by etching to remove the active material from all regions outside of the device boundaries .
• the selective recess etch in the gate region is shown. This is as shown at 401.
• the gate region 401 is defined within an opening in a photolithographic film.
• This region is etched to remove the highly doped contact layer 107 and a portion of the Schottky layer, described as layer 106, prior to the deposition of the gate electrode material and is the area of primary focus in the invention of the present disclosure.
• a chemistry which etches GaAs at a higher etch rate when compared to the In ⁇ a ⁇ P etch rate, is to used to form the recess.
• such a selective chemistry would be H, 2SO A 4:H2,0,2:H,20 of volumetric ratio 1:8:500.
• the GaAs etch rate is on the order of 10 Angstroms per second at room temperature and the ratio of GaAs to In 05 Ga 05 P etch rates is on the order of 150. While it is clear that this chemistry is exemplary, it is of interest to note that other chemistries are clearly possible. To this end, the primary purpose of the etch- stop is to assure that the etching of the layers 106 and 107 proceed at a much faster rate than that of layer 105. By selecting the appropriate chemistry and thereby assuring an appropriate ratio of etch rates of the etch- stop layer 105 to that of layers 106 and 107, a relatively uniform recess etch depth is attained across the wafer.
• the gate electrode 601 is fabricated through deposition techniques well known to one of ordinary skill in the art. Using the same lithographic layer used for recess definition, a Schottky contact is deposited and lifted off. A typical gate electrode stack might consist of -TiPtAu. Following this, the device is usually passivated with a dielectric such as silicon nitride and connected with other circuit elements with additional layers of metalization. Optionally, the proportion of the etch-stop layer 105 exposed by the lithographic film used for recess definition may be selectively removed to reveal the underlying layer 105 prior to gate electrode deposition.
• etch-stop thicknesses 10 angstroms and 20 Angstroms, are preferred, although other thicknesses are possible.
• I max of 400 mA/mm compares well to a wafer fabricated through conventional techniques .
• a pinch-off voltage of -1.78 volts compares well to conventionally fabricated devices.
• the intrinsic transconductance of devices fabricated by the technique of the present disclosure with a 20 Angstrom etch-stop layer is on the order of 156 mS/mm which is comparable to a device fabricated by conventional techniques without an etch-stop layer.
• the sum of the source and drain resistances shows no significant difference to devices fabricated without an etch-stop.
• the AlAs samples exhibited 0.3 and 0.8 Ohm-mm for the 10 and 25 Angstrom case respectively as compared with 0.1 Ohm-mm for the control samples.
• the difference in value is attributable to a reduction in electron tunneling probability associated with the relatively large conduction band discontinuity at the AlAs/GaAs interfaces.
• For the In 05 Ga 05 P case no significant difference was observed between samples, including the control samples. That is, all exhibit contact resistances on the order of 0.15 Ohm-mm.
• the later result suggests that In 05 Ga 05 P etch stop layers as thick as 20 Anstroms do not present an additional parasitic resistive element when compared to the parasitic resistive elements of the control sample devices which do not use the etch stop layer of the present invention.
• the In x Ga 1. x P layer can be removed by highly selective chemistries.
• This region 501 has the In x Ga 1.x P layer removed, by a suitable chemistry.
• This alternative embodiment has certain advantages with respect to higher selectivity, hence, greater uniformity in etch depth.
• the invention of the present disclosure is drawn to an etch-stop layer which enables an improvement in across-wafer parameter uniformity by virtue of a uniform recess depth, without the deleterious effect on the device access resistances associated with more conventional etch-stop layers.
• etch-stop layer which enables an improvement in across-wafer parameter uniformity by virtue of a uniform recess depth, without the deleterious effect on the device access resistances associated with more conventional etch-stop layers.
• other materials and chemistries for etching such materials are within the purview of the artisan of ordinary skill, such within the scope of the present invention.

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• 1998
  • 1998-11-23 AU AU16007/99A patent/AU1600799A/en not_active Abandoned
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