EP1031128B1 - Système de temporisation de mise en marche et méthode pour la désactivation d'un dispositif de visualisation - Google Patents

Système de temporisation de mise en marche et méthode pour la désactivation d'un dispositif de visualisation Download PDF

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Publication number
EP1031128B1
EP1031128B1 EP98962202A EP98962202A EP1031128B1 EP 1031128 B1 EP1031128 B1 EP 1031128B1 EP 98962202 A EP98962202 A EP 98962202A EP 98962202 A EP98962202 A EP 98962202A EP 1031128 B1 EP1031128 B1 EP 1031128B1
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EP
European Patent Office
Prior art keywords
sync
signal
delay
display unit
turn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP98962202A
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German (de)
English (en)
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EP1031128A1 (fr
Inventor
Holger Weissbrod
Heiner Drewer-Gutland
Heinrich Hehemann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wincor Nixdorf International GmbH
Original Assignee
Wincor Nixdorf GmbH and Co KG
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the invention relates to a switch-on delay device for a data display device and a method for deactivation of such a device.
  • Such computer systems usually contain a central computer to which one Input device and a visual display device, i.e. a monitor, are connected as an output device. about the input device guides the user to the computer system the required input information.
  • an input device can be, for example, a keyboard or a so-called touchscreen can be used. Under touchscreen one understands one in the screen of the data display device integrated input device that touches implemented by the user in input information.
  • VGA video graphics card
  • EP-A-0 678 843 describes a method for deactivation known a visual display device in which the visual display device by blocking at least one of these controlling signals is in the idle state, which of a control device generated signal for a predetermined Delay period is locked.
  • the invention solves this problem by means of a switch-on delay device for a data display device that through Lock at least one controlling the data display device Signal can be put into an idle state.
  • the switch-on delay device contains at least one Input with a control device which supplies the signal is connected to a locking device that Blocks signal for a predetermined delay time, and at least one output connected to the data display device is connected and this the signal after the delay time supplies.
  • control signals usually a horizontal and a vertical synchronizing signal, that of a control device of a Computers, e.g. a graphics card, are generated and the Movement of an electron beam in the picture tube of the data display device coordinate by the horizontal sync signal the horizontal rewind and the vertical signal the vertical return of the electron beam controls during screen construction.
  • the invention now provides between the control device of the computer and the data display device a switch-on delay device to turn on when you start the computer the control signals for a predetermined delay time blocked so that the screen of the data display device darkened while the operating system is loading and that otherwise shown on the screen System messages are not displayed. On in this way the risk that a user standing in front of the data display device through the prompted system messages displayed on the screen sees, via an input device, for example a keyboard or a touchscreen to make entries, and so a complete failure of the computer system causes.
  • the invention offers the possibility of an existing Computer system regardless of the operating system and the used Retrofitting software in the manner shown above, without major changes to the computer system to have to.
  • the invention is particularly applicable to all Computer systems are applied in which one after VGA standard control device, i.e. a VGA graphics card, drives a VGA monitor.
  • VGA standard control device i.e. a VGA graphics card
  • the connection between the switch-on delay device and the computer on the one hand and the switch-on delay device and the display device on the other hand can Standard plug connections are made, for example through D-subminiature plug connections and corresponding plug receptacles are given.
  • the locking device has at least two switches which a first switch has a first input, that of a horizontal synchronizing signal is fed to the control device is connected to a first output, and a second switch a second input that from the control device a vertical synchronizing signal is supplied, connects to a second output.
  • the assigned to each other Inputs and outputs are therefore directly above one each controlled by the locking device Switches connected together.
  • They can be advantageous Switches can be designed as CMOS switches. Advantages of Switches made in CMOS technology are high Immunity to interference, low power consumption and large Temperature stability.
  • the locking device can also be a timer included that follow the first and second switches The delay time closes. As a timer can use inexpensive integrated circuits become.
  • the timer can be set in a particularly simple manner with a monostable multivibrator.
  • the computer system can be, for example, a Switch controlling output of the multivibrator the synchronization signals supplied to the delay device be switched to its unstable state. The output of the multivibrator in this state that the switches are opened and thus the synchronous signals are locked. After the delay time has expired, the Output of the multivibrator automatically in its stable State and closes the switches. The sync signals are now available to the data display device for screen construction to disposal.
  • the delay time can be advantageous can be set by a potentiometer.
  • the horizontal synchronous signal fed voltage supply provided, it can be connected to an external power supply or to a power supply in the form of a Battery are dispensed with. This lowers manufacturing and Operating costs and makes it easier to retrofit existing ones Computer systems with the switch-on delay device.
  • According to another aspect of the invention is a method specified for deactivating a visual display device.
  • FIG 1 illustrates a power-on delay device 10 is shown, the one Computer 12 connects to a data display device 14.
  • the Components shown in Figure 1 can be part of a system be used for example in a financial institution is used to transfer money automatically from a bank customer or have account debited.
  • the computer 12 can be a personal computer of known type be an interface 16 for connecting the data display device 14 has.
  • the computer 12 also includes one Controller 18, for example in the form of a pluggable graphics card, which the text and Graphic information prepared for the data display device 14.
  • the Controller 16 has a VGA graphics card that contains the text and graphics information converts into an analog signal and the Data display device 14 feeds, which in turn according to the VGA standard is working.
  • the data display device 14 includes a screen 20 an integrated input device 21, also touchscreen called, about which a bank customer by touching the Screen 20 can make entries.
  • the data display device 14 also has an input control 22, i.e. a touch controller to control the touch screen, and a power supply 22.
  • connection cable 26 In known systems there is one of the data display device 14 outgoing connection cable 26 directly to the interface 16 of the computer 12 connected. Usually done the connection between the connecting cable 26 and the interface 16 via a standardized plug connection.
  • the connecting cable 26 with one the usual 15-pin D-subminiature connector 28 the in a system according to the prior art in a corresponding connector receptacle 30 of the interface 16 of the computer 12 is inserted.
  • the system of Figure 1 is now distinguished from State of the art through the switch-on delay device 10 made between the computer 12 and the visual display device 14 is switched.
  • On the switch-on delay device 10 is one to the D-subminiature connector 28 of the connecting cable 26 matching plug receptacle 32 provided the same as the connector 30 of the interface 16 of the computer 12 can.
  • the D-subminiature connector 28 of the connection cable 26 is in the connector receptacle 32 of the switch-on delay device 10 inserted.
  • Connecting cable 26 of the data display device 14 is a connecting cable 34 via a D-subminiature connector 36 connected to the connector receptacle 30 of the interface 16.
  • the connecting cable 34 can be firmly attached to a housing Switch-on delay device 10 may be attached.
  • the VGA graphics card 18 generates several control signals, which are required for image display in the data display device 14 and of which only one horizontal synchronizing signal in FIG. 1 H-SYNC IN and a vertical sync signal V-SYNC IN are shown.
  • the sync signals H-SYNC IN, V-SYNC IN are connected via the connecting cable 34 of the switch-on delay device 10 fed there in the Starting phase of the computer in a manner to be described locked for a predetermined delay time and after Expiry of this delay time to the data display device 14 connected through.
  • Figure 1 are the through Synchronous signals labeled H-SYNC OUT and V-SYNC OUT. Coordinate the synchronization signals H-SYNC OUT and V-SYNC OUT the movement of an electron beam in one in figure 1 picture tube, not shown, of the data display device 14th
  • the data display device 14 has an energy saving function, as they are used in VGA monitors today is. If the data display device 14 registers the absence of the synchronous signals H-SYNC OUT and V-SYNC OUT, see above it is put into an idle state, for example by his screen 20 is darkened. The too For this purpose, apparatus precautions are required on the data display device 14 are known per se and are therefore not explained further here. It is essential that the data display device 14 in the manner just described the absence of the synchronous signals H-SYNC OUT and V-SYNC OUT responds.
  • FIG. 2 shows a possible circuit arrangement of the switch-on delay device 10, which shows that of the control 18 generated synchronous signals H-SYNC IN and V-SYNC IN after switching on or after a restart the computer 12 after the elapse of an adjustable Locking time is switched through to the data display device 14.
  • the 2 contains a functional unit, the power supply in a manner to be described the switch-on delay device 10 builds.
  • This functional unit consists of the resistors R1, R2, R3, R7, the diodes D1, D2, D3, the capacitors C1, C2, C3, and switch 40.
  • a timer 42 forms with the resistors R4, R6, the potentiometer R5 and capacitors C4 and C5 another Functional unit.
  • the timer 42 is in the explained embodiment by an integrated Circuit of the type ICM7555IBA given that as monostable Multivibrator is operated.
  • the rest in figure 2 listed and connected to the timer 42 Components are the resistors R8, R9, R10, the capacitor C6 and switches 44, 46 and 48. These too Components can essentially be used as a functional unit to be viewed as.
  • the switch 40 and further switches 44, 46, 48 are in a four-way switch 50 summarized.
  • the four-way switch 50 is made in CMOS technology and through an integrated circuit of the type HEF4066BT given.
  • the circuit arrangement according to Figure 2 contains also inputs 52, 54, 56 and outputs 58, 60, 62.
  • the inputs 52, 54, 56 are the connector receptacle 30 and the outputs 58, 60, 62 the D-subminiature connector 28 to assign to Figure 1.
  • the synchronization signals generated by the VGA graphics card 18 H-SYNC IN, V-SYNC IN become the on-delay device 10 fed via inputs 52 and 54, respectively.
  • the Input 56 and output 62 of the switch-on delay device 10 are grounded (GND).
  • the switch-on delay device 10 required voltage through the synchronization signals H-SYNC IN and V-SYNC IN can be provided on an external power supply or on a power supply in the form a battery can be dispensed with.
  • the synchronizing signals H-SYNC IN and V-SYNC IN are now switched on by switches 44, 46 the outputs 58 and 60 of the switch-on delay device 10 switched through and are thus the Data display device 14 available.
  • the switched through Synchronous signals are in Figure 2 with H-SYNC OUT and V-SYNC OUT designated. Finally, in the data display device 14 using the sync signals H-SYNC OUT and V-SYNC OUT the screen structure.
  • the delay time after which the as a monostable multivibrator operated timer 42, the switches 44, 46 closes via its output 3, corresponds to the blocking time, in which the screen 20 of the data display device 14 darkened after starting the operating system of the computer 10 is.
  • This delay time can be seen on the Set potentiometer R5, its resistance value, for example adjustable from the outside using a screwdriver is.
  • the delay time can be between 0.5 and 5 minutes can be set.
  • the invention is not limited to the circuit arrangement according to FIG. 2, which is only to be regarded as a special exemplary embodiment.
  • the dimensions of the components used in the circuit arrangement according to FIG. 2 are matched to the synchronous signals H-SYNC IN and V-SYNC IN, as are generated by the VGA graphics card 18.
  • R1 680 ⁇
  • R2 1.8 k ⁇
  • R3 22 k ⁇
  • R4 22 k ⁇
  • R6 1M ⁇
  • R7 100 k ⁇
  • R8 1M ⁇
  • R9 100 k ⁇
  • R10 1.8k ⁇
  • C4 100 ⁇ F / 10V
  • C5 100nF / 50V
  • C6 100nF / 50V.
  • the capacitors C2 and C4 are electrolytic capacitors with the polarity indicated in Figure 2. As diodes D1 and D2 become BAR43S diodes and one as diode D3 BAR42 diode used.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Sources (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Studio Circuits (AREA)
  • Synchronizing For Television (AREA)

Claims (11)

  1. Dispositif de temporisation de mise en marche (10) pour un appareil de visualisation de données (14) qui peut être mis dans un état de repos par le blocage d'au moins un signal (H-SYNC IN, V-SYNC IN) commandant l'appareil de visualisation de données (14), comportant
    au moins une entrée (52, 54) qui est reliée à un dispositif de commande (18) lui envoyant le signal (H-SYNC IN, V-SYNC IN),
    un dispositif de blocage (42, 44, 46) qui bloque le signal (H-SYNC IN, V-SYNC IN) pour une durée de temporisation prédéterminée,
    et au moins une sortie (58, 60) qui est reliée à l'appareil de visualisation de données (14) et qui envoie à celui-ci le signal (H-SYNC OUT, V-SYNC OUT) après l'expiration de la durée de temporisation.
  2. Dispositif de temporisation de mise en marche (10) selon la revendication 1, caractérisé par le fait que le dispositif de blocage contient au moins deux interrupteurs (44, 46), un premier interrupteur (44) reliant une première entrée (52), à laquelle un signal de synchronisation horizontale (H-SYNC IN) est envoyé par le dispositif de commande, à une première sortie (58) et un deuxième interrupteur (46) reliant une deuxième entrée (54), à laquelle un signal de synchronisation verticale (V-SYNC IN) est envoyé par le dispositif de commande, à une deuxième sortie (60).
  3. Dispositif de temporisation de mise en marche (10) selon la revendication 2, caractérisé par le fait que les interrupteurs (44, 46) sont sous la forme d'interrupteurs CMOS.
  4. Dispositif de temporisation de mise en marche (10) selon la revendication 2 ou 3, caractérisé par le fait que le dispositif de blocage contient un circuit temporisateur (42) qui ferme le premier et le deuxième interrupteur (44, 46) après l'expiration de la durée de temporisation.
  5. Dispositif de temporisation de mise en marche (10) selon la revendication 4, caractérisé par le fait que le circuit temporisateur (42) est une bascule monostable.
  6. Dispositif de temporisation de mise en marche (10) selon la revendication 4 ou 5, caractérisé par un potentiomètre (R5) branché du côté amont du circuit temporisateur (42) pour régler la durée de temporisation.
  7. Dispositif de temporisation de mise en marche (10) selon l'une des revendications 2 à 6, caractérisé par une alimentation en tension alimentée par le signal de synchronisation horizontale (H-SYNC IN).
  8. Dispositif de temporisation de mise en marche (10) selon la revendication 7, caractérisé par le fait que l'alimentation en tension a des moyens (D1 à D3, C1 à C3) pour redresser et lisser le signal de synchronisation horizontale (H-SYNC IN).
  9. Dispositif de temporisation de mise en marche (10) selon l'une des revendications précédentes, caractérisé par le fait qu'il est fabriqué dans la technique des composants montés en surface.
  10. Dispositif de temporisation de mise en marche (10) selon l'une des revendications précédentes pour un appareil de visualisation de données VGA.
  11. Procédé pour désactiver un appareil de visualisation de données (14) qui peut être mis dans un état de repos par le blocage d'au moins un signal (H-SYNC IN, V-SYNC IN) commandant l'appareil de visualisation de données (14), le signal (H-SYNC IN, V-SYNC IN) produit par un dispositif de commande (18) étant bloqué pour une durée de temporisation prédéterminée, caractérisé par le fait qu'on libère le signal (H-SYNC IN, V-SYNC IN) après l'expiration de la durée de temporisation et on l'envoie à l'appareil de visualisation de données (14).
EP98962202A 1997-11-20 1998-11-03 Système de temporisation de mise en marche et méthode pour la désactivation d'un dispositif de visualisation Expired - Lifetime EP1031128B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19751577 1997-11-20
DE19751577 1997-11-20
PCT/DE1998/003202 WO1999027516A1 (fr) 1997-11-20 1998-11-03 Systeme de temporisation de mise en marche pour dispositif de visualisation

Publications (2)

Publication Number Publication Date
EP1031128A1 EP1031128A1 (fr) 2000-08-30
EP1031128B1 true EP1031128B1 (fr) 2002-03-06

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EP98962202A Expired - Lifetime EP1031128B1 (fr) 1997-11-20 1998-11-03 Système de temporisation de mise en marche et méthode pour la désactivation d'un dispositif de visualisation

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US (1) US6239717B1 (fr)
EP (1) EP1031128B1 (fr)
AT (1) ATE214190T1 (fr)
DE (1) DE59803302D1 (fr)
WO (1) WO1999027516A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064765B2 (en) * 2002-06-24 2006-06-20 Hewlett-Packard Development Company, L.P. System and method for grabbing frames of graphical data
JP4657174B2 (ja) * 2006-08-25 2011-03-23 京セラ株式会社 表示機器
DE202008005537U1 (de) 2008-03-17 2008-07-24 Maxdata International Gmbh Monitor für einen PC und mit mindestens einem Steckverbinder für ein Videosignal

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960004651B1 (ko) * 1990-06-18 1996-04-11 세이꼬 엡슨 가부시끼가이샤 플랫 표시장치 및 표시체 구동장치
US5148153A (en) * 1990-12-20 1992-09-15 Motorola Inc. Automatic screen blanking in a mobile radio data terminal
ES2078818T3 (es) * 1992-01-31 1995-12-16 Siemens Nixdorf Inf Syst Unidad funcional electrica y pantalla con tubo catodico conmutable en estados para el ahorro de energia.
US5389952A (en) 1992-12-02 1995-02-14 Cordata Inc. Low-power-consumption monitor standby system
US5375245A (en) * 1993-02-22 1994-12-20 Tandberg Data A/S Apparatus for automatically reducing the power consumption of a CRT computer monitor
US5414863A (en) * 1993-04-02 1995-05-09 Cirrus Logic, Inc. Power control staggering circuit for powering different components at different delay timings
DE9409987U1 (de) 1994-06-21 1994-08-11 Soe Oppermann & Elna Gmbh Automatische Abschalteinrichtung für Computermonitore
TW421772B (en) * 1996-07-11 2001-02-11 Samsung Electronics Co Ltd Cathode ray tube display apparatus
US5801635A (en) 1997-02-14 1998-09-01 Price; Glenn L. Power interruption detector

Also Published As

Publication number Publication date
ATE214190T1 (de) 2002-03-15
WO1999027516A1 (fr) 1999-06-03
EP1031128A1 (fr) 2000-08-30
DE59803302D1 (de) 2002-04-11
US6239717B1 (en) 2001-05-29

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