EP1011801A1 - Reference de tension compensee en courant et en temperature - Google Patents

Reference de tension compensee en courant et en temperature

Info

Publication number
EP1011801A1
EP1011801A1 EP98902622A EP98902622A EP1011801A1 EP 1011801 A1 EP1011801 A1 EP 1011801A1 EP 98902622 A EP98902622 A EP 98902622A EP 98902622 A EP98902622 A EP 98902622A EP 1011801 A1 EP1011801 A1 EP 1011801A1
Authority
EP
European Patent Office
Prior art keywords
voltage
circuit
volts
amplifier
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98902622A
Other languages
German (de)
English (en)
Inventor
Terrence L. Apartment A 23 MARSHALL
Suneel Arora
Michael W. Dooley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cardiac Pacemakers Inc
Original Assignee
Cardiac Pacemakers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cardiac Pacemakers Inc filed Critical Cardiac Pacemakers Inc
Publication of EP1011801A1 publication Critical patent/EP1011801A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/362—Heart stimulators
    • A61N1/37—Monitoring; Protecting
    • A61N1/3706—Pacemaker parameters

Definitions

  • This invention relates generally to precision voltage and current references.
  • an analog-to-digital converter typically requires a precise voltage reference to establish and quantize an analog input voltage range.
  • analog filters such as transconductance-capacitance (g m C) filters, have filter gain and rolloff frequency characteristics that depend upon their bias currents.
  • a precise current reference is useful for generating accurate bias currents in such filters and other circuits.
  • the present invention provides a system that includes current and temperature compensated voltage reference that is capable of operating from a power supply voltage as low as approximately 1.3 Volts.
  • operation at lower power supply voltages offers significant advantages; it may eliminate the need for electrically coupling more than one battery in series in order to obtain a higher power supply voltage.
  • an internal battery impedance increases over the course of the battery life, thereby reducing the voltage available at the battery terminals.
  • the useful life of the battery may be extended by using a reference circuit that is capable of operating from this reduced battery terminal voltage near the end of the battery's life.
  • cardiac rhythm management systems such as pacemakers and defibrillators
  • circuits that are capable of operating at reduced power supply voltages can extend battery life for several years, thereby avoiding surgical explantation and replacement of the implanted device.
  • cardiac rhythm management systems such as pacemakers and defibrillators
  • circuits that are capable of operating at reduced power supply voltages can extend battery life for several years, thereby avoiding surgical explantation and replacement of the implanted device.
  • cardiac rhythm management systems such as pacemakers and defibrillators
  • the system by operating from a power supply voltage as low as approximately 1.3 Volts, may significantly increase the longevity of the implanted device.
  • the system also operates with less power consumption, further increasing the longevity of the implanted device.
  • the increased device longevity provides the implanting physician with more options in selecting the most appropriate therapy for the patient. Discomfort and patient mortality due to explantation and replacement of the implanted medical device may be decreased.
  • the system also provides a reference circuit in which the value of the reference voltage and reference current are capable of fine adjustment.
  • the resulting reference voltage is temperature compensated, i.e. the sensitivity of the reference voltage to temperature variations is reduced.
  • the system also provides a method of generating a temperature compensated reference voltage.
  • a voltage difference is measured between first and second bias circuits, each having different temperature dependencies and each having a voltage drop of less than that of three series-coupled diodes.
  • a temperature dependent reference current is generated from the voltage difference.
  • a current proportional to the reference current is applied to a third bias circuit to establish a first voltage.
  • the first voltage has a temperature dependence that substantially offsets the temperature dependence of a second voltage in series with the first voltage to provide the temperature compensated reference voltage.
  • the system provides a current reference circuit comprising a first and second bias circuits and a first amplifier.
  • the first bias circuit has a first temperature dependence, and includes less than three series- coupled diodes.
  • the second bias circuit has a second temperature dependence, different from the first temperature dependence, and also includes less than three series-coupled diodes.
  • the first amplifier has first and second inputs electrically coupled to the respective first and second bias circuits.
  • the first amplifier also has an output providing a temperature dependent reference current in response thereto.
  • the system also provides a voltage reference circuit, including a third bias circuit and a second amplifier.
  • the third bias circuit is electrically coupled for receiving a current proportional to the reference current and providing a temperature compensated reference voltage in response thereto.
  • the received current which is proportional to the reference current, establishes a first voltage having a temperature dependence that substantially offsets the temperature dependence of a second voltage that is in series with the first voltage, thereby providing the temperature compensated reference voltage.
  • a second amplifier is electrically coupled to the first and third bias circuits for stabilizing the reference voltage and providing a load current.
  • Figure 1 is a schematic illustration of a reference circuit including a current reference circuit and a voltage reference circuit.
  • FIG. 2 is a more detailed schematic illustration of the current reference circuit of Figure 1.
  • Figure 3 is a more detailed schematic illustration of the voltage reference circuit of Figure 1.
  • Figure 4 is a schematic/block diagram illustrating one embodiment of the system in which the reference circuit is used in a cardiac rhythm management system.
  • Figure 1 is a schematic illustration of one embodiment of the system providing a silicon integrated circuit (IC) reference circuit 300 including current reference circuit 305 and voltage reference circuit 310, each receiving a power supply voltage V DD at power supply node 315 and a ground voltage V ss at ground voltage node 320.
  • Current reference circuit 305 provides an internal reference current, as discussed below, and provides a voltage at node 325 from which a current proportional to the reference current can be generated in voltage reference circuit 310.
  • Current reference circuit 305 is capable of providing a current proportional to the reference current through node 330.
  • Current reference circuit 305 also provides through node 335 a first bias voltage to voltage reference circuit 310 for biasing an amplifier input therein.
  • Current reference circuit 305 also provides through node 336 a fourth bias voltage to voltage reference circuit 310 for biasing current mirrors therein.
  • Voltage reference circuit 310 provides a reference voltage at node 340.
  • FIG. 2 is a more detailed schematic illustration of one embodiment of current reference circuit 305.
  • current reference circuit 305 comprises first amplifier 350, first bias network 355, second bias network 360, and startup circuit 365.
  • First bias network 355 includes two series-coupled diodes 366 and 367, implemented as base-emitter (BE) junctions of bipolar junction transistors (BJTs), each BJT receiving an independent collector-emitter current, I CE , as described below.
  • Second bias network 360 includes two series- coupled diodes 368 and 369, implemented as BE junctions of BJTs, each BJT receiving an independent I CE , as described below.
  • Second bias network 360 also includes first resistor 370 in series with the two series-coupled diodes, 368 and 369, therein.
  • the BE junction areas of the diodes 368 and 369 in the second bias network 360 are different from the BE junction areas of the diodes 366 and 367 in the first bias network 355.
  • the BE junction areas of the diodes 368 and 369 in the second bias network 360 are made four times larger than the BE junction areas of the diodes 366 and 367 in the first bias network 355.
  • Each of the diodes 368 and 369 is implemented as four parallel-connected BJT's of the same area as the single BJT's that implement the diodes 366 and 367.
  • Other BE junction area ratios and connection configurations could also be used without departing from the scope and spirit of the present invention.
  • Substantially identical I CE currents are provided to each of diodes 366, 367, 368, and 369. Since diodes 368 and 369 in second bias circuit 360 each have four times larger BE junction area than each of diodes 366 and 367 in first bias circuit 355, diodes 368 and 369 in second bias circuit 360 each have approximately one fourth the current density of diodes 366 and 367 in first bias circuit 355, as a result of the substantially identical I CE currents.
  • First bias network 355 provides at node 335 to a first input of first amplifier 350 the first bias voltage having a first temperature dependence resulting from the two series-coupled diodes, 366 and 367, therein.
  • Second bias network 360 provides across its two series-coupled diodes, 368 and 369, a second bias voltage, having a second temperature dependence, at node 380, which is coupled through first resistor 370 to the output and the second input at node 385 of first amplifier 350.
  • First amplifier 350 measures the voltage difference, at nodes 335 and 385, between the first and second bias networks 355 and 360, providing in response thereto a reference current, I PTAT , through first resistor 370, that is proportional to absolute temperature (PTAT).
  • I PTAT reference current
  • Equation (1) The value of I PTAT is illustrated by Equation (1).
  • first resistor 370 is a variable or trimmable resistor having an adjustable resistance value R 370 near approximately 1.482 megaohms for adjusting reference current AT to 50 nA at 37 degrees Celsius, or other fine adjustment to a desired value at a particular temperature.
  • the first bias voltage at node 335, the fourth bias voltage at node 336, and a voltage at node 325 from which reference current I PTAT is generated by output transconductor 390 of first amplifier 350, are each provided to voltage reference circuit 310.
  • the voltage at node 325, from which reference current I PTAT is generated, is also provided to startup circuit 365 and to each of current mirror p-channel field-effect transistors PFETs 391-395.
  • Current mirror PFETs 391-393 provide a I CE currents, proportional to reference current, I PTAT , to respective diodes 366-368.
  • Output transconductor PFET 390 of first amplifier 350 provides the reference current, I PTAT , as the I CE current of diode 369.
  • Current mirror PFET 394 provides a current, proportional to reference current I PTAT , to diode-connected transistor 395, which generates the fourth bias voltage at node 336 in response thereto.
  • the fourth bias voltage at node 336 is also provided to first amplifier 350 for biasing the gate terminals of current mirror n-channel field-effect transistors (NFETs) 415-417 contained therein.
  • Current mirror PFET 395 is optionally included for providing a bias current at node 330, such as to another circuit on the integrated circuit. Other current mirror PFETs may similarly be used to provide other bias current sources to other circuits.
  • first amplifier 350 is a folded cascode amplifier that is carefully designed to operate from a reduced power supply voltage V DD at power supply node 315, such as a power supply voltage V DD as low as approximately 1.3 Volts, when biased by first and second bias circuits, 355 and 360.
  • reference circuit 300 can operate at a reduced power supply voltage V DD , such as, for example, a voltage approximately between 1.3 Volts and 3.25 Volts provided by a single lithium-silver vanadium pentoxide battery cell in an implantable defibrillator.
  • V DD reduced power supply voltage
  • reference circuit 300 is operated from a power supply voltage V DD approximately between 1.65 Volts and 3.25 Volts.
  • V DD is particularly advantageous for battery powered electronics devices, such as portable electronics or implantable electronics, but operation at higher values of power supply voltage V DD is also possible.
  • Folded cascode first amplifier 350 comprises source-coupled input NFETs 400 and 401, having respective gate terminals electrically coupled to the first and second bias circuits 355 and 360.
  • the drain terminals of input NFETs 400 and 401 are respectively coupled to the drain terminals of load PFETs 405 and 406, the source terminals of which are electrically coupled to power supply node 315.
  • Cascode PFETs 410 and 411 are each electrically coupled at their respective source terminals to the drain terminals of respective load PFETs 405 and 406.
  • the drain terminals of cascode PFETs 410 and 411 are respectively electrically coupled to drain terminals of current mirror NFETs 415 and 416 at respective nodes 325 and 420.
  • Current mirror NFET 417 is electrically coupled at its drain terminal to the source terminals of each of input NFETs 400 and 401.
  • the source terminals of each of current mirror NFETs 415 -417 are coupled to ground node 320.
  • cascode PFET 411 are coupled to node 420, with cascode PFET 411 being diode-connected, i.e. the gate and drain terminals of cascode PFET 411 are both connected to node
  • Output transconductor 390 is a PFET having a gate terminal electrically coupled to node 325, a source terminal electrically coupled to power supply node
  • first amplifier 350 In order to obtain the above-described operation at reduced power supply voltages V DD , first amplifier 350 must be carefully designed and biased.
  • input NFETs 400 and 401 are sized for operation in the weak inversion region.
  • Current mirror NFETs 415-417 and load PFETs 405 and 406 are sized for operation in the moderate inversion region, i.e. between the weak inversion and strong inversion regions.
  • Cascode PFETs 410 and 411 are sized for operation in the weak inversion region., and more particularly, cascode PFETs 410 and 411 are sized for operation at much lower current densities than load PFETs 405 and 406.
  • current density J is determined from: the current I through the FET, L is the length of the FET between its drain and source regions, and W is the width of the FET in a direction transverse to the current flow between the drain and source regions.
  • the dimensions, L and W, and bias currents, I, in the cascode PFETs 410 and 411 and load PFETs 405 and 406 are designed such that the load PFETs 405 and 406 have approximately between six and seven hundred times the current density J as in the cascode PFETs 410 and 411.
  • first amplifier 350 i.e.
  • first amplifier 350 advantageously operates at a lower power supply voltage V DD than, for example, a conventional differential amplifier having a current mirror load.
  • V DD m ⁇ n The minimum power supply voltage, V DD m ⁇ n needed to operate first amplifier 350 is illustrated in Equation (3).
  • the minimum supply voltage, V DD m ⁇ n is determined from: the BE voltage of diode 366, V 366 , of approximately 0.5 Volts; the BE voltage of diode 367, V 367 , of approximately 0.5 Volts; the process minimum threshold voltage of input NFET 400 of approximately 0.5 Volts; the minimum drain-source voltage, ⁇ V 400 , of approximately 0.1 Volts to keep input NFET 400 out of the nonsaturation/linear/triode region of operation; and, the minimum drain-source voltage, ⁇ V 405 , required to keep load FET 405 out of the nonsaturation/linear/triode region of operation, or approximately 0.2 Volts.
  • first amplifier 350 is capable of operating from a minimum power supply voltage, V DD m ⁇ n , as low as approximately 0.8 Volts, for this biasing arrangement.
  • the minimum power supply voltage, V DD min needed for operation of the current reference circuit 305 is not limited by the minimum power supply voltage needed for operation of first amplifier 305.
  • the minimum power supply voltage needed for operation of current reference circuit 305 is either limited by the voltage requirements of first bias circuit 355 and its associated current mirror PFET 392, or similarly limited by the voltage requirement of second bias circuit 360 and output transconductor PFET 390.
  • the voltage requirement of first bias circuit 355 and associated current mirror PFET 392 is illustrated in Equation (4).
  • the minimum power supply voltage, V DD min is determined from: the BE voltage of diode 366, V 366 , of approximately 0.5 Volts; the BE voltage of diode 367, V 367 , of approximately 0.5 Volts; and, the minimum drain-source voltage, ⁇ V 392 , required to keep current mirror PFET 392 out of the nonsaturation/linear/triode region of operation, or approximately 0.25 Volts.
  • current reference circuit 305 is capable of operating from a minimum power supply voltage, V DD min , as low as approximately 1.3 Volts for this biasing arrangement.
  • current reference circuit 305 is operated from a power supply voltage V DD that is approximately equal to 1.3 Volts. In another embodiment, current reference circuit 305 is operated at a higher power supply voltage V DD , such as at approximately between 1.65 Volts and 3.25 Volts. It is also understood that current reference circuit 305 may be operated at even higher power supply voltages V DD .
  • Startup circuit 365 is designed to establish a voltage at node 325 that turns on output transconductor PFET 390 and current mirror PFETs 391-394 such that these devices provide bias current to first and second bias circuits 355 and 360 and first amplifier 350. Startup circuit 365 is also designed to release control over the voltage at node 325 when current reference circuit 350 operates as described in Equation (1).
  • Startup circuit 365 comprises PFET 500, NFET 505, and pnp BJT 510.
  • PFET 500 has a source terminal that is electrically coupled to power supply node 315, a gate terminal that is electrically coupled to node 325, and a drain terminal that is electrically coupled to the drain terminal of NFET 505 at node 515.
  • NFET 505 has a gate terminal electrically coupled to power supply node 315 and a source terminal that is electrically coupled to ground node 320.
  • BJT 510 has an emitter terminal that is electrically coupled to node 325, a base terminal that is electrically coupled to node 515, and a collector terminal that is electrically coupled to ground node 320.
  • PFET 500 When power is initially applied to power supply node 315, there is initially no charge on capacitor 520, hence the voltage at node 325 is approximately equal to the voltage at power supply node 315.
  • PFET 500 is turned off due to insufficient voltage between its gate and source terminals at nodes 325 and 315, respectively.
  • NFET 505 is turned on, since the voltage between its gate terminal, at power supply node 315, and its source terminal, at ground node 320, is approximately equal to the power supply voltage V DD .
  • the voltage at node 515 is a diode voltage drop below the voltage at node 325, which is approximately equal to the voltage at power supply node 315.
  • NFET 505 operates in a saturation region, and provides base current to BJT 510.
  • the collector-emitter current, I CE , of BJT 510 charges capacitor 520 to decrease the voltage at node 325 from its initial value at approximately V DD until PFET 500, output transconductor PFET 390, and current mirror PFETs 391-395 turn on.
  • current reference circuit 305 establishes operation at the stable operating point described in Equation (1).
  • PFET 500 is designed to source more current than NFET 505 can sink under all process and supply voltage variations, hence the voltage of node 515 is increased to V DD , and BJT 510 turns off.
  • NFET 505 remains on, but is sized to draw an acceptably low quiescent current in this second state.
  • FIG 3 is a more detailed schematic illustration of the voltage reference circuit 310 of Figure 1.
  • voltage reference circuit 310 comprises a second amplifier 600 and a third bias circuit 605.
  • Second amplifier 600 receives at a first input at node 335 the first bias voltage, which is two series-coupled diode voltage drops above the voltage at ground node 320.
  • Second amplifier 600 is connected in a negative feedback configuration, i.e. the output of second amplifier 600 is coupled to the inverting second input, at node 610, of second amplifier 600, through third bias circuit 605.
  • Second amplifier 600 is connected in a negative feedback configuration, a "virtual ground" exists between the first input, at node 335, and the second input, at node 610, of second amplifier 600, thereby providing a voltage approximately equal to the first bias voltage at its second input at node 610.
  • the voltage at node 610 is approximately equal to two series-coupled diode voltage drops above the voltage at ground node 320.
  • Third bias circuit 605 comprises second resistor 620, in series with diode 611, which is implemented as a BJT biased with a collector- emitter current, I CE , received from current mirror PFET 613 having a gate terminal electrically coupled to node 325.
  • the BE voltage of diode 611 offsets the voltage at node 610 from a second voltage at node 615, such that the resulting second voltage at node 615 is approximately one diode voltage drop above the voltage at ground node 320.
  • the temperature dependence of the second voltage at node 615 is substantially offset by the temperature dependence of a first voltage across resistor 620, which is created by the temperature dependent current provided by current mirror NFET 617.
  • the resistance of second resistor 620 is such that the resulting voltage at node 340 is approximately equal to the bandgap voltage of silicon, i.e. approximately 1.25 Volts, the resulting voltage at node 340 is approximately temperature compensated.
  • second resistor 620 is a variable or trimmable resistor having an adjustable resistance value near approximately 7.0 megaohms for adjusting the reference voltage at node 340 to 1.25 Volts with the desired degree of accuracy.
  • Second amplifier 600 is a folded-cascode amplifier designed and operating similarly to first amplifier 350, which was discussed in detail above.
  • Second amplifier 600 comprises: input NFETs 700 and 701; load PFETs 705 and 706 ; output transconductor NFET 720 ; cascode PFETs 710 and 711; and, current mirror NFETS 730-733.
  • second amplifier 600 is output compensated, i.e. its low frequency pole is determined, in part, by capacitor 800.
  • Gain degeneration resistor 810 electrically coupling the common source terminals of load PFET 706 and output transconductor PFET 720 to the power supply node 315, and capacitor 820 provide improved frequency response characteristics of second amplifier 600.
  • Second amplifier 600 stabilizes the reference voltage at node 340 and provides a load current to any other circuits that are electrically coupled to thereto.
  • V DD m ⁇ n The minimum power supply voltage, V DD m ⁇ n , needed for operation of the voltage reference circuit 310 is illustrated by Equation (5).
  • the minimum power supply voltage, V DD min needed for operation of the voltage reference circuit 310 is approximately limited by: the value of the reference voltage at node 340, V 340 , of approximately 1.25 Volts; the minimum drain-source voltage needed for operation of output transconductor NFET 720 in the saturation region, ⁇ V 720 , of approximately 0.175 Volts; and, the voltage V g]0 , across resistor 810, which is negligible.
  • the resulting minimum power supply voltage, V DD ⁇ min needed is approximately 1.45 Volts, however, as will be shown, simulation data indicates that voltage reference circuit 310 is capable of operating at an even lower power supply voltage V DD> min .
  • Table 1 illustrates the performance of reference circuit 300, as obtained from a circuit simulation performed using the HSPICE Version H96.1 circuit simulator from Metasoftware, Inc., of Campbell, CA.
  • Table 1 Operation of Reference Circuit 300 At Various Power Supply Voltages
  • current reference circuit 305 and voltage reference circuit 310 are capable of operating together from a power supply voltage V DD that is even lower than the 1.45 Volts yielded by Equation (5), such as a minimum power supply voltage V DD min that is approximately equal to 1.3 Volts.
  • current reference circuit 305 and voltage reference circuit 310 are operated from a power supply voltage V DD of approximately 1.3 Volts.
  • a power supply voltage V DD approximately between 1.65 Volts and 3.25 Volts is used to ensure proper operation of current reference circuit 305 and voltage reference circuit 310.
  • an even higher power supply voltage V DD could also be used.
  • FIG 4 is a schematic/block diagram illustrating one embodiment of the system in which reference circuit 300 is used in a cardiac rhythm management system such as implantable cardioverter-defibrillator (ICD) 900.
  • ICD 100 includes a single lithium-silver vanadium pentoxide battery 905, providing the power supply voltage V DD at node 315 to reference circuit 300, and providing the ground voltage V ss at node 320 to reference circuit 300 and other electronics 910.
  • Reference circuit 300 provides the reference voltage at node 340 and a current proportional to the reference current I PTAT , through node 330, to electronics 910.
  • the power supply voltage V DD provided by battery 905 is approximately equal to 3.25 Volts during time periods in which ICD 900 is monitoring a patient's heart.
  • the power supply voltage V DD provided by the battery may drop to between approximately 1.65 Volts and 3.25 Volts while charging capacitors for providing an electrical defibrillation countershock to restore the patient's heart to a normal rhythm.
  • reference circuit 300 offers significant advantages; it may eliminate the need for electrically coupling more than one battery in series in order to obtain a higher power supply voltage. Also, in some batteries, an internal battery impedance increases over the course of the battery life, thereby reducing the voltage available at the battery terminals when appreciable currents are drawn therefrom. Thus, the useful life of the battery may be extended by using a reference circuit that is capable of operating from this reduced battery terminal voltage near the end of the battery's life. This is particularly true for implantable medical devices such as pacemakers and defibrillators. For example, a pacemaker may draw appreciable currents from the battery during the charging of a capacitor for the subsequent delivery of an electrical pacing pulse.
  • a defibrillator may draw appreciable currents from the battery during the charging of a capacitor for the subsequent delivery of an electrical defibrillation countershock.
  • Circuits that are capable of operating at reduced power supply voltages can extend battery life for several years, thereby avoiding surgical explantation and replacement of the implanted device. In elderly patients, such traumatic surgical intervention may be both uncomfortable and risky.
  • the system by operating from a power supply voltage as low as approximately 1.3 Volts, may significantly increase the longevity of the implanted device in which it is used. The system also operates with low power consumption, further enhancing the longevity of the implanted device. The increased device longevity provides the implanting physician with more options in selecting the most appropriate therapy for the patient.
  • the system also provides a reference circuit in which the value of the reference voltage and reference current are capable of fine adjustment. Furthermore, the resulting reference voltage is temperature compensated, i.e. the sensitivity of the reference voltage to temperature variations is reduced.

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Abstract

Circuit à référence de tension compensée en courant et en température, fonctionnant avec une tension d'alimentation basse qui descend jusqu'à environ 1,3 V. Un circuit à référence de courant utilise un amplificateur cascode replié pour mesurer les tensions dépendant de la température fournies par des premier et second circuits de polarisation, chacun d'entre eux comprenant deux diodes en série ou transistors à jonction bipolaire montés en diode, et il fournit en réponse à ces dispositifs un courant en température proportionnelle à absolue (PTAT). Un circuit à référence de tension utilise un courant de type PTAT via une résistance pour établir une tension de type PTAT en série avec une tension de diode, et la valeur de la résistance est adaptée jusqu'à ce que la somme des tensions en question équivale approximativement à la tension de la barrière de potentiel du silicium. Il en résulte une référence de tension compensée en température. Le circuit de référence considéré est utilisable avec un système implantable de gestion du rythme cardiaque ayant une pile qui fournit une tension d'alimentation approximativement comprise entre 1,3 et 3,25 V.
EP98902622A 1997-01-29 1998-01-16 Reference de tension compensee en courant et en temperature Withdrawn EP1011801A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US79047097A 1997-01-29 1997-01-29
US790470 1997-01-29
PCT/US1998/000954 WO1998032490A1 (fr) 1997-01-29 1998-01-16 Reference de tension compensee en courant et en temperature

Publications (1)

Publication Number Publication Date
EP1011801A1 true EP1011801A1 (fr) 2000-06-28

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Country Status (3)

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EP (1) EP1011801A1 (fr)
CA (1) CA2278498A1 (fr)
WO (1) WO1998032490A1 (fr)

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US6292050B1 (en) * 1997-01-29 2001-09-18 Cardiac Pacemakers, Inc. Current and temperature compensated voltage reference having improved power supply rejection
CN110247645B (zh) * 2019-05-24 2023-06-06 广州金升阳科技有限公司 一种电压比较器
CN117492507B (zh) * 2023-10-19 2024-10-22 合肥芯谷微电子股份有限公司 一种二阶补偿低温度系数基准电压集成电路

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CN110752838B (zh) * 2019-11-11 2023-10-31 上海联影医疗科技股份有限公司 串联二极管电路

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CA2278498A1 (fr) 1998-07-30

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