EP0995227A4 - A controlled cleavage process - Google Patents

A controlled cleavage process

Info

Publication number
EP0995227A4
EP0995227A4 EP98924756A EP98924756A EP0995227A4 EP 0995227 A4 EP0995227 A4 EP 0995227A4 EP 98924756 A EP98924756 A EP 98924756A EP 98924756 A EP98924756 A EP 98924756A EP 0995227 A4 EP0995227 A4 EP 0995227A4
Authority
EP
European Patent Office
Prior art keywords
cleavage process
controlled cleavage
controlled
cleavage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98924756A
Other languages
German (de)
French (fr)
Other versions
EP0995227A1 (en
Inventor
Francois J Henley
Nathan W Cheung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Genesis Corp
Original Assignee
Silicon Genesis Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/026,115 external-priority patent/US6155909A/en
Application filed by Silicon Genesis Corp filed Critical Silicon Genesis Corp
Publication of EP0995227A1 publication Critical patent/EP0995227A1/en
Publication of EP0995227A4 publication Critical patent/EP0995227A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
    • B26D3/00—Cutting work characterised by the nature of the cut made; Apparatus therefor
    • B26D3/28—Splitting layers from work; Mutually separating layers by cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
    • B26F3/00—Severing by means other than cutting; Apparatus therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
    • B26F3/00—Severing by means other than cutting; Apparatus therefor
    • B26F3/002—Precutting and tensioning or breaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Forests & Forestry (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
EP98924756A 1997-05-12 1998-05-11 A controlled cleavage process Withdrawn EP0995227A4 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US4627697P 1997-05-12 1997-05-12
US46276P 1997-05-12
US09/026,115 US6155909A (en) 1997-05-12 1998-02-19 Controlled cleavage system using pressurized fluid
US09/026,027 US5994207A (en) 1997-05-12 1998-02-19 Controlled cleavage process using pressurized fluid
US26115 1998-02-19
PCT/US1998/009567 WO1998052216A1 (en) 1997-05-12 1998-05-11 A controlled cleavage process
US26027 2001-12-20

Publications (2)

Publication Number Publication Date
EP0995227A1 EP0995227A1 (en) 2000-04-26
EP0995227A4 true EP0995227A4 (en) 2000-07-05

Family

ID=27362676

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98924756A Withdrawn EP0995227A4 (en) 1997-05-12 1998-05-11 A controlled cleavage process

Country Status (6)

Country Link
EP (1) EP0995227A4 (en)
JP (1) JP2001525991A (en)
CN (1) CN1146973C (en)
AU (1) AU7685198A (en)
CA (1) CA2290104A1 (en)
WO (1) WO1998052216A1 (en)

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SG87916A1 (en) 1997-12-26 2002-04-16 Canon Kk Sample separating apparatus and method, and substrate manufacturing method
US6383890B2 (en) 1997-12-26 2002-05-07 Canon Kabushiki Kaisha Wafer bonding method, apparatus and vacuum chuck
US6540861B2 (en) * 1998-04-01 2003-04-01 Canon Kabushiki Kaisha Member separating apparatus and processing apparatus
JP2000349264A (en) 1998-12-04 2000-12-15 Canon Inc Method for manufacturing, use and utilizing method of semiconductor wafer
JP4365920B2 (en) * 1999-02-02 2009-11-18 キヤノン株式会社 Separation method and semiconductor substrate manufacturing method
US6468923B1 (en) 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
FR2795865B1 (en) * 1999-06-30 2001-08-17 Commissariat Energie Atomique METHOD FOR MAKING A THIN FILM USING PRESSURIZATION
FR2796491B1 (en) 1999-07-12 2001-08-31 Commissariat Energie Atomique METHOD FOR TAKING OFF TWO ELEMENTS AND DEVICE FOR IMPLEMENTING SAME
FR2797347B1 (en) * 1999-08-04 2001-11-23 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN FILM HAVING A SURFRAGILILIZATION STEP
JP2003506883A (en) * 1999-08-10 2003-02-18 シリコン ジェネシス コーポレイション Cleavage process for manufacturing multi-layer substrates with low implant dose
US6653209B1 (en) 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
FR2809867B1 (en) * 2000-05-30 2003-10-24 Commissariat Energie Atomique FRAGILE SUBSTRATE AND METHOD FOR MANUFACTURING SUCH SUBSTRATE
FR2811807B1 (en) * 2000-07-12 2003-07-04 Commissariat Energie Atomique METHOD OF CUTTING A BLOCK OF MATERIAL AND FORMING A THIN FILM
JP2002075917A (en) 2000-08-25 2002-03-15 Canon Inc Device and method for separating sample
FR2817395B1 (en) 2000-11-27 2003-10-31 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SUBSTRATE, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED THEREBY
FR2818010B1 (en) * 2000-12-08 2003-09-05 Commissariat Energie Atomique METHOD OF MAKING A THIN LAYER INVOLVING THE INTRODUCTION OF GAS SPECIES
FR2819099B1 (en) * 2000-12-28 2003-09-26 Commissariat Energie Atomique METHOD FOR PRODUCING A STACKED STRUCTURE
JP4803884B2 (en) * 2001-01-31 2011-10-26 キヤノン株式会社 Method for manufacturing thin film semiconductor device
JP2002305293A (en) 2001-04-06 2002-10-18 Canon Inc Method of manufacturing semiconductor member, and method of manufacturing semiconductor device
US6770966B2 (en) * 2001-07-31 2004-08-03 Intel Corporation Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat
TW558743B (en) 2001-08-22 2003-10-21 Semiconductor Energy Lab Peeling method and method of manufacturing semiconductor device
FR2834380B1 (en) 2002-01-03 2005-02-18 Soitec Silicon On Insulator DEVICE FOR CUTTING LAYER OF SUBSTRATE, AND ASSOCIATED METHOD
FR2847714B1 (en) * 2002-11-27 2005-02-18 Soitec Silicon On Insulator SEMICONDUCTOR WAFER RECOVERY METHOD AND DEVICE
TWI233154B (en) 2002-12-06 2005-05-21 Soitec Silicon On Insulator Method for recycling a substrate
EP1427002B1 (en) * 2002-12-06 2017-04-12 Soitec A method for recycling a substrate using local cutting
JP4151421B2 (en) * 2003-01-23 2008-09-17 セイコーエプソン株式会社 Device manufacturing method
JP2005039114A (en) * 2003-07-17 2005-02-10 Disco Abrasive Syst Ltd Semiconductor wafer shifting device
JP4526561B2 (en) * 2004-03-22 2010-08-18 ジングルス・テヒノロギース・アクチェンゲゼルシャフト Method and apparatus for separating disk-type substrates
DE102004041378B4 (en) 2004-08-26 2010-07-08 Siltronic Ag Semiconductor wafer with a layered structure with low warp and bow and process for its production
DE102005000826A1 (en) 2005-01-05 2006-07-20 Siltronic Ag Semiconductor wafer with silicon-germanium layer and method for its production
EP1894234B1 (en) 2005-02-28 2021-11-03 Silicon Genesis Corporation Substrate stiffening method and system for a layer transfer.
JP5064692B2 (en) * 2006-02-09 2012-10-31 信越化学工業株式会社 Manufacturing method of SOI substrate
JP5064693B2 (en) * 2006-02-13 2012-10-31 信越化学工業株式会社 Manufacturing method of SOI substrate
US8293619B2 (en) * 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
JP2008112847A (en) 2006-10-30 2008-05-15 Shin Etsu Chem Co Ltd Process for manufacturing single crystal silicon solar cell and single crystal silicon solar cell
JP5284576B2 (en) * 2006-11-10 2013-09-11 信越化学工業株式会社 Manufacturing method of semiconductor substrate
JP5166745B2 (en) * 2007-03-07 2013-03-21 信越化学工業株式会社 Method for producing single crystal silicon solar cell
US20100193900A1 (en) * 2007-07-13 2010-08-05 National University Corporation Tohoku University Soi substrate and semiconductor device using an soi substrate
JP2010021398A (en) * 2008-07-11 2010-01-28 Disco Abrasive Syst Ltd Method of treating wafer
US7994064B2 (en) * 2009-06-15 2011-08-09 Twin Creeks Technologies, Inc. Selective etch for damage at exfoliated surface
WO2013058222A1 (en) * 2011-10-18 2013-04-25 富士電機株式会社 Solid-phase bonded wafer support substrate detachment method and semiconductor device fabrication method
FR2995447B1 (en) * 2012-09-07 2014-09-05 Soitec Silicon On Insulator METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ACCORDING TO A CHOSEN INTERFACE
JP2014138189A (en) * 2013-01-16 2014-07-28 Silicon Genesis Corp Controlled process and resulting device
CN103077885B (en) * 2013-01-31 2016-06-01 上海新傲科技股份有限公司 Controlled thining method and semiconducter substrate
JP6213046B2 (en) * 2013-08-21 2017-10-18 信越半導体株式会社 Manufacturing method of bonded wafer
FR3032555B1 (en) * 2015-02-10 2018-01-19 Soitec METHOD FOR DEFERRING A USEFUL LAYER
CN104979262B (en) * 2015-05-14 2020-09-22 浙江中纳晶微电子科技有限公司 Wafer separation method
CN106529159A (en) * 2016-10-28 2017-03-22 山东理工大学 Calculation method for natural angular frequency of transverse vibration of nanometer chord of piezoelectrically-controlled single atomic chain

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466852A (en) * 1983-10-27 1984-08-21 At&T Technologies, Inc. Method and apparatus for demounting wafers
EP0397237A1 (en) * 1989-05-08 1990-11-14 Koninklijke Philips Electronics N.V. Method of cleaving a plate of brittle material
US5213451A (en) * 1991-01-10 1993-05-25 Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh Apparatus and method of automatically separating stacked wafers
EP0703609A1 (en) * 1994-09-22 1996-03-27 Commissariat A L'energie Atomique Process of manufacturing a structure having a thin semiconductor layer on a substrate
EP0793263A2 (en) * 1996-02-28 1997-09-03 Canon Kabushiki Kaisha Fabrication process of a semiconductor substrate
EP0843344A1 (en) * 1996-11-15 1998-05-20 Canon Kabushiki Kaisha Process for transferring a semiconductor layer using silicon on insulator (SOI) technology
EP0867921A2 (en) * 1997-03-26 1998-09-30 Canon Kabushiki Kaisha Substrate and production method thereof

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JPH04359518A (en) * 1991-06-06 1992-12-11 Nec Corp Manufacture of semiconductor device
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JP3257580B2 (en) * 1994-03-10 2002-02-18 キヤノン株式会社 Manufacturing method of semiconductor substrate
JP3667079B2 (en) * 1997-03-26 2005-07-06 キヤノン株式会社 Thin film formation method
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Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466852A (en) * 1983-10-27 1984-08-21 At&T Technologies, Inc. Method and apparatus for demounting wafers
EP0397237A1 (en) * 1989-05-08 1990-11-14 Koninklijke Philips Electronics N.V. Method of cleaving a plate of brittle material
US5213451A (en) * 1991-01-10 1993-05-25 Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh Apparatus and method of automatically separating stacked wafers
EP0703609A1 (en) * 1994-09-22 1996-03-27 Commissariat A L'energie Atomique Process of manufacturing a structure having a thin semiconductor layer on a substrate
EP0793263A2 (en) * 1996-02-28 1997-09-03 Canon Kabushiki Kaisha Fabrication process of a semiconductor substrate
EP0843344A1 (en) * 1996-11-15 1998-05-20 Canon Kabushiki Kaisha Process for transferring a semiconductor layer using silicon on insulator (SOI) technology
EP0867921A2 (en) * 1997-03-26 1998-09-30 Canon Kabushiki Kaisha Substrate and production method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LU X ET AL: "SOI MATERIAL TECHNOLOGY USING PLASMA IMMERSION ION IMPLANTATION", PROCEEDINGS OF THE ANNUAL SOS/SOI TECHNOLOGY CONFERENCE. (FROM 1991 PROCEEDINGS OF THE INTERNATIONAL SOI CONFERENCE.) SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES,US,NEW YORK, NY: IEEE, 1996, pages 48 - 49, XP000736841, ISBN: 0-7803-3316-0 *
See also references of WO9852216A1 *

Also Published As

Publication number Publication date
AU7685198A (en) 1998-12-08
CN1146973C (en) 2004-04-21
CN1255237A (en) 2000-05-31
EP0995227A1 (en) 2000-04-26
WO1998052216A1 (en) 1998-11-19
CA2290104A1 (en) 1998-11-19
JP2001525991A (en) 2001-12-11

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