Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
  • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
  • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
  • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
  • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
  • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
  • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
  • H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage

Definitions

• This invention relates generally to devices which convert magnetic field energy to regulated electrical energy. Specifically, the present invention regulates direct current electrical energy which has been converted from magnetic field energy, measures the strength of the incoming magnetic field energy, adjusts the detection level of the incoming magnetic field and discharges excess energy from the magnetic field converter circuitry.
• the problem not previously addressed by prior art is the ability of an electronic circuit to determine the strength of an incoming magnetic field as measured by electrical power for the purpose of enhancing electro-magnetic communication between devices.
• the present invention has the ability to determine the strength of an incoming magnetic field as measured by electrical power, to adjust the detection level of the input converter circuitry and discharge excess energy based on the measured magnetic field strength and to interpret changes in the measured magnetic field strength as a method for communicating digital
• frequency voltage regulating circuit which comprises a magnetic field power sensor circuit, a programmable magnetic field detection circuit coupled to the magnetic field power sensor circuit, a discharge expediter circuit coupled to the programmable magnetic field detection circuit, a magnetic field converter circuit coupled to the discharge expediter circuit, a rectifier circuit coupled to the magnetic field converter circuit, a voltage clamping circuit coupled to the magnetic field power sensor circuit, and a charging circuit coupled to the voltage clamping circuit.
• a highly efficient multi-frequency voltage regulating circuit is disclosed where the programmable magnetic field detection circuit may be controlled by an analog reference current.
• a highly efficient multi-frequency voltage regulating circuit where the programmable magnetic field detection circuit may be controlled by selection of a discrete reference current.
• multi-frequency regulating circuit where the selection of a particular discharge path within the discharge expediter circuit is programmable.
• a highly efficient multi-frequency voltage regulating circuit which comprises a magnetic field power sensor circuit that measures incoming magnetic field energy variations for the purpose of communicating digital data over a magnetic field.
• Figure 1 is an electrical schematic of a magnetic field converter circuit, a discharge expediter circuit, a rectifier circuit, a magnetic field power sensor circuit, a programmable magnetic field detection circuit, a voltage clamping circuit, and charging circuit.
• Figure 2A is a waveform diagram of a typical sinusoidal waveform as seen by the LC magnetic field converter circuit.
• Figure 2B is a waveform diagram of the digital output of the magnetic field power sensor circuit for the sinusoidal waveform of figure 2A.
• Figure 2C is a waveform diagram of a pulse waveform of varying amplitudes as seen by
• Figure 2D is a waveform diagram of the digital output of the magnetic field power sensor circuit for the pulse waveform of figure 2C.
• Fig. 3 is a simplified electrical schematic of a prior art, idealized FWBR input structure
• FIG. 4 is a simplified electrical schematic of a prior art FWBR input structure having parasitic BJTs implemented in an integrated circuit.
• Fig. 5 is a simplified electrical schematic of a new FWBR input structure having parasitic BJTs of minimized gain in an integrated circuit.
• Fig. 6 is a simplified electrical schematic of another version of a new FWBR input structure having parasitic BJTs of minimized gain in an integrated circuit.
• Fig. 7 is a simplified drawing showing one possible manner of physically implementing
• Fig. 8 is a cross-sectional view of the physical implementation from Figure 7 taken along line 6-6.
• a highly efficient multi-frequency voltage regulating circuit 200 which comprises a magnetic field power sensor circuit 220, a programmable magnetic field detection circuit 250 coupled to the magnetic field power sensor circuit 220, a discharge
• expediter circuit 210 coupled to the programmable magnetic field detection circuit 250, a magnetic field converter circuit 280 coupled to the discharge expediter circuit 210, a rectifier circuit 290 coupled to the magnetic field converter circuit 280, a voltage clamping circuit 260 coupled to the magnetic field power sensor circuit 220, and a charging circuit 270 coupled to the voltage clamping circuit 260 for charging a battery and an energy storage device.
• the LC magnetic field converter circuit 280 and the rectifier circuit 290 are described in copending U.S. Patent Application entitled "A ROBUST LC FULL- WAVE BRIDGE RECTIFIER INPUT STRUCTURE," Serial No. 09/007,485 and a filing date of January 15, 1998, and is incorporated by reference as noted above under "Related Applications”.
• the clamping circuit 260 is a simple capacitor 262 coupled in parallel to a zener diode
• the charging circuit 270 is comprised of a biasing resistor 272 coupled to the gate connector of a NMOS FET switch 274, a diode 276 and resistor 275 in parallel coupled to a source connector of the NMOS FET transistor switch 274, a battery 278 coupled to the diode 276 and resistor 275, and a energy storage device 279 coupled to the diode 276 and resistor 275.
• the charging circuit 270 permits charging of the energy storage device 279 and recharging of the battery 278.
• the charging circuit 270 has also been disclosed by prior art.
• the magnetic field power sensor circuit 220 provides the capability of determining the strength of the incoming electro-magnetic field.
• the magnetic field power sensor circuit is comprised of an input current (Iz) 222, an input current divider circuit 230 coupled to Iz 222, an input current multiplier circuit 240 coupled to the input current divider circuit 230, a reference current (I REF ) 224 coupled to the input current multiplier circuit 240, and a comparator 248 coupled to the input current multiplier circuit 240.
• Iz 222 is the same as the output current of the clamping circuit 260.
• IREF 224 is generated external to the present invention.
• IREF 224 The purpose of IREF 224 is to establish an equilibrium point at the negative node of the comparator 248.
• the positive node of the comparator is coupled to a bias voltage. Disregarding the input current divider circuit 230 and the input current multiplier circuit 240 for a moment, if Iz 222 is less than IREF 224, the output of the comparator will be 0. However, if Iz 222 is larger than I REF 224, the comparator 248 will give a positive output which yields two results. First, a positive output of the comparator 248 indicates that the rectified voltage is above the breakdown voltage of the zener diode 264. Second, the incoming magnetic signal has enough power to subsequently maintain an input current through the zener diode 264. Thus, the positive output
• the comparator 248 which is reached only when Iz becomes greater than IREF, enables the determination of whether a certain induced voltage level has been exceeded and what nominal power level is present in the electromagnetic field received by the voltage regulating circuit 200.
• the operation of the input current divider circuit 230 and the input current multiplier circuit 240 is described.
• the purpose of the current divider and multiplier circuits (230 & 240) is to have Iz mirror IREF by a combination of the divider circuit 230, which effectively reduces Iz, and the multiplier circuit 240, which effectively increases Iz.
• the equilibrium point at the negative node of the comparator 248 is evaluated with respect to variations in Iz and thus to incoming magnetic field
• the input current divider circuit 230 is comprised of at least one NMOS transistor 232.
• the at least one NMOS transistor 232 is configured such that the gate and drain connectors of each of the at least one NMOS transistors 232 is coupled to the input current 222.
• the source connectors of each of the at least one NMOS transistors 232 are coupled to a ground reference.
• the effect of this input current divider circuit 230 is to mirror an Iz that is divided by the number of NMOS transistors 232 in the circuit.
• the zener diode breakdown voltage is 5 volts
• the threshold voltage of the input current divider circuit 230 is 0.7 volts
• the magnetic field power is increased until the output of the comparator 248 becomes positive.
• the input current multiplier circuit 240 is comprised of a second at least one NMOS transistor 242.
• the second at least one NMOS transistor 242 is configured such that the gate connectors of each of the second at least one NMOS transistors 242 are coupled to Iz 222 and the input current divider circuit 230.
• the second at least one NMOS transistor 242 is further configured such that the drain connectors of each of the second at least one NMOS transistors 242 are coupled to the reference current 224 and also to the negative node of the comparator 248.
• the second at least one NMOS transistor 242 is configured such that the source connectors of each of the second at least one NMOS transistors 242 are coupled to a ground reference.
• the effect of this input current multiplier circuit 240 is to multiply Iz by the number of NMOS transistors 242 in the circuit. For example, suppose there were three transistor as part of the input current multiplier circuit 240, I RE F 224 was set at 10 uA, the zener diode breakdown voltage is 5 volts, the threshold voltage of the input current multiplier circuit 240 is 0.7 volts and the magnetic field power is increased until the output of the comparator 248 becomes positive.
• the input current 222 is mirrored by a factor of 1/m for the input current divider circuit 230 and by a factor of n for the input current multiplier circuit 240.
• m equals the number of NMOS transistors in the input current divider circuit 230
• n equals the number of NMOS transistors in the input current multiplier circuit 240.
• the ratio of m:n is defined as the current mirror ratio.
• CMOS FETs may be implemented with minor modification to the circuit to acheive substantially, if not identical, results.
• the programmable magnetic field detection circuit 250 permits the screening of incoming magnetic field energy by the adjustment of comparator bias voltage. Thus, only magnetic field induced voltage signals that meet or exceed bias voltages will be processed.
• the programmable magnetic field detection circuit 250 is comprised of at least two comparators 252 & 254 and a multiplexer 256.
• the output of the LC magnetic field converter circuit 280 is connected to each of the positive nodes of the 5 comparators 252 & 254.
• the negative node of one comparator 252 is connected to a bias voltage.
• the negative node of the second comparator 254 is connected to the voltage induced by I REF 224.
• the outputs of the comparators 252 & 254 are connected to the inputs of the multiplexer 256.
• the output of the comparator 248 of the magnetic field sensor circuit 220 is connected to the input select for the multiplexer 256.
• the output of the multiplexer 256 is l o connected to logic beyond the scope of the present invention such as signal processing.
• the programmable magnetic field detection circuit 250 operates as follows.
• the biasing voltage for the first comparator 252 is typically set at a threshold level to allow the output of the LC magnetic field converter circuit 280 to pass through the first comparator 252 to an input of the multiplexer 256.
• the biasing voltage for the second comparator 254 is set to the
• the output of the comparator 248 of the magnetic field sensor circuit 220 is connected to the input select of the multiplexer 256.
• the sensitivity of the circuit 250 is adjustable by varying the amplitude of the reference current 224 and the selection of the second comparator 254 by the output of the magnetic field sensor circuit 220.
• a programmable magnetic field detection circuit 250 which is comprised of two comparators 252 & 254. Those skilled in the art will recognize that the present invention is not limited to two comparators. Additional comparators can be incorporated into the programmable magnetic field detection circuit 250 to allow for greater flexibility. Similarly, the multiplexer 256 which is disclosed as having two inputs may also be expanded to include additional inputs.
• the amplitude of the reference current may be varied by analog means such as a sinusoidal, triangle, sawtooth or other known wave generators. Furthermore, the amplitude of the reference current may be varied by discrete means well known to those skilled in the art. For example, selection logic can be incorporated into the present invention to select as between a plurality of available discrete reference currents. This selection may be accomplished either dynamically or may be preset.
• the discharge expediter circuit 210 provides a programmable discharge path for excess energy stored by the magnetic field converter circuit 280.
• the discharge expediter circuit 210 is comprised of a decoder 219 and four discharge paths, i.e. two discharge paths for each node of the magnetic field converter circuit 280.
• the present invention is not limited to four discharge paths.
• the first pair of discharge paths are connected to a first common node of the magnetic
• the first discharge path is formed by the combination of resistor 211 and transistor 215.
• the second discharge path is formed by the combination of resistor 212 and transistor 216.
• the impedance value of resistor 211 is distinct from the impedance value of resistor 212.
• resistors by having resistors with unique impedance values to control the rate of discharge.
• the second pair of discharge paths are connected to a second common node of the
• the third discharge path is formed by the combination of
• the fourth discharge path is formed by the combination of
• resistor 214 resistor 214 and transistor 218.
• impedance value of resistor 214 resistor 214 and transistor 218.
• resistor 213 approximates that of resistor 211 and the impedance value of resistor 214 approximates that
• the decoder 219 activates the selected discharge path(s).
• decoder 219 is coupled to a programming source that is beyond the scope of the present
• the D (decode) input to the decoder 219 is coupled to the data source to be decoded.
• the D input is coupled to the output of the comparator 248.
• Oi output of the decoder 219 is coupled to the control electrodes of the transistors 215 & 217.
• the O 2 output of the decoder 219 is coupled to the control electrodes of the transistors 216 &
• the resistors 211, 212, 213 «& 214 will optimize the efficiency of the discharge paths for specific magnetic field strengths.
• FIGS. 2A-2D waveform diagrams of the conversion of the incoming magnetic field to digital data are disclosed for the purpose of illustrating digital communication over a magnetic field.
• the abscissa is time and the ordinate is power.
• Two variations of an incoming magnetic field waveforms are shown.
• Figure 2A reflects a typical sinusoidal waveform as seen by the LC magnetic field converter circuit 280 (figure 1).
• Figure 2B reflects the digital output of the comparator 248 (figure 1) for the sinusoidal waveform of Figure 2A.
• Figure 2C reflects a pulse waveform with varying amplitudes at the LC magnetic field converter circuit 280 (figure 1).
• Figure 2D reflects the digital output of the comparator 248 (Figure 1) for the pulse waveform of Figure 2C.
• the trigger point for the digital output of the comparator 248 is determined by the power of the incoming magnetic signal and the parameters described for the voltage regulating circuit 200 ( Figure 1).
• the digital output of the comparator 248 can be used to receive digital communication from a magnetic transmitter. Referring to Figure 3, simplified electrical schematic is shown of a prior art, idealized
• the FWBR input structure implemented in an integrated circuit.
• the FWBR input structure is generally designated by reference number 10. It includes an inductor 12 coupled in parallel to a capacitor 14 about input nodes 16 and 18. From input nodes 16 and 18, there are resistors 20 and 22, respectively, before reaching the cathode junction of a pair of diodes 24 and 26, respectively.
• the anode junctions of diodes 24 and 26 are tied to ground.
• the node at the cathode junction of diode 24 is connected to the source of a PMOS transistor 28, and to the gate of PMOS transistor 30.
• the node at the cathode junction of diode 26 is connected to the source of a PMOS transistor 30, and to the gate of PMOS transistor 28.
• the drain of PMOS transistor 28 is tied to the drain of PMOS transistor 30 at the output node 32 for the FWBR input structure 10.
• FIG 4 a simplified electrical schematic is shown of a prior art FWBR input structure having parasitic BJTs implemented in an integrated circuit.
• implementation of the ideal, prior art FWBR input structure 10 of Figure 3 into an integrated circuit effectively results in the creation of parasitic BJTs 48 and 50, rather than the ideal diodes 24 and 26 (see Figure 3) by themselves. Otherwise, Figures 3 and 4 are the same.
• the FWBR input structure of Figure 4 is generally designated by reference number 34.
• inductor 36 coupled in parallel to a capacitor 38 about input nodes 40 and 42. From input nodes 40 and 42, there are resistors 44 and 46, respectively, before reaching the emitter junctions of a pair of parasitic BJTs 48 and 50, respectively.
• the base junctions of parasitic BJTs 48 and 50 are tied to ground, and their collector junctions are tied to a supply voltage VDD through a resistor 52.
• the node at the emitter junction of parasitic BJT 48 is connected to the source of a PMOS transistor 54, and to the gate of a PMOS transistor 56.
• the node at the emitter junction of parasitic BJT 50 is connected to the source of PMOS transistor 56, and to the gate of PMOS transistor 54.
• the drain of PMOS transistor 54 is tied to the drain of PMOS transistor 56 at the output node 58 for the FWBR
• the flow path for the FWBR input structure 34 which is analogous to that for the FWBR input structure 10 of Figure 3, is as follows: 1) an electromagnetic field is applied across the tuned LC input (i.e.
• inductor 36 and capacitor 38 to create alternating complementary current at input nodes 40 and 42; 2) assuming a positive potential at node 40, current flows through resistor 44; 3) since a negative potential is applied to the gate of PMOS transistor 54, it will be on to conduct current to the output load via node 58; and 4) the return path encompasses current flow via ground, through the base-to-emitter junction of parasitic BJT 50, and through the resistor 46.
• FWBR input structure 60 a new FWBR input structure, generally designated by reference number 60, and having parasitic BJTs of minimized gain in an integrated circuit.
• FWBR input structure generally refers to all that is shown in Figure 5; however, it will become apparent that the portion of primary concern is shown in the dashed-line box labelled by reference number 62. Nonetheless, the FWBR input structure 60 comprises, in combination, a pair of input nodes 68 and 70, and a pair of parasitic BJTs 76 and 88 coupled in parallel with the pair of input nodes 68 and 70 wherein each parasitic BJT 76 and 88 has more than one collector. Note
• the FWBR input structure 60 includes an inductor 64 and a capacitor 66 connected in parallel across the pair of input nodes 68 and 70.
• the inductor 64 and capacitor 66 are tuned to a resonant frequency of an electromagnetic transmission, which provides power and/or data to circuitry downstream of the LC pair (i.e., 64 and 66).
• the LC pair therefore acts, in essence, as an "antenna" for the FWBR input structure 60, and circuitry located downstream of output node 116.
• the LC pair 64 and 66 is shown comprising single components; however, those skilled in the art recognize that other tuned frequency "antennas" well known to those skilled in the art could be implemented, if desired.
• each parasitic BJT 76 and 88 comprises an NPN-type parasitic BJT; however, those skilled in the art realize that other BJTs such as PNP-type parasitic BJTs could, in a slightly different situation, be implemented, if desired.
• a first parasitic BJT 76 has a first collector 80 connected to ground and a second collector 82 coupled to VDD through resistor 84.
• a second parasitic BJT 88 has a first collector 92 connected to ground and a second collector 94 coupled to VDD through resistor 96.
• the first parasitic BJT 76 has an emitter 78 connected to a first node 68 of the pair of input nodes 68 and 70.
• the second parasitic BJT 88 has an emitter 90 connected to a second node 70 of the pair of input nodes 68 and 70.
• Each emitter 78 and 90 has an area smaller than its corresponding collector 82 and 94, respectively, coupled to VDD.
• the first parasitic BJT 76 has a base 85 coupled to ground through a resistor 86
• the second parasitic BJT 88 has a base 97 coupled to ground through a resistor 98.
• the FWBR input structure 60 further includes a first plurality of zener diodes 100- 104
• first 112 and second 114 MOS transistors wherein the second end of the first plurality of zener diodes 100-104 is connected to a source of the first MOS transistor 112 and to a gate of the second MOS transistor 114.
• the other end of the second plurality of zener diodes 106-110 is connected to a source of the second MOS transistor 114 and to a gate of the first MOS transistor 112.
• the drain of the first MOS transistor 112 is connected to a drain of the second MOS transistor 114 to form an output node 116.
• the first 112 and second 114 MOS transistors are preferably PMOS-type transistors; however, in situations well known to those skilled in the art, NMOS-type transistors could be implemented.
• the second NMOS transistor would have its gate and drain tied to the other output node of 62 (or 120 in Figure 6).
• MOS transistors 112 and 114 in Figures 5 and 6 is shown only as one possible way of completing the FWBR input structures 60 and 118.
• Those skilled in the art will fully realize that there are numerous ways of taking the signals at the output nodes from the dashed-line box 62 (or 120 in Figure 6) and processing them to complete the full-wave rectification. It is considered within the scope of the invention here to take any one of the many different combinations of elements, well known to those skilled in the art, and incorporate them in place of transistors 112 and 114.
• FIG. 6 shows a simplified electrical schematic of another version of the new FWBR input structure, generally designated by reference number 118, and having parasitic BJTs of minimized gain in an integrated circuit.
• the FWBR input structure 118 of Figure 6 is identical to that shown in Figure 5, with one modification, and therefore the FWBR input structure 118 will not be discussed in detail.
• each of the parasitic BJTs 76 and 88 have an MOS device coupled to them — this is the modification.
• the FWBR input structure 118 includes a first MOS transistor 122 having its source 128 connected to the first collector 80 of the first parasitic BJT 76, and having its drain
• a second MOS transistor 130 is also included having its source 136 connected to the first collector 92 of the second parasitic BJT 88, and having its drain 134 and gate 132 connected to the emitter 90 of the second parasitic BJT 88.
• the first 122 and second 130 MOS transistors are NMOS-type transistors; however, those skilled in the art realize that under different circumstances, PMOS-type transistors could be implemented.
• Figures 7 and 8 one possible manner of physically implementing the instant invention into silicon is shown; however, note that only a portion of the instant invention is shown in Figures 7 and 8 (i.e., that portion corresponding to like numbers in Figures 5 and 6). Nonetheless, those skilled in the art of implementing electrical devices, systems, and the like into silicon understand what the remainder of the instant invention would look like in Figures 7 and 8. Moreover, those skilled in the relevant art also understand that the manner shown in Figures 7 and 8 for physically implementing the instant invention into silicon comprises but one of the many possible manners of implementation. More specifically, the NFET device 122 and the parasitic npn BJT 76 of Figure 6 are
• Figures 7 and 8 on a p-type silicon substrate.
• Figure 7 shows a top view, without metallization, while Figure 8 shows a side cross-sectional view taken along line 6-6 of Figure 7.
• the NFET device 122 is located between nodes 128, 126, and 124, where node 126 forms the drain and node 128 the source for device 122.
• the parasitic npn BJT 76 is located
• the emitter of parasitic npn BJT 76 is formed by node 78, its base comprises node 85, and the grounded base contact is formed by node GB.
• GB stands for grounded base, which is situated (as viewed in Figure 6) between resistors 86 and 98.
• the base resistance 86 is associated with the distance from the actual base (85 in Figure 6) of the parasitic npn BJT 76 to the GB node. Note that the base contact GB, and therefore the base resistance 86, may be distributed depending on the layout of the surrounding circuitry.
• the grounded collector 80 of the parasitic npn BJT 76 completely surrounds emitter 78 in this implementation.
• the high voltage collector 82 is situated some distance away from the base 85 of the parasitic npn BJT 76 and has an implied resistance 84.
• the high voltage collector 82, and therefore the resistance 84 may also be distributed as the layout of the surrounding circuitry dictates. Note that where an area of the Figures is labelled with more than one reference number, this is meant to indicate that the area is shared. For example, the area labelled 124 and 85 is shared between the corresponding components labelled in Figure 6, and the area labelled 128 and 80 is shared between its corresponding components from Figure 6. Additionally, note that the base 86 and collector 84 resistances are the sum of more than one leg in Figure 7. Lastly, note that an even more detailed description of Figures 7 and 8 is not required here, as those skilled in the art, after a comparison of the full patent disclosure including all of the Figures, understand the
• the "antenna” can be implemented using the LC pair, one or more inductors, one or more capacitors, a transformer, or the like.
• the LC pair i.e., 64 and 66
• the FWBR input structure 60 (or 118 of Figure 6) simply provides a rectified signal for use by downstream loads (not shown).
• the electromagnetic signal input to the LC pair i.e., 64 and 66) causes alternating complementary current at input nodes 68 and 70. In other words, when the potential at node 68 is positive, it is negative at node 70, and vice versa.
• the gate of transistor 114 is low, so it conducts current from node 70, through resistor 74, through transistor 114, through the output node 116, and to the downstream load.
• current flows from ground, through resistor 86, through the base-to-emitter junction of parasitic BJT 76, and to node 68.
• the return flow path here also includes current flow from the grounded collector 80 to the emitter 78, and to the node 68.
• parasitic BJTs e.g., 48 and 50 in Figure 4
• the parasitic BJTs here 76 and 88 have been modified to minimize their gain, and thereby minimize the amount of current drawn from the downstream power supply whether it be a battery, a capacitor, or some other power storage device.
• a number of features have been built into parasitic BJTs 76 and 88 to minimize their gain. By way of example, these features will be discussed for parasitic BJT 76; however, note that similar changes are also included for parasitic BJT 88.
• the area of emitter 78 is purposefully made smaller than the area for collector 82. There is no magic number for how small the emitter 78 should be or how small it should be relative to the collector 82 other than to say that the emitter's area should be smaller than the area for collector 82. Ideally, the area for emitter 78 should be no larger than the area required to support the anticipated current that will be drawn through the emitter's return flow path. In the preferred embodiment, that return flow path current typically falls in the range of 10-50 ma; however, this range is not considered limiting. Rather, in general, the emitter's area should be no larger than that required to support the anticipated return flow path current, and in any case, not larger than the area of collector 82.
• a second feature is the addition of a second large area collector 80 connected to ground.
• the area of collector 80 is certainly larger than the area of the emitter 78, and for optimum operation, the larger the area for collector 80, the better; however, design space constraints may limit the area for collector 80 to a reasonably large size.
• a third feature implemented in the parasitic BJT 76 comprises adding a resistor 86 between its base 85 and ground.
• a fourth feature added to parasitic BJT 76 was increasing the resistance 84 between VDD and the collector 82. Note that the fourth feature is represented by including a separate resistor 84 and 96 for each BJT's second collector 82 and 94 (instead of a single, shared resistor like 52 in Figure 4).
• the parasitic BJTs 76 and 88 are also put to constructive use by having them act as "fold-back devices" (a term well known to those skilled in the art) during Electro-Static Discharge (hereafter "ESD”) conditions.
• ESD Electro-Static Discharge
• the emitter 78 or 90 of one of the parasitic BJTs 76 or 88 will act as a collector, while the grounded collector 80 or 92 acts as an emitter.
• the base 85 or 97 of the affected parasitic BJT 76 or 88 floats, and as soon as the voltage difference between the acting collector and the acting emitter is high enough, the parasitic BJT 76 or 88 will fold back into a low resistance mode, absorbing all of the unwanted energy from the ESD pulse.
• either parasitic BJT 76 or 88 can operate in the fold-back mode per standard BJT operation.
• the zener diode groups 100-104 and 106-110 ensure that the voltage down stream of
• the zener diode groups 100-104 and 106-110 limit the downstream voltage to approximately 15 volts; however, those skilled in the art realize that more or less than groups of three zener diodes, or zener diodes with a different rating (i.e., other than approximately 5 volts each), could be used to achieve different downstream voltage limitations.
• the addition of the two groups of zener diodes 100-104 and 106-110 further enhanced the robustness of the FWBR input structure 60.
• FIG. 6 a simplified electrical schematic is shown of another embodiment of the new FWBR input structure, generally designated by reference number 118. It is essentially identical to the FWBR input structure 60 from Figure 5, with the exception that the dashed-line box labelled 120 includes some supplemental circuitry.
• MOS transistors 122 and 130 have been added. These thick oxide field NMOS transistors 122 and 130 are connected between the grounded collector and the emitter or their respective parasitic BJTs 76 and 88. This addition implies that an additional conductive path may be formed during high voltage conditions (e.g., ESD conditions) when the threshold voltage of the thick oxide over the base of the respective parasitic BJT 76 or 88 is exceeded.
• high voltage conditions e.g., ESD conditions
• the respective thick oxide field NMOS transistor 122 or 130 creates a short circuit to assist during the ESD condition. For example, if a positive potential is applied at
• the gate 124 of transistor 122 will be forward biased, causing the drain 126 and the source 128 to be tied together. This puts the collector 80 and the emitter 78 of the parasitic BJT 76 at the same potential, which form a low resistance path, and the ESD pulse will be further assisted in its dissipation to ground. Note that the other thick oxide field NMOS transistor 130 operates identically.

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• 1999
  • 1999-01-15 EP EP99902303A patent/EP0985278A2/en not_active Withdrawn
  • 1999-01-15 KR KR1019997008400A patent/KR20000076299A/ko not_active Application Discontinuation
  • 1999-01-15 JP JP53751999A patent/JP2001516460A/ja active Pending
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