Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
  • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • H03M7/3002—Conversion to or from differential modulation
  • H03M7/3004—Digital delta-sigma modulation
  • H03M7/3015—Structural details of digital delta-sigma modulators
  • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
  • H03M7/3042—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H17/00—Networks using digital techniques
  • H03H17/02—Frequency selective networks
  • H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
  • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • H03M7/3002—Conversion to or from differential modulation
  • H03M7/3004—Digital delta-sigma modulation
  • H03M7/3015—Structural details of digital delta-sigma modulators
  • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
  • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
  • H03M7/3026—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one

Definitions

• the invention relates to a device for processing a digital signal, comprising an input for receiving the digital signal and an output for supplying an output signal, filter means for deriving an error signal, and adding means coupled to the input for supplying to the output a sum of the digital signal and the error signal, whereby the error signal is indicative of the difference between the sum signal and a word-length-limited version thereof.
• Such a device is known from the English-language abstract JP-A 08 293 761.
• a digital signal processor is described, in which such a device is used to reduce the effect of quantization errors originating from the limitation of the word length of data being processed.
• the word length of data increases with every addition and multiplication. In general it is desired to limit this increasing word length to a desired word length.
• This limitation causes quantization errors.
• a quantization error is meant to be the difference between a data word before word-length- limitation has been applied and the same data word after its word length has been limited. When these quantization errors are uncorrelated and uniformly distributed over the frequency spectrum they are often referred to as quantization noise.
• the word-length-limitation is performed by means of a shift register.
• the resulting quantization noise is noise shaped, so that the amount of quantization noise in the frequency band of interest (e.g. the audio band) is decreased. In this way, the signal to noise ratio and the dynamic range in the frequency band of interest can be increased.
• the device according to the invention is characterized in that the adding means are embodied so as to supply the most significant symbols of the sum signal to the output and to supply the least significant symbols of the sum signal to the filter means.
• the adding means are embodied so as to supply the most significant symbols of the sum signal to the output and to supply the least significant symbols of the sum signal to the filter means.
• a shift register is not needed here because the word-length-limitation is performed by simply leaving out the least significant symbols of the sum signal. Only the most significant symbols of the sum signal are supplied to the output. It will be clear that the least significant symbols represent the quantization error resulting from the word-length-limitation.
• This quantization error is supplied to a filter means in order to derive an error signal. This error signal is fed back to the adding means, in order to reduce the effect of the quantization error in the output signal.
• the word length can be even further reduced, while still maintaining a desired signal to noise ratio or dynamic range, because a smaller amount of the quantization noise is included in the frequency band of interest.
• An embodiment of the device according to the invention is characterized in that the filter means comprise a delay unit. By this measure, a simple noise shaper is formed which shifts the quantization noise out of the frequency band of interest.
• a further embodiment of the device according to the invention is characterized in that the device comprises further filter means, via which the adding means are coupled to the output. By virtue thereof, the quantization noise, which is present outside the frequency band of interest, can be filtered out of the output signal. For example, if the quantization noise is shifted towards a higher part of the frequency spectrum, a low-pass filter could be used here.
• the Figure shows a block diagram of an example of a device for processing a digital signal according to the invention.
• the Figure shows a block diagram of an example of a device for processing a digital signal according to the invention.
• the device comprises an input 10 for receiving a digital input signal and an output 18 for supplying an output signal.
• the circuit further comprises filter means 14 coupled to the output 18 for deriving an error signal.
• Adding means 12 are coupled to the input 10 and the filter means 14 for supplying to the output 18 the sum of the input signal and the derived error signal.
• the device limits the word length of the input signal.
• the adding means 12 are embodied so as to supply the n most significant bits of the sum signal to the output 18, and to supply the m-n least significant bits of the sum signal to the filter means 14, the word length of the input signal (m bits) is effectively limited to n bits, which is the word length of the output signal.
• the resulting quantization noise is fed back via the filter means 14, which preferably comprise a delay unit, to the adding means 12 in order to shift the quantization noise out of the frequency band of interest, e.g. the audio band. Consequently, the signal to noise ratio and the dynamic range of the output signal are improved.
• the device according to the invention can also be used when the signals involved are oversampled.
• the negative effect of the quantization noise is already limited by this oversampling, because only a part of the quantization noise is included in the frequency band of interest.
• filter means 16 may be inserted between the adding means 12 and the output 18 in order to filter out of the output signal the quantization noise, which is present outside the frequency band of interest. For example, if the quantization noise is shifted towards a higher part of the frequency spectrum, it is advantageous to use a low-pass filter here.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Mathematical Physics (AREA)
• Theoretical Computer Science (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)
• Analogue/Digital Conversion (AREA)
• Signal Processing For Digital Recording And Reproducing (AREA)

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• 1999
  • 1999-01-21 EP EP99900237A patent/EP0970565A2/de not_active Withdrawn
  • 1999-01-21 JP JP53909599A patent/JP2001522571A/ja active Pending
  • 1999-01-21 WO PCT/IB1999/000092 patent/WO1999039440A2/en not_active Ceased

Non-Patent Citations (1)

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