EP0952508A1 - Generating circuit for reference voltage - Google Patents

Abstract

The circuit has a first stage (T1,T3) providing a first voltage with a negative temperature coefficient and a second stage (T1-T4,R1-R4) providing a difference voltage with a positive temperature coefficient via 2 further voltages. The reference voltage is obtained by combining the first voltage and the difference voltage. The first voltage and each of the further voltages is obtained as a sum voltage of a pair of pn junction voltages.

Description

The present invention relates to a reference voltage generating circuit or reference voltage source according to the preamble of claim 1.

Most integrated circuits that operate from an unstabilized supply voltage, i. H. Almost all smart power ICs require an internal reference voltage source. This applies in particular to voltage regulators whose output voltage serves as a reference voltage for other integrated circuits or circuit blocks.

Known reference voltage sources use, for example, Zener diodes, to which an unstabilized input voltage is supplied via a series resistor, the voltage tapped at the Zener diode being used as the voltage-stabilized reference voltage. In addition, the forward or forward voltage of a diode or the base-emitter voltage of a bipolar transistor can in principle be used as a reference voltage. However, the forward voltage of a pn junction has a negative temperature coefficient and thus a temperature dependency that is negative for many applications. If, for example, sensors, A / D converters or similar components are to be supplied with the aid of a voltage regulator, the output voltage of which serves as a reference voltage, the output voltage of the voltage regulator must be highly precise and, in particular, extremely temperature-stable. Nowadays, tolerance limits of up to 1% are normal requirements.

For this reason, the reference voltage sources described above have been replaced by bandgap or Bandgap reference voltage sources replaced, which provide a temperature-stabilized reference voltage. These known bandgap reference voltage sources are based on an addition of a forward voltage of a current-carrying pn junction and a differential voltage multiplied by a corresponding factor, which is formed from two forward voltages of two pn junctions through which different current densities flow. In general, the forward voltage of a current-carrying pn junction - as has already been explained above - has a negative temperature coefficient. In contrast, the difference between two forward voltages increases proportionally to the absolute temperature and is therefore subject to a positive temperature coefficient. If the factor by which the differential voltage explained above is multiplied is set such that the negative temperature coefficient of the forward voltage of the pn junction cancels the positive temperature coefficient of the differential voltage, a temperature-stabilized output or reference voltage can be obtained which only has a parabolic or exhibits quadratic temperature dependence. In particular, the output voltage of the bandgap reference voltage source, which is obtained by adding the previously explained forward voltage of a current-carrying pn junction with the difference voltage multiplied by the corresponding factor of two further forward voltages, is approximately 1.25 V, which is approximately the band gap (band gap ) of silicon. The magnitude of the output voltage of this reference voltage source has therefore given the bandgap reference voltage source its name.

2 shows a generalized circuit diagram of a known bandgap reference voltage source. A current mirror circuit S ₁ , which connects the collector currents I ₁ and I ₂ from two npn bipolar transistors T ₁ and T ₂ connected according to FIG. 2, is connected to a positive supply voltage connection V _cc compares. The currents of these currents I ₁ and I ₂ are predetermined by the transistors T ₁ and T ₂ . The base terminals of these transistors T ₁ and T ₂ are connected to each other, wherein the base voltage of the transistor T is multiplied up ₁ via a voltage divider consisting of two resistors R ₅ and R _6, so that the resistor R _{6 ref} a desired initial or reference voltage V can be tapped. 1, the current mirror S _{1 has} an output which reproduces the result of the comparison of the currents I ₁ and I ₂ and is coupled to an actuator ST, for example an operational amplifier or an amplifying transistor.

With the aid of the control circuit shown in Fig. 2 with the current mirror S ₁ and the actuator ST, the ratio of through the transistors T ₁ and T ₂ flowing currents I ₁ and I ₂ is adjusted, the currents I ₁ and I ₂ usually are the same size. In BICMOS circuits, however, the current I _{1 is} often also set to a multiple value of the current I ₂ , so that the following generally applies: $${\text{I.}}_{\text{1}}{\text{= m · I}}_{\text{2nd}}\text{.}$$

The transistors T ₁ and T ₂ have different emitter areas, the emitter area of the transistor T ₂ corresponding to a multiple of the emitter area of the transistor T ₁ , so that the relationship between the emitter areas A _E1 and A _{E2 of} the transistors T ₁ and T ₂ is shown as follows can be: $${\text{A}}_{\text{E2}}{\text{= n · A}}_{\text{E1}}\text{.}$$

Because of the relationships given above, the emitter current densities of transistors T ₁ and T ₂ differ by the factor n · m, ie the emitter current density of transistor T ₁ is (n · m) times as large as the emitter current density of the transistor T ₂ .

At the common base connection of the transistors T ₁ and T ₂ , the total voltage is tapped from the base-emitter voltage of the transistor T ₁ and the voltage present at the node between the resistors R ₁ and R ₂ . The first-mentioned base-emitter voltage of the transistor T ₁ corresponds to the forward voltage of a current-carrying pn junction and therefore, as has been explained above, has a negative temperature coefficient. The voltage drop across the resistor R ₁ is dependent on the difference between the base-emitter voltage of the transistor T ₁ and the base-emitter voltage of the transistor T ₂ and, as has also been explained above, has a positive temperature coefficient. The emitter-base voltage of the bipolar transistor T ₁ decreases by 2mV / K depending on the temperature. The bandgap reference voltage source shown in FIG. 2 can be dimensioned in such a way that the differential voltage across the resistor R ₁ from the forward voltages of the two transistors T ₁ and T _{2 is} one by appropriate selection of the resistors R ₁ and R ₂ and the previously specified factor n the negative temperature coefficient compensating positive temperature coefficient of + 2mV / K is subject. The voltage 2mV / K x 300K = 600mV drops across the resistor R ₁ at room temperature, so that the desired temperature-stabilized bandgap reference voltage is obtained at the common base connection of the transistors T ₁ and T ₂ due to the typical emitter-base voltage of approx. 650mV of approximately 1.25V (= 650mV + 600mV), which is then multiplied by the divider with the resistors R ₅ and R ₆ .

The resistance ratios R ₅ : R ₆ , R ₁ : R ₂ , the current mirror transmission ratio I ₁ : I ₂ (m: 1) and the ratio are in particular for a narrow tolerance of the output voltage V _ref the emitter areas of the transistors T ₁ and T ₂ (1: n) critical. Furthermore, the circuit shown in FIG. 2 reacts very sensitively to the temperature gradients which are ubiquitous in integrated power circuits. With usual emitter area ratios (e.g. n = 8) and room temperatures, the difference between the emitter-base voltages of the two transistors T ₁ and T _{2 is} approximately 50 mV. If the temperatures of the transistors T ₁ and T ₂ differ by 1K, the difference in the emitter-base voltages changes by approximately 2 mV, ie by approximately 4%. It is therefore necessary to arrange the transistors T ₁ and T ₂ exactly on isotherms of the largest heat source of the corresponding circuit in an implemented circuit layout. However, modern layout with reusable circuit and layout blocks prohibits the circuit from being adapted to the respective location of the existing heat sources. In addition, the number of heat sources in smart power ICs is increasing steadily, so that the course of the corresponding isotherms of these heat sources cannot be clearly determined. Furthermore, due to the large number of components of the bandgap reference voltage source that are critical with regard to the mating properties, an individual adjustment of the circuit is generally required, which can be done, for example, with the aid of so-called "zapping" zener diodes, which break through in the reverse direction when a high external voltage is applied and a generate low-resistance connection. However, this increases the complexity of the circuitry.

The invention is therefore based on the object of specifying a reference voltage generating circuit of the type described at the outset, which is less sensitive to temperature fluctuations and component tolerances.

This object is achieved according to the present invention by a reference voltage generation circuit with the features of claim 1 solved. The subclaims each describe advantageous and preferred embodiments of the present invention, which in turn contribute to a circuit that is as simple to implement as possible or to the greatest possible temperature stability.

According to the present invention, the reference voltage is further generated by adding a voltage component with a negative temperature coefficient to a voltage component with a positive temperature coefficient. According to the invention, however, the portion subject to the negative temperature coefficient comprises a plurality of forward voltages of corresponding pn junctions, and the portion with the positive temperature coefficient in turn comprises a differential voltage, each voltage contributing to the differential voltage corresponding to a sum voltage from a plurality of forward voltages of corresponding pn junctions. In particular, the difference voltage, which represents the proportion of the desired reference voltage with a positive temperature coefficient, is the difference between two sums of several forward voltages with different current densities through pn junctions. In this case, the reference voltage source provides an output voltage that is a multiple of the usual bandgap reference voltage. This voltage is sufficiently high for most applications, so that, for example, a voltage divider for high multiplication of the reference voltage can be omitted.

By appropriate dimensioning of the reference voltage source according to the invention it can be achieved that a deviation of 1K in the temperature of one of the transistors used is only 1.3% of the difference in the total voltages. Furthermore, it is possible to arrange the transistors in the layout of the reference voltage source according to the invention in such a way that linear temperature gradients cannot falsify the output voltage of the reference voltage source from any direction.

According to a preferred embodiment, circuit means are used which compensate for the remaining parabolic temperature dependency of the generated reference voltage, so that the output reference voltage can ideally be generated in a temperature-stable manner within a 0.03% window.

• Fig. 1 zeigt ein vereinfachtes Schaltbild eines bevorzugten Ausführungsbeispiels der erfindungsgemäßen Referenzspannungsquelle,
• Fig. 2 zeigt ein vereinfachtes Schaltbild einer bekannten Referenzspannungsquelle,
• Fig. 3 zeigt ein verfeinertes Ausführungsbeispiel der erfindungsgemäßen Referenzspannungsquelle, und
• Fig. 4 zeigt eine weiter verfeinerte und tatsächlich realisierte Ausgestaltung der in Fig. 3 dargestellten Referenzspannungsquelle der vorliegenden Erfindung.

The invention is explained in more detail below on the basis of preferred exemplary embodiments with reference to the accompanying drawings.

• 1 shows a simplified circuit diagram of a preferred exemplary embodiment of the reference voltage source according to the invention,
• 2 shows a simplified circuit diagram of a known reference voltage source,
• 3 shows a refined embodiment of the reference voltage source according to the invention, and
• FIG. 4 shows a further refined and actually implemented embodiment of the reference voltage source of the present invention shown in FIG. 3.

In the simplified circuit shown in FIG. 1, which corresponds to a preferred exemplary embodiment of a reference voltage source according to the present invention, the previously described principle known per se is used in turn to add the reference voltage by adding a component with a negative temperature coefficient and a component with a positive temperature coefficient generate, whereby by suitable circuit dimensioning the negative temperature coefficient can be compensated for by the positive temperature coefficient. According to the exemplary embodiment shown in FIG. 1, however, the portion of the generated reference voltage which is subject to a positive temperature coefficient is the difference between two summation voltages from a plurality of forward voltages of pn junctions through which different current densities flow. Furthermore, the portion that is subject to the negative temperature coefficient comprises the sum of the forward voltages of several pn junctions.

. Die Basisanschlüsse der Transistoren T₁ und T₂ sind voneinander getrennt an die Emitter weiterer npn-Bipolartransistoren T₃ bzw. T₄ angeschlossen. Die Emitterflächen A_E3 und A_E4 der Transistoren T₃ bzw. T₄ stehen zueinander im Verhältnis 1:n₂. Die Transistoren T₃ und T₄ werden von unterschiedlichen Strömen I₃ und I₄ durchflossen, welche über Widerstände R₃ und R₄ eingestellt werden können. Die Kollektoren der Transistoren T₃ und T₄ sind gemäß Fig. 1 an ein positives Versorgungsspannungspotential V_cc angeschlossen. Die Basisanschlüsse der Transistoren T₃ und T₄ sind miteinander verbunden. Des weiteren sind die Widerstände R₁ und R₂ mit den Transistoren T₁ bzw. T₂ in Übereinstimmung mit der in Fig. 2 gezeigten bekannten Referenzspannungsquelle verschaltet.The circuit shown in FIG. 1 again comprises npn transistors T ₁ and T ₂ , the emitter areas A _E1 and A _{E2 of which are} in the ratio 1: n ₁ . The transistors T ₁ and T ₂ are operated with collector currents I ₁ and I ₂ , respectively, which are compared by a current mirror circuit S ₁ , the current strengths of these currents I ₁ and I ₂ being predetermined by the transistors T ₁ and T ₂ . The currents I ₁ and I ₂ are related to each other ${\text{m}}_{\text{1}}{\text{= I}}_{\text{1}}{\text{/ I}}_{\text{2nd}}$

. The base connections of the transistors T ₁ and T ₂ are separately connected to the emitters of further npn bipolar transistors T ₃ and T ₄ . The emitter areas A _E3 and A _{E4 of} the transistors T ₃ and T ₄ are in a ratio of 1: n ₂ . The transistors T ₃ and T ₄ are flowed through by different currents I ₃ and I ₄ , which can be set via resistors R ₃ and R ₄ . 1, the collectors of the transistors T ₃ and T ₄ are connected to a positive supply voltage _potential V _CC . The base connections of the transistors T ₃ and T ₄ are connected to one another. Furthermore, the resistors R ₁ and R _{2 are} connected to the transistors T ₁ and T ₂ in accordance with the known reference voltage source shown in FIG. 2.

A diode D or a corresponding pn junction is coupled to the resistor R ₃ . The voltage across resistor R ₄ corresponds to the difference between the emitter-base voltages of transistors T ₃ and T ₄ . So that the ratio of the emitter currents of these transistors is temperature stable, the voltage across resistor R ₃ must also be proportional to temperature. This is achieved with the aid of the diode D, since the voltage at R ₁ increases in proportion to the temperature and the forward voltages of the bipolar transistor T ₁ and the diode D do not differ significantly, so that the voltage across the resistor R _3, as desired, is proportional to the temperature.

In the reference voltage source shown in FIG. 1, the desired reference or output voltage is tapped at the common base connection of the bipolar transistors T ₃ and T ₄ . This output voltage corresponds to the total voltage from the base-emitter voltages of the transistors T ₃ and T ₁ and the voltage present at the node between the resistors R ₁ and R ₂ . The base-emitter voltages of the transistors T ₃ and T _{1 are} known to have a negative temperature coefficient of approximately -2 mV / K. The voltage present at the node between the resistors R ₁ and R ₂ is determined by the base-emitter voltages of the transistors T ₁ -T ₄ and corresponds in particular to the difference between a first voltage and the sum of the forward voltages of those through which a high current density flows Transistors T ₁ and T ₃ depends, and a second voltage, which depends on the sum of the forward voltages of the bipolar transistors T ₂ and T ₄ through which a low current density flows. That is, the voltage present at the node between the resistors R ₁ and R ₂ depends on the difference between the sum of the base-emitter voltages of the transistors T ₁ and T ₃ and the sum of the base-emitter voltages of the transistors T ₂ and T ₄ from. By suitable Dimensioning of the components shown in Fig. 1 or the currents supplied to the individual bipolar transistors can be achieved that the differential voltage present at the node between the resistors R ₁ and R ₂ has such a positive temperature coefficient which the negative temperature coefficient of the base-emitter voltages the bipolar transistors T ₃ and T ₁ compensated. In this case, the positive temperature coefficient of the differential voltage drop across the resistor R ₁ must be as high as the negative temperature coefficient of the base-emitter voltages of the transistors T ₃ and T ₁ and consequently be approximately + 4mV / K. Thus, at room temperature (300K), a voltage drop of approximately 1.2 V must occur at R ₁ , so that the output voltage finally tapped at the common base connection of the bipolar transistors T ₃ and T _{4 is} approximately 2.5 V (= 1.2 V + 2x650 mV) , which is twice as high as in the known reference voltage source shown in FIG. 2, so that the reference voltage source shown in FIG. 1 is in principle a double bandgap reference voltage source.

The voltage of approximately 2.5 V present at the common base of the transistors T ₃ and T ₄ is sufficiently high for most applications, so that in principle the use of a voltage divider with resistors R ₅ and R ₆ for high multiplication of the reference voltage can be omitted . Therefore, in the circuit shown in FIG. 1, the voltage divider with the resistors R ₅ and R _{6 is} only shown in broken lines.

Of course, the circuit shown in Fig. 1 can be modified in a simple manner such that not only the difference is formed from two summation voltages, but that the difference is formed from several summation voltages by using a correspondingly larger number of bipolar transistors, each of these summation voltages corresponds to an addition of even three or more forward voltages of pn junctions through which different current densities flow. In this way, the circuit shown in FIG. 1 can be modified in such a way that a voltage which corresponds to a multiple of the bandgap of silicon is generally tapped at the base terminal of the transistor T ₃ .

With regard to the circuit shown in FIG. 1, it should be noted that the emitter current of the bipolar transistor T ₄ can be chosen to be very small, since the greatest thermal leakage current from the collector of each npn transistor to the substrate in barrier-layer-insulated bipolar technologies does not enter the emitter current of the in the present case corresponding npn transistor is received. For example, if the emitter currents of the bipolar transistors T ₃ and T _{4 are} 10 μA and 0.5 μA (ratio 1:20), the emitter area ratios n ₁ and n _{2 are} each 4 and the collector currents I ₁ , I _{2 of} the bipolar transistors T ₁ , T _{2 of the} same size (ie m ₁ = 1), the previously explained differential voltage of the sums of the individual forward voltages is approximately 150 mV. A deviation of the temperature of one of the bipolar transistors T ₁ - T ₄ by 1K is only 1.3% in this differential voltage, so that the reference voltage circuit shown in Fig. 1 is less sensitive to temperature fluctuations or temperature gradients. In addition, it is simpler to arrange the transistors shown in FIG. 1 crosswise in the layout of the circuit actually implemented in such a way that linear temperature gradients from any direction cannot falsify the output voltage at the common base connection of the bipolar transistors T ₃ and T ₄ .

The resistance ratio R ₁ : R _{2 can be set} to 4: 1 by a clever choice of the individual components shown in FIG. 1. This is a ratio that can be adjusted particularly precisely. The current mirror S ₁ can be special be manufactured precisely if the current ratio I ₁ : I _{2 is} 1: 1, ie m ₁ = 1.

As in the known reference voltage source shown in FIG. 2, an actuator ST is again coupled to the output terminal of the current mirror S _{1 in the} circuit shown in FIG. 1, which is controlled as a function of the comparison result of the current mirror S1 in order to avoid an uneven load on the latter Output connection to allow readjustment of the output voltage V _ref .

The general principle on which the present invention is based was explained with reference to FIG. 1. 3 shows a refined exemplary embodiment of the reference voltage source according to the invention, the corresponding components being provided with the same reference numerals and a repeated description of these components being dispensed with.

According to FIG. 3, a further current mirror circuit S _{2 is} used, which compares collector currents I ₇ and I ₈ from further transistors T ₇ and T ₈ and controls the actuator ST depending on the comparison result. These bipolar transistors T ₃ and T ₄ form an amplifier stage in order to keep the current consumption of the reference voltage source shown in FIG. 3 as low as possible. With current mirror S ₁ , the inputs correspond to the outputs and are connected to the base connections of transistors T ₇ and T ₈ . Another npn bipolar transistor T ₅ , together with another current mirror circuit S _3, serves to compensate for the errors arising from the base current of transistor T ₂ . By using the npn bipolar transistor T ₆ shown in FIG. 3 it can be achieved that the thermal leakage currents of the bipolar transistors T ₁ and T ₅ from their collectors to the substrate compared to the thermal leakage currents of the bipolar transistors T ₂ and T ₆ cancel if the ratio of the current mirror S _{1 is} 1: 1. The bipolar transistor T ₅ has an emitter area corresponding to the emitter area of the bipolar transistor T ₂ , while the bipolar transistor T _{6 has} an emitter area corresponding to the emitter area of the bipolar transistor T ₁ , ie the emitter area of the bipolar transistor T ₅ is n ₁ times as large as the emitter area of the bipolar transistor M ₆ .

A circuit arrangement is coupled to the resistor R ₃ , which, in addition to the diode D already shown in FIG. 1 in accordance with FIG. 3, has connected resistors R ₇ -R ₉ and a further bipolar transistor T ₉ . This circuit arrangement works as follows. At low temperatures, the current flow through the resistor R _{3 is} smallest and the flow voltages of all pn junctions are so high that the resistors R7 and R8 essentially determine the behavior of this circuit arrangement. At medium temperatures, the path leading via the diode D and the resistor R _{9 dominates} , in which case the resistance of the equivalent circuit diagram of this circuit arrangement is lower due to the parallel connection of R ₈ and R ₇ to R ₉ and the diode voltage by the factor (R ₈ + R ₇ ) / (R ₇ + R ₈ + R ₉ ) is divided down. At high temperatures, on the other hand, the path leading through transistor T ₉ dominates, the equivalent circuit diagram having a diode forward voltage increased by the factor (R ₇ + R ₈ ) / R ₇ without series resistance. This results in a sectionally linear temperature response at the collector of the bipolar transistor T ₉ , which proceeds approximately according to a parabolic function, so that, with the correct dimensioning of this circuit arrangement, the parabolic temperature dependence of the reference voltage that remains despite the temperature stabilization as a result of the differential voltage formation can be compensated. The reference voltage generated can thus ideally be within of a 0.03% window can be generated in a temperature-stable manner. Finally, in FIG. 3, a voltage divider with resistors R ₅ and R _{6 is also connected} to the common base connection of the transistors T ₃ and T ₄ in order to multiply the base voltage of these transistors and to obtain the desired reference voltage V _ref .

FIG. 4 shows an example of a double band gap reference voltage source implemented on a test chip according to the present invention. Again, those components that correspond to the components shown in FIG. 3 are given the same reference numerals and will not be explained again.

4, two p-channel MOS field effect transistors M ₁ and M _{2 form} the current mirror S ₁ shown in FIG. 3, the common gate connection of these transistors M ₁ and M ₂ to the common emitter connection of transistors T ₇ and T ₈ is laid. . The current mirror S ₃ shown in Figure 3 includes p-channel MOS field effect transistors M ₃ - M ₆ and n-channel MOS field effect transistors M ₇ - M _10. The current mirror circuit S ₂ , however, is implemented by a pnp bipolar transistor T ₁₁ . 4, the reference potential of the current mirrors S ₁ and S ₃ corresponds to the input potential of the actuator ST, which is realized by an actuating transistor M ₁₁ . Furthermore, the reference potential of the current mirror S _{2 is} connected to the reference potential of the control transistor M ₁₁ . However, the previously described relationship of the reference potentials is not absolutely necessary.

The resistor R ₁₀ additionally shown in FIG. 4 serves to compensate for the thermal leakage current of the resistor R ₄ . The components T ₁₂ , T ₁₃ , C ₁ - C ₃ and R ₁₁ serve to stabilize the circuit.

Finally, the diode D shown in FIG. 3 is realized by the pn junction of a further bipolar transistor T ₁₀ , the base-collector path of which is short-circuited. Otherwise, the mode of operation of the reference voltage source shown in FIG. 4 corresponds to that of the circuits shown in FIGS. 1 and 3.

Claims (19)

Reference voltage generating circuit, with first circuit means (T ₁ , T ₃ ) for generating a first voltage which is subject to a negative temperature coefficient, and with second circuit means (T ₁ - T ₄ , R ₁ - R ₄ ) for generating a differential voltage from a second voltage and a third voltage, the second voltage and the third voltage each being derived from forward voltages of corresponding pn junctions and the differential voltage one subject to positive temperature coefficients,
wherein the reference voltage (V _ref ) can be _tapped as the sum of the first voltage of the first switching means (T ₁ , T ₃ ) and the differential voltage of the second switching means (T ₁ - T ₄ , R ₁ - R ₄ ),
characterized, that the first circuit means (T ₁ , T ₃ ) are designed and arranged such that they derive the first voltage from a sum voltage of at least two forward voltages of corresponding pn junctions, and that the second circuit means (T ₁ - T ₄ , R ₁ - R ₄ ) are designed and arranged in such a way that they derive the second voltage or the third voltage from a first or second total voltage of at least two forward voltages of corresponding pn junctions and generate the differential voltage therefrom. Reference voltage generating circuit according to claim 1,
characterized, that the second circuit means (T ₁ - T ₄ , R ₁ - R ₄ ) are designed and arranged such that they have the second voltage or the third voltage from a first summation voltage or a second summation voltage of at least two forward voltages each different Derive current-densely flowing pn junctions. Reference voltage generating circuit according to claim 1 or 2,
characterized, that the second circuit means comprise first, second, third and fourth bipolar transistors (T ₁ - T ₄ ) which are flowed through with a first, second, third and fourth current density and are connected in such a way that the second voltage from the total voltage of the forward voltages of the first and third bipolar transistors (T ₁ , T ₃ ) and the third voltage is derived from the sum voltage of the forward voltages of the second and fourth bipolar transistors (T ₂ , T ₄ ), the first and third bipolar transistors (T ₁ , T ₃ ) being included a higher current density than the second and fourth bipolar transistor (T ₂ , T ₄ ) and that the first and third bipolar transistor (T ₁ , T ₃ ) is also part of the first circuit means such that the first voltage from the total voltage of the forward voltages of the first and third bipolar transistors (T ₁ , T ₃ ) is derived. Reference voltage generating circuit according to claim 3,
characterized, that the emitter area of the second bipolar transistor (T ₂ ) corresponds to a multiple of the emitter area of the first bipolar transistor (T ₁ ) and the emitter area of the fourth bipolar transistor (T ₄ ) corresponds to a multiple of the emitter area of the third bipolar transistor (T ₃ ). Reference voltage generating circuit according to claim 3 or 4,
characterized, that the collector of the first bipolar transistor (T ₁ ) first current, a second current is supplied to the collector of the second bipolar transistor (T ₂ ), a third current is supplied to the collector of the third bipolar transistor (T ₃ ) and a fourth current is supplied to the collector of the fourth bipolar transistor (T ₄ ), that the base of the first bipolar transistor (T ₁ ) with the emitter of the third bipolar transistor (T ₃ ) and the emitter of the first bipolar transistor (T ₁ ) via a first resistor (R ₁ ) with a negative supply voltage connection and via a second resistor (R ₂ ) is connected to the emitter of the second bipolar transistor (T ₂ ), that the base of the second bipolar transistor (T ₂ ) is connected to the emitter of the fourth bipolar transistor (T ₄ ), the node between the base of the first bipolar transistor (T ₁ ) and the emitter of the third bipolar transistor (T ₃ ) via a third resistor (R ₃ ) to the negative supply voltage connection and via a fourth resistor (R ₄ ) to the node between the base of the second bipolar transistor (T ₂ ) and the emitter of the fourth bipolar transistor (T ₄ ), and that the base of the third bipolar transistor (T ₃ ) is connected to the base of the fourth bipolar transistor (T ₄ ), so that the sum voltage of the base-emitter voltages of the third bipolar transistor (T ₃ ) and the first bipolar transistor (T1) of the first voltage and that on the first resistor (R ₁ ) falling voltage corresponds to the differential voltage and the reference voltage (V _ref ) is tapped at the base of the third bipolar transistor (T ₃ ) that can. Reference voltage generating circuit according to claim 5,
characterized, that the emitter area of the second bipolar transistor (T ₂ ) is approximately four times as large as the emitter area of the first bipolar transistor (T ₁ ) and the emitter area of the fourth Bipolar transistor (T ₄ ) is approximately four times as large as the emitter area of the third bipolar transistor (T ₃ ), that the first current supplied to the first bipolar transistor (T ₁ ) is approximately the same size as the second current supplied to the second bipolar transistor (T ₂ ), and that the first resistor (R ₁ ) is approximately four times the size of the second resistor (R ₂ ). Reference voltage generating circuit according to claim 5 or 6,
characterized, that the third or fourth bipolar transistor (T ₃ , T ₄ ) and the third and fourth resistor (R ₃ , R ₄ ) are dimensioned such that the emitter current of the fourth bipolar transistor (T ₄ ) is significantly smaller than the emitter current of the third bipolar transistor (T ₃ ). Reference voltage generating circuit according to one of claims 5 to 7,
marked by a current mirror circuit (S ₁ ) which is connected on the one hand to a positive supply voltage connection and on the other hand supplies the first current supplied to the first bipolar transistor (T ₁ ) and the second current supplied to the second bipolar transistor (T ₂ ). Reference voltage generating circuit according to claim 8,
characterized, that a fifth bipolar transistor (T ₅ ) is connected between the current mirror circuit (S ₁ ) and the collector of the first bipolar transistor (T ₁ ), and that between the base of the fifth bipolar transistor (T ₅ ) and the node between the base of the second bipolar transistor (T ₂ ) and the emitter of the fourth bipolar transistor (T ₄ ) another current mirror circuit (S ₃ ) is connected. Reference voltage generating circuit according to claim 9,
characterized, that a sixth bipolar transistor (T ₆ ) with a short-circuited base-collector path is connected between the current mirror circuit (S ₁ ) and the collector of the second bipolar transistor (T ₂ ). Reference voltage generating circuit according to claim 10,
characterized, that the emitter area of the sixth bipolar transistor (T ₆ ) corresponds approximately to the emitter area of the first bipolar transistor (T ₁ ) and the emitter area of the fifth bipolar transistor (T ₅ ) approximately corresponds to the emitter area of the second bipolar transistor (T ₂ ) and the transmission ratio of the current mirror circuit (S ₁ ) is 1: 1. Reference voltage generating circuit according to one of claims 5 to 11,
characterized, that a further current mirror circuit (S ₂ ) is provided, which is connected to a positive supply voltage connection (V _cc ) and supplies the third current supplied to the third bipolar transistor (T ₃ ) and the fourth current supplied to the fourth bipolar transistor (T ₄ ), and that an amplifier circuit (T ₇ , T ₈ ) is connected between the further current mirror circuit (S ₂ ) and the collectors of the third or fourth bipolar transistor (T ₃ , T ₄ ). Reference voltage reference circuit according to one of the preceding claims,
marked by third circuit means (D, T ₉ , R ₇ - R ₉ ) for compensating for a parabolic temperature dependence of the reference voltage (V _ref ) generated by the second circuit means (T ₃ , R ₃ ). Reference voltage reference circuit according to claim 13 and one of claims 5 to 12,
characterized, that the third circuit means (D, T ₉ , R ₇ - R ₉ ) comprise a diode (D) connected between the third resistor (R ₃ ) and the negative supply voltage connection. Reference voltage generating circuit according to claim 14,
characterized, that the third circuit means comprise a parallel circuit connected between the third resistor (R ₃ ) and the negative supply voltage connection, comprising a series circuit of a resistor (R ₉ ) with the diode (D) and a series circuit of two further resistors (R ₇ , R ₈ ), wherein a further bipolar transistor (T ₉ ) with its main current path parallel to the two further resistors (R ₇ , R ₈ ) and with its base connected to the node between the two further resistors (R ₇ , R ₈ ). Reference voltage generating circuit according to one of the preceding claims,
characterized, that the first circuit means comprise amplifier means (R ₅ , R ₆ ) for amplifying the reference voltage (V _ref ). Reference voltage generating circuit according to one of Claims 5 to 12 and Claim 16,
characterized, that the amplifier means comprise a voltage divider (R ₅ , R ₆ ) acting on the base of the third bipolar transistor (T ₃ ). Reference voltage generating circuit according to one of the preceding claims,
characterized, that the first and second circuit means (T ₁ - T ₄ , R ₁ -R ₄ ) are designed such that the sum of the first voltage of the first circuit means (T ₃ , T ₁ ) and the differential voltage of the second circuit means (T ₁ - T ₄ ) generated reference voltage (V _ref ) is approximately 2.5 V. Reference voltage generating circuit according to one of the preceding claims,
characterized, that control means (ST, M ₁₁ ) are provided in order to keep the reference voltage (V _ref ) output by the reference voltage generating _circuit at an output connection constant in the event of an uneven load on the output voltage connection.

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