EP0929910A1 - Vertical power mosfet - Google Patents

Vertical power mosfet

Info

Publication number
EP0929910A1
EP0929910A1 EP98947303A EP98947303A EP0929910A1 EP 0929910 A1 EP0929910 A1 EP 0929910A1 EP 98947303 A EP98947303 A EP 98947303A EP 98947303 A EP98947303 A EP 98947303A EP 0929910 A1 EP0929910 A1 EP 0929910A1
Authority
EP
European Patent Office
Prior art keywords
zone
zones
additional zones
power mosfet
vertical power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98947303A
Other languages
German (de)
French (fr)
Inventor
Gerald Deboy
Jenoe Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0929910A1 publication Critical patent/EP0929910A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body

Definitions

  • the invention relates to a vertical power MOSFET with a semiconductor body with an inner zone of the first conductivity type and a predetermined doping concentration, with at least one base zone of the second conductivity type adjacent to the inner zone and a first surface of the semiconductor body, in each of which at least one source zone is embedded , with at least one drain zone adjoining one of the surfaces of the semiconductor body, with additional zones of the second conduction type arranged in the inner zone essentially within the space charge zone spanning the blocking voltage, with at least one additional zone between these additional zones and doped higher than the inner zone from first conductivity type and with a doping level of the additional zones and with distances of the additional zones of the second conductivity type from one another such that their charge carriers are largely eliminated when the reverse voltage is applied.
  • Such a vertical power MOSFET is described for example in DE 43 09 764 C2.
  • This known vertical power MOSFET which is shown in section in the attached FIG. 3, has a lightly n-doped inner zone 1.
  • Base zones 3 of the p-conductivity type are embedded in the upper surface 2 of a semiconductor body.
  • Source zones 4 of the n + line type are embedded in the base zones 3.
  • a gate electrode 8 is provided insulated above the surface 2.
  • a highly doped drain zone 7 of the same conductivity type as the inner zone 1 is arranged on the other surface 6.
  • Additional semiconductor zones 11, 12 are provided in the inner zone 1 in the region of the space charge zone spanning at blocking voltage.
  • Additional zones 12 doped higher than the inner zone and of the same n-conduction type as the inner zone 1 are arranged between the zones 11.
  • the zones 11, 12 are columnar.
  • the additional zones 11 of the opposite conduction type can also be arranged in the form of a rod. They are then surrounded on all sides by a single zone 12. Like zones 12, this single zone has the same conductivity type as inner zone 1, but it has a higher doping.
  • the power MOSFET If there is a voltage in the forward direction on the power MOSFET according to FIG. 3, it can be controlled in a conductive manner via the gate electrode 8. Here, the electrons originating from a source zone 4 find a high doping in the additional zones 12. The path resistance of the power MOSFET is thus reduced.
  • a space charge zone is formed starting from the pn junction between the inner zone 1 and the base zone 3, the expansion of which increases with the reverse voltage increasing. If the space charge zone abuts the p-doped zones 11, these are conductively connected to the base zones 3 via the cleared area of the inner zone 1. A high ear connection is not desirable because of the dynamic properties. If the reverse voltage increases further, the space charge zone expands further, so that some of the charge carriers also come from
  • Zones 11 and 12 are cleared. This is shown schematically by a dashed line 13.
  • the charge carriers are then from a large part of the inner zone 1 and from the Zones 11, 12 completely cleared.
  • the space charge zone thus takes a course in the inner zone 1, which is delimited by a dashed line 14. With the maximum reverse voltage present, the additional zones 11, 12 are completely in the space charge zone.
  • the removal of the charge carriers has the effect as if zones 11 and 12 were not present.
  • the maximum extent of the space charge zone is exclusively the doping of the inner zone 1.
  • the degree of compensation that is to say the total balance of the sum of the charges in zones 11 ("p-pillars") and the sum of the charges in zones 12 ("n-pillars") and the surrounding areas, is chosen to be low enough, then with block this component without difficulty 1,000 V and more.
  • this power MOSFET has a resistance that corresponds to that of a significantly lower blocking MOSFET.
  • the blocking behavior is determined by the "height" of zones 11, 12 and the degree of compensation.
  • the sheet resistance can be set by the distance a of the zones 11, 12 from the first surface 2. It can also be influenced by the doping of the zones 12.
  • the doping and the thickness of the zones 11, 12 are set such that the charge carriers from these zones 11, 12 are completely cleared out when the maximum reverse voltage is applied.
  • the FREDFET Fluorescence Epitaxial Diode-FET
  • the reverse recovery behavior (“backward recovery behavior”), however, is not optimal due to the desired transistor properties with regard to current stall, level and time course of the reverse current peak.
  • Zones of the first conduction type are reduced and that the thickness dimensioning of the additional zones is selected such that the space charge zone spanning at blocking voltage faces away from the first surface of the semiconductor body Transition between the additional zones of the first line type and the inner zone practically does not exceed.
  • the invention is based on the knowledge that the doping concentration of the additional zones is the same
  • Conduction type like the inner zone is on average about an order of magnitude above the doping concentration of the substrate receiving the same reverse voltage, which is, for example, n " -doped. Therefore, the charge carrier lifetime can be determined by diffusion of platinum, gold etc. or by irradiation with electrons or helium are reduced more by at least the same amount before negative effects on the specific resistance of the MOSFET occur as a result of the compensating effect of the lifetime adjustment on the doping of the current-carrying regions.
  • the thickness dimensioning of the additional zones forming an active layer is optimally selected such that the space charge zone does not reach the (rear) n ⁇ / n + transition between the inner zone and the drain zone facing away from the first surface of the semiconductor body at full reverse voltage.
  • An example of this is a thickness of approximately below 10 ⁇ m for a reverse voltage of 400 V.
  • FIG. 1 shows a section through the vertical power MOSFET according to the invention
  • FIG. 2 (a) to (c) are schematic representations to explain the manufacture of the power MOSFET and
  • Figure 3 shows a section through an existing vertical power MOSFET.
  • the n-type zones 11 are doped by diffusion with platinum, gold, etc., in order to reduce the charge carrier life in these zones.
  • This reduction in the lifetime of the charge carrier can also be achieved by irradiation with electrons or helium.
  • effects on the specific resistance of the MOSFET as a result of the compensating effect of the reduction in the carrier lifetime are prevented.
  • the thickness dimensioning of the additional zones 11, 12 is selected such that the space charge zone does not reach the "rear” n + / n " transition between the inner zone 1 and the drain zone 7 at full blocking voltage and practically at the transition between the additional zones 11, 12 and inner zone 1 ends.
  • the inner zone 1 can be p-doped, while the zones 11 are n-doped and the zones 12, like the inner zone 1, are p-doped. It is also possible in a p-type inner zone 1 to provide only one n-type zone 11 (“column”) or only one p-type zone 11 in an n-type inner zone 1.
  • the zones 11, 12 can be used as "p-pillars" for the zones 11 in an n-epitaxial layer for the zones 12 (see FIG. 2 (c)) or as "n-pillars” for the zones 12 in a p- Epitaxial layer for the zones 11 (see FIG. 2 (b)) can be produced. It is also possible to introduce the zones 11, 12 as “n-pillars” and “p-pillars” in an n ⁇ or p ⁇ epitaxial layer (see FIG. 2 (a)). The variant of FIG. 2 (c) has proven to be particularly advantageous.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a vertical power MOSFET, comprising additional zones (11, 12) arranged in an inner zone (1), said zones having the same and inverse type of conductivity as the inner zone (1). The charge carrier service life is reduced in the additional zones (12) having the same conductivity as the inner zone (1). The additional zones (11, 12) are dimensioned in such a way that the space charge zone practically does not exceed the edge opposite to the upper surface of the MOSFET in the additional zone (12) having the same conductivity as the inner zone (1).

Description

Beschreibungdescription
Vertikaler Leistungs-MOSFETVertical power MOSFET
Die Erfindung betrifft einen vertikalen Leistungs-MOSFET mit einem Halbleiterkörper mit einer Innenzone vom ersten Leitungstyp und vorgegebener Dotierungskonzentration, mit mindestens einer an der Innenzone und an eine erste Oberfläche des Halbleiterkörpers angrenzenden Basiszone vom zweiten Lei- tungstyp, in die jeweils mindestens eine Sourcezone eingebettet ist, mit mindestens einer an eine der Oberflächen des Halbleiterkörpers angrenzenden Drainzone, mit in der Innenzone im wesentlichen innerhalb der sich bei Sperrspannung aufspannenden Raumladungszone angeordneten zusätzlichen Zonen des zweiten Leitungstyps, mit mindestens einer zwischen diesen zusätzlichen Zonen liegenden, höher als die Innenzone dotierten zusätzlichen Zone vom ersten Leitungstyp und mit einer Dotierungshöhe der zusätzlichen Zonen und mit Abständen der zusätzlichen Zonen des zweiten Leitungstyps voneinander derart, daß ihre Ladungsträger bei angelegter Sperrspannung weitgehend ausgeräumt sind.The invention relates to a vertical power MOSFET with a semiconductor body with an inner zone of the first conductivity type and a predetermined doping concentration, with at least one base zone of the second conductivity type adjacent to the inner zone and a first surface of the semiconductor body, in each of which at least one source zone is embedded , with at least one drain zone adjoining one of the surfaces of the semiconductor body, with additional zones of the second conduction type arranged in the inner zone essentially within the space charge zone spanning the blocking voltage, with at least one additional zone between these additional zones and doped higher than the inner zone from first conductivity type and with a doping level of the additional zones and with distances of the additional zones of the second conductivity type from one another such that their charge carriers are largely eliminated when the reverse voltage is applied.
Ein derartiger vertikaler Leistungs-MOSFET ist beispielsweise in der DE 43 09 764 C2 beschrieben.Such a vertical power MOSFET is described for example in DE 43 09 764 C2.
Dieser bekannte vertikale Leistungs-MOSFET, der im Schnitt in der beigefügten Fig. 3 dargestellt ist, hat eine niedrig n- dotierte Innenzone 1. In die obere Oberfläche 2 eines Halbleiterkörpers sind Basiszonen 3 des p-Leitungstyps eingela- gert. In die Basiszonen 3 sind Sourcezonen 4 des n+-Leitungε- typs eingebettet. Isoliert über der Oberfläche 2 ist eine Gateelektrode 8 vorgesehen. An der anderen Oberfläche 6 ist einen hochdotierte Drainzone 7 vom gleichen Leitungstyp wie die Innenzone 1 angeordnet . In der Innenzone 1 sind im Bereich der sich bei Sperrspannung aufspannenden Raumladungszone zusätzliche Halbleiterzonen 11, 12 vorgesehen. Es sind mindestens zwei Zonen 11 des der Innenzone 1 entgegengesetzten Leitungstyps vorhanden. Zwischen den Zonen 11 sind höher als die Innenzone dotierte zusätzliche Zonen 12 des der Innenzone 1 gleichen n-Leitungstyps angeordnet. Die Zonen 11, 12 sind säulenförmig ausgebildet. Die zusätzlichen Zonen 11 des entgegengesetzten Leitungstyps können auch stabförmig angeordnet werden. Sie sind dann von ei- ner einzigen Zone 12 allseitig umgeben. Diese einzige Zone hat ebenso wie die Zonen 12 den gleichen Leitungstyp wie die Innenzone 1, sie weist jedoch eine höhere Dotierung auf.This known vertical power MOSFET, which is shown in section in the attached FIG. 3, has a lightly n-doped inner zone 1. Base zones 3 of the p-conductivity type are embedded in the upper surface 2 of a semiconductor body. Source zones 4 of the n + line type are embedded in the base zones 3. A gate electrode 8 is provided insulated above the surface 2. A highly doped drain zone 7 of the same conductivity type as the inner zone 1 is arranged on the other surface 6. Additional semiconductor zones 11, 12 are provided in the inner zone 1 in the region of the space charge zone spanning at blocking voltage. There are at least two zones 11 of the conduction type opposite to the inner zone 1. Additional zones 12 doped higher than the inner zone and of the same n-conduction type as the inner zone 1 are arranged between the zones 11. The zones 11, 12 are columnar. The additional zones 11 of the opposite conduction type can also be arranged in the form of a rod. They are then surrounded on all sides by a single zone 12. Like zones 12, this single zone has the same conductivity type as inner zone 1, but it has a higher doping.
Liegt am Leistungs-MOSFET nach Fig. 3 eine Spannung in Durch- laßrichtung an, so kann er über die Gateelektrode 8 leitend gesteuert werden. Hierbei finden die aus einer Sourcezone 4 stammenden Elektronen in den zusätzlichen Zonen 12 eine hohe Dotierung vor. Damit verringert sich der Bahnwiderstand des Leistungs-MOSFETs .If there is a voltage in the forward direction on the power MOSFET according to FIG. 3, it can be controlled in a conductive manner via the gate electrode 8. Here, the electrons originating from a source zone 4 find a high doping in the additional zones 12. The path resistance of the power MOSFET is thus reduced.
Liegt am Leistungs-MOSFET eine Sperrspannung an, so bildet sich ausgehend vom pn-Obergang zwischen der Innenzone 1 und der Basiszone 3 eine Raumladungszone aus, deren Ausdehnung mit steigender Sperrspannung anwächst. Stößt die Raumladungs- zone an die p-dotierten Zonen 11 an, so werden diese über das ausgeräumte Gebiet der Innenzone 1 leitend an die Basiszonen 3 angeschlossen. Eine hochohrnige Verbindung ist wegen der dynamischen Eigenschaften an sich nicht erwünscht. Bei weiter ansteigender Sperrspannung dehnt sich die Raumladungszone weiter aus, so daß auch ein Teil der Ladungsträger aus denIf a reverse voltage is present at the power MOSFET, a space charge zone is formed starting from the pn junction between the inner zone 1 and the base zone 3, the expansion of which increases with the reverse voltage increasing. If the space charge zone abuts the p-doped zones 11, these are conductively connected to the base zones 3 via the cleared area of the inner zone 1. A high ear connection is not desirable because of the dynamic properties. If the reverse voltage increases further, the space charge zone expands further, so that some of the charge carriers also come from
Zonen 11 und 12 ausgeräumt wird. Dies ist durch eine gestrichelte Linie 13 schematisch dargestellt.Zones 11 and 12 are cleared. This is shown schematically by a dashed line 13.
Bei weiterer Steigerung der Sperrspannung sind dann die La- dungsträger aus einem großen Teil der Innenzone 1 und aus den Zonen 11, 12 vollständig ausgeräumt. Die Raumladungszone nimmt damit in der Innenzone 1 einen Verlauf an, der durch eine gestrichelte Linie 14 begrenzt ist. Bei maximal anliegender Sperrspannung liegen so die zusätzlichen Zonen 11, 12 vollständig in der Raumladungszone.If the reverse voltage increases further, the charge carriers are then from a large part of the inner zone 1 and from the Zones 11, 12 completely cleared. The space charge zone thus takes a course in the inner zone 1, which is delimited by a dashed line 14. With the maximum reverse voltage present, the additional zones 11, 12 are completely in the space charge zone.
Das Ausräumen der Ladungsträger hat die Wirkung, als ob die Zonen 11 und 12 nicht vorhanden wären. Bei maximaler Ausdehnung der Raumladungszone ist also in erster Näherung aus- schließlich die Dotierung der Innenzone 1 maßgebend. Wird der Kompensationsgrad, also die Gesamtbilanz der Summe der Ladungen in den Zonen 11 ("p-Säulen") und der Summe der Ladungen in den Zonen 12 ("n-Säulen") sowie der umgebenden Bereiche niedrig genug gewählt, so lassen sich mit diesem Bauelement ohne weiteres 1.000 V und mehr sperren. Im Durchlaßfall hat dagegen dieser Leistungs-MOSFET einen Widerstand, der dem eines erheblich niedriger sperrenden MOSFET entspricht. Das Sperrverhalten wird durch die "Höhe" der Zonen 11, 12 und den Kompensationsgrad bestimmt.The removal of the charge carriers has the effect as if zones 11 and 12 were not present. In the first approximation, the maximum extent of the space charge zone is exclusively the doping of the inner zone 1. If the degree of compensation, that is to say the total balance of the sum of the charges in zones 11 ("p-pillars") and the sum of the charges in zones 12 ("n-pillars") and the surrounding areas, is chosen to be low enough, then with block this component without difficulty 1,000 V and more. In the forward case, however, this power MOSFET has a resistance that corresponds to that of a significantly lower blocking MOSFET. The blocking behavior is determined by the "height" of zones 11, 12 and the degree of compensation.
Der Bahnwiderstand läßt sich durch den Abstand a der Zonen 11, 12 von der ersten Oberfläche 2 einstellen. Er läßt sich außerdem durch die Dotierung der Zonen 12 beeinflussen.The sheet resistance can be set by the distance a of the zones 11, 12 from the first surface 2. It can also be influenced by the doping of the zones 12.
Bei diesem bekannten MOSFET werden die Dotierung und die Dik- ke der Zonen 11, 12 so eingestellt, daß die Ladungsträger aus diesen Zonen 11, 12 bei Anlegen der maximalen Sperrspannung vollständig ausgeräumt sind.In this known MOSFET, the doping and the thickness of the zones 11, 12 are set such that the charge carriers from these zones 11, 12 are completely cleared out when the maximum reverse voltage is applied.
Vertikale MOSFETs, die in der Leistungselektronik eingesetzt werden, bieten an sich im Gegensatz zu anderen Transistorkonzepten, wie beispielsweise einem Bipolartransistor mit isoliertem Gate (IGBT) die Möglichkeit, die durch ein ^-Substrat, eine n"-Epitaxieschicht und eine p-Wanne (vgl. die Be- zugszeichen 7, 1 und 3 in Fig. 3) gebildete Inversdiode als Freilaufdiode einzusetzen. Solche Freilaufdioden werden insbesondere in Pulswechselrichteranwendungen, wie beispielsweise Schaltnetzteilen und Halb- oder Vollbrücken zur Motorsteuerung, benötigt.Vertical MOSFETs that are used in power electronics, in contrast to other transistor concepts, such as an insulated gate bipolar transistor (IGBT), offer the possibility that a ^ substrate, an n " epitaxial layer and a p-well ( cf. reference numerals 7, 1 and 3 in FIG. 3) formed as an inverse diode Use free-wheeling diode. Such freewheeling diodes are required in particular in pulse inverter applications, such as switching power supplies and half or full bridges for motor control.
Derzeit gibt es mit dem FREDFET ("Fast Recovery Epitaxial Di- ode-FET" ) ein Bauelement, dessen Inversdiode in gewisser Weise als Freilaufdiode einsetzbar ist. Das Reverse-Recovery- Verhalten ( "Rückwärts-Erholungsverhalten" ) ist jedoch auf- grund der angestrebten Transistoreigenschaften hinsichtlich Stromabriß, Höhe und zeitlicher Verlauf der Rückstromspitze, nicht optimal.The FREDFET ("Fast Recovery Epitaxial Diode-FET") is currently a component whose inverse diode can be used to a certain extent as a freewheeling diode. The reverse recovery behavior ("backward recovery behavior"), however, is not optimal due to the desired transistor properties with regard to current stall, level and time course of the reverse current peak.
Werden übliche MOSFETs angewendet, so ist ständig eine exter- ne Beschaltung mit eigener Freilaufdiode und einer weiteren Zener-Diode zwischen Drain und Source zum Schutz des MOSFETs vor einem Durchbruch erforderlich. Auch der aus der DE 43 09 764 C2 bekannte und oben anhand der Fig. 3 erläuterte Leistungs-MOSFET ist hinsichtlich der Eigenschaften seiner Inversdiode nicht befriedigend.If conventional MOSFETs are used, external circuitry with their own free-wheeling diode and a further Zener diode between drain and source is constantly required to protect the MOSFET from breakdown. The power MOSFET known from DE 43 09 764 C2 and explained above with reference to FIG. 3 is also unsatisfactory with regard to the properties of its inverse diode.
Es ist daher Aufgabe der vorliegenden Erfindung, einen vertikalen Leistungs-MOSFET zu schaffen, der hinsichtlich der Eigenschaften seiner Inversdiode ohne Verschlechterung der Transistoreigenschaften, insbesondere des spezifischen Widerstandes zwischen Drain und Source, verbessert ist.It is therefore an object of the present invention to provide a vertical power MOSFET which is improved in terms of the properties of its inverse diode without deteriorating the transistor properties, in particular the resistivity between drain and source.
Diese Aufgabe wird bei einem vertikalen Leistungs-MOSFET der eingangs genannten Art erfindungsgemäß dadurch gelöst, daß die Ladungsträger-Lebensdauer mindestens in den zusätzlichenThis object is achieved according to the invention in a vertical power MOSFET of the type mentioned at the outset in that the charge carrier lifetime is at least in the additional
Zonen vom ersten Leitungstyp vermindert ist und daß die Dik- kendi ensionierung der zusätzlichen Zonen so gewählt ist, daß die sich bei Sperrspannung aufspannende Raumladungszone den von der ersten Oberfläche des Halbleiterkörpers abgewandten Übergang zwischen den zusätzlichen Zonen vom ersten Leitungs- typ und der Innenzone praktisch nicht überschreitet.Zones of the first conduction type are reduced and that the thickness dimensioning of the additional zones is selected such that the space charge zone spanning at blocking voltage faces away from the first surface of the semiconductor body Transition between the additional zones of the first line type and the inner zone practically does not exceed.
Die Erfindung geht dabei von der Erkenntnis aus, daß die Do- tierungskonzentration der zusätzlichen Zonen des gleichenThe invention is based on the knowledge that the doping concentration of the additional zones is the same
Leitungstyps wie die Innenzone durchschnittlich um etwa eine Größenordnung über der Dotierungskonzentration des die gleiche Sperrspannung aufnehmenden Substrates, das beispielsweise n"-dotiert ist, liegt. Daher kann die Ladungsträger-Lebens- dauer durch Diffusion von Platin, Gold usw. oder durch Bestrahlung mit Elektronen oder Helium um mindestens den gleichen Betrag stärker abgesenkt werden, bevor negative Auswirkungen auf den spezifischen Widerstand des MOSFETs als Folge der kompensierenden Wirkung der Lebensdauereinstellung auf die Dotierung der stromführenden Gebiete auftreten.Conduction type like the inner zone is on average about an order of magnitude above the doping concentration of the substrate receiving the same reverse voltage, which is, for example, n " -doped. Therefore, the charge carrier lifetime can be determined by diffusion of platinum, gold etc. or by irradiation with electrons or helium are reduced more by at least the same amount before negative effects on the specific resistance of the MOSFET occur as a result of the compensating effect of the lifetime adjustment on the doping of the current-carrying regions.
Es ist also eine wesentlich kürzere Lebensdauer der Ladungsträger erzielbar, wobei Werte für diese angestrebt werden, die unterhalb 0,5 μs liegen sollten. Durch diese geringere Lebensdauer wird ein rascheres Abkommutieren des Stromes erreicht, so daß der MOSFET früher seine Sperrspannung aufnehmen kann. Damit werden die Speicherladung und die Belastung des einschaltenden MOSFETs in einer Voll- oder Halbbrückenkonfiguration entsprechend verringert.It is therefore possible to achieve a significantly shorter lifespan for the charge carriers, values for which should be below 0.5 μs. Due to this shorter lifespan, the current commutates faster, so that the MOSFET can absorb its reverse voltage earlier. This reduces the storage charge and the load on the switching-on MOSFET in a full or half-bridge configuration.
Die Dickendi ensionierung der eine aktive Schicht bildenden zusätzlichen Zonen ist optimal so gewählt, daß die Raumladungszone bei voller Sperrspannung den von der ersten Oberfläche des Halbleiterkörpers abgewandten (hinteren) n~/n+- Übergang zwischen der Innenzone und der Drainzone jedenfalls nicht erreicht. Als Beispiel sei hierfür eine Dicke von etwa unterhalb 10 μm für eine Sperrspannung von 400 V genannt.The thickness dimensioning of the additional zones forming an active layer is optimally selected such that the space charge zone does not reach the (rear) n ~ / n + transition between the inner zone and the drain zone facing away from the first surface of the semiconductor body at full reverse voltage. An example of this is a thickness of approximately below 10 μm for a reverse voltage of 400 V.
Da damit der Strom im wesentlichen innerhalb relativ hoch do- tierter Bahngebiete fließt, ist der Verlust an spezifischem Drain-Source-Widerstand sehr gering. Auch wird erreicht, daß die Speicherladung im "hinteren" Bereich des MOSFETs verbleibt. Diese Speicherladung wird durch Rekombination und Diffusion innerhalb von etwa 0,5 μs abgebaut, so daß ein "sanfter" Verlauf der Rückstromspitze, ein sog. "soft reco- very-Verhalten" erzielbar ist. Insbesondere kann auch der Abriß des Rückstromes, der sonst bei jedem MOSFET mit minimaler Dickenauslegung auftritt, vermieden werden. Überspannungen, die durch Streuinduktivitäten im Zweig zwischen kommutieren- dem und einschaltendem MOSFET bis hin zu einem Avalanche- durchbruch des kommutierenden Schalters auftreten, und die damit verbundenen Netzbelastungen werden so sicher verhindert .Since this means that the electricity essentially flows within relatively heavily doped railroad areas, the loss is more specific Drain-source resistance very low. It is also achieved that the storage charge remains in the "rear" region of the MOSFET. This storage charge is reduced by recombination and diffusion within about 0.5 μs, so that a "gentle" course of the return current peak, a so-called "soft recovery behavior" can be achieved. In particular, the breakdown of the reverse current, which otherwise occurs in any MOSFET with a minimal thickness design, can also be avoided. Overvoltages that occur due to leakage inductances in the branch between the commutating and switching-on MOSFET up to an avalanche breakdown of the commutating switch, and the associated network loads are thus reliably prevented.
Damit ist ein Einsatz des erfindungsgemäßen vertikalen Leistungs-MOSFET als Freilaufdiode möglich. Das heißt, eine entsprechende Ersatzbeschaltung mit einer eigenen Freilaufdiode ist im Gegensatz zum Stand der Technik nicht mehr erforderlich.This makes it possible to use the vertical power MOSFET according to the invention as a freewheeling diode. This means that, in contrast to the prior art, a corresponding equivalent circuit with its own free-wheeling diode is no longer required.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Figur 1 einen Schnitt durch den erfindungsgemäßen vertikalen Leistungs-MOSFET,FIG. 1 shows a section through the vertical power MOSFET according to the invention,
Figur 2 (a) bis (c) schematische Darstellungen zur Erläuterung der Herstellung des Leistungs-MOSFET undFigure 2 (a) to (c) are schematic representations to explain the manufacture of the power MOSFET and
Figur 3 einen Schnitt durch einen bestehenden vertikalen Leistungs-MOSFET.Figure 3 shows a section through an existing vertical power MOSFET.
Die Fig. 3 ist bereits eingangs ausführlich beschrieben worden. In der Fig. 1 werden für einander entsprechende Bauteile die gleichen Bezugszeichen wie in Fig. 3 verwendet, so daß von näheren Erläuterungen hierzu abgesehen werden kann.3 has already been described in detail at the beginning. In Fig. 1, the same reference numerals are used as in Fig. 3 for corresponding components, so that further explanations can be dispensed with.
Im Gegensatz zu dem bestehenden vertikalen MOSFET gemäßIn contrast to the existing vertical MOSFET
Fig. 3 sind bei dem erfindungsgemäßen vertikalen Leistungs- MOSFET die n-leitenden Zonen 11 durch Diffusion mit Platin, Gold usw. dotiert, um die Ladungsträger-Lebensdauer in diesen Zonen zu vermindern. Diese Verringerung der Ladungsträger- Lebensdauer kann auch durch Bestrahlung mit Elektronen oder Helium erreicht werden. Infolge der ursprünglich höheren Dotierung werden Auswirkungen auf den spezifischen Widerstand des MOSFETs als Folge der kompensierenden Wirkung der Verringerung der Ladungsträger-Lebensdauer verhindert.3, in the vertical power MOSFET according to the invention, the n-type zones 11 are doped by diffusion with platinum, gold, etc., in order to reduce the charge carrier life in these zones. This reduction in the lifetime of the charge carrier can also be achieved by irradiation with electrons or helium. As a result of the originally higher doping, effects on the specific resistance of the MOSFET as a result of the compensating effect of the reduction in the carrier lifetime are prevented.
Durch die geringere Ladungsträger-Lebensdauer wird ein rascheres Abkommutieren des Stromes erreicht, so daß der Leistungs-MOSFET früher seine Sperrspannung aufnehmen kann.Due to the shorter charge carrier life, the current is commutated more quickly, so that the power MOSFET can absorb its reverse voltage earlier.
Die Dickendimensionierung der zusätzlichen Zonen 11, 12 ist so gewählt, daß die Raumladungszone bei voller Sperrspannung den "hinteren" n+/n"-Übergang zwischen der Innenzone 1 und der Drainzone 7 keinesfalls erreicht und praktisch am Übergang zwischen den zusätzlichen Zonen 11, 12 und der Innenzone 1 endet.The thickness dimensioning of the additional zones 11, 12 is selected such that the space charge zone does not reach the "rear" n + / n " transition between the inner zone 1 and the drain zone 7 at full blocking voltage and practically at the transition between the additional zones 11, 12 and inner zone 1 ends.
Die maximale Ausdehnung der Raumladungszone ist in Fig. 1 durch eine Linie 15 angedeutet.The maximum extent of the space charge zone is indicated in FIG. 1 by a line 15.
Die in den Fig. 1 und 2 angegebenen Polaritäten können selbstverständlich vertauscht werden. So kann beispielsweise die Innenzone 1 p-dotiert sein, während die Zonen 11 n- dotiert und die Zonen 12 wie die Innenzone 1 p-dotiert sind. Außerdem ist es auch möglich, in einer p-leitenden Innenzone 1 nur eine n-leitende Zone 11 ("Säule") oder in einer n- leitenden Innenzone 1 nur eine p-leitende Zone 11 vorzusehen.The polarities indicated in FIGS. 1 and 2 can of course be interchanged. For example, the inner zone 1 can be p-doped, while the zones 11 are n-doped and the zones 12, like the inner zone 1, are p-doped. It is also possible in a p-type inner zone 1 to provide only one n-type zone 11 (“column”) or only one p-type zone 11 in an n-type inner zone 1.
Die Zonen 11, 12 können als "p-Säulen" für die Zonen 11 in einer n-Epitaxieschicht für die Zonen 12 (vgl. Fig. 2(c)) oder als "n-Säulen" für die Zonen 12 in einer p-Epitaxie- schicht für die Zonen 11 (vgl. Fig. 2(b)) hergestellt werden. Auch ist es möglich, die Zonen 11, 12 als "n-Säulen" und "p- Säulen" in eine n~- bzw. p~-Epitaxieschicht einzubringen (vgl. Fig. 2 (a) ) . Als besonders vorteilhaft hat sich die Variante der Fig. 2(c) erwiesen. The zones 11, 12 can be used as "p-pillars" for the zones 11 in an n-epitaxial layer for the zones 12 (see FIG. 2 (c)) or as "n-pillars" for the zones 12 in a p- Epitaxial layer for the zones 11 (see FIG. 2 (b)) can be produced. It is also possible to introduce the zones 11, 12 as "n-pillars" and "p-pillars" in an n ~ or p ~ epitaxial layer (see FIG. 2 (a)). The variant of FIG. 2 (c) has proven to be particularly advantageous.

Claims

Patentansprüche claims
1. Vertikaler Leistungs-MOSFET mit einem Halbleiterkörper mit einer Innenzone (1) vom ersten Leitungstyp und vorgegebener Dotierungskonzentration, mit mindestens einer an die Innenzone (1) und an eine erste Oberfläche des Halbleiterkörpers angrenzenden Basiszone (3) vom zweiten Leitungstyp, in die jeweils mindestens eine Sourcezone (4) eingebettet ist, mit mindestens einer an eine der Oberflächen des Halbleiterkör- pers angrenzenden Drainzone (7) mit in der Innenzone (1) im wesentlichen innerhalb der sich bei Sperrspannung aufspannenden Raumladungszone angeordneten zusätzlichen Zonen (11) des zweiten Leitungstyps, mit mindestens einer zwischen diesen zusätzlichen Zonen liegenden, höher als die Innenzone (1) do- tierten zusätzlichen Zone (12) vom ersten Leitungstyp und mit einer Dotierungshöhe der zusätzlichen Zonen (11, 12) und mit Abständen der zusätzlichen Zonen des zweiten Leitungstyps voneinander derart, daß ihre Ladungsträger bei angelegter Sperrspannung weitgehend ausgeräumt sind, d a d u r c h g e k e n n z e i c h n e t , daß die Ladungsträger-Lebensdauer mindestens in den zusätzlichen Zonen (12) vom ersten Leitungstyp vermindert ist und daß die Dickendimensionierung der zusätzlichen Zonen (11, 12) so gewählt ist, daß die sich bei Sperrspannung aufspannende Raumladungszone (vgl. 15) den von der ersten Oberfläche des1. Vertical power MOSFET with a semiconductor body with an inner zone (1) of the first conductivity type and a predetermined doping concentration, with at least one base zone (3) adjacent to the inner zone (1) and a first surface of the semiconductor body, in each case at least one source zone (4) is embedded, with at least one drain zone (7) adjoining one of the surfaces of the semiconductor body, with additional zones (11) of the second conductivity type arranged in the inner zone (1) essentially within the space charge zone spanning the blocking voltage , with at least one additional zone (12) of the first conductivity type doped between these additional zones, higher than the inner zone (1), and with a doping level of the additional zones (11, 12) and with distances between the additional zones of the second conductivity type such that their charge carriers largely when the reverse voltage is applied that the charge carrier life is reduced at least in the additional zones (12) of the first conduction type and that the thickness dimensioning of the additional zones (11, 12) is selected so that the space charge zone spanning at reverse voltage (cf. 15) that of the first surface of the
Halbleiterkörpers abgewandten Übergang zwischen den zusätzlichen Zonen (12) vom ersten Leitungstyp und der Innenzone (1) praktisch nicht überschreitet.Transition between the additional zones (12) of the first conductivity type and the inner zone (1) facing away from the semiconductor body practically does not exceed.
2. Vertikaler Leistungs-MOSFET nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß die Ladungsträger-Lebensdauer durch Diffusion von Platin und/oder Gold oder durch Bestrahlung mit Elektronen und/oder Helium herabgesetzt ist. 2. Vertical power MOSFET according to claim 1, characterized in that the charge carrier life is reduced by diffusion of platinum and / or gold or by irradiation with electrons and / or helium.
3. Vertikaler Leistungs-MOSFET nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die Ladungsträger-Lebensdauer auf Werte unterhalb 0,5 μs eingestellt ist.3. Vertical power MOSFET according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the charge carrier life is set to values below 0.5 μs.
4. Vertikaler Leistungs-MOSFET nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die Dicke der zusätzlichen Zonen (11, 12) in Dickenrichtung des vertikalen MOSFETs für eine Sperrspannung von 400 V etwa unterhalb 10 μm beträgt.4. Vertical power MOSFET according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the thickness of the additional zones (11, 12) in the thickness direction of the vertical MOSFET for a reverse voltage of 400 V is approximately below 10 microns.
5. Vertikaler Leistungs-MOSFET nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , daß eine der zusätzlichen Zonen (11, 12) als p-Säule bzw. als n-Säule in eine n- bzw. p-Epitaxieschicht eingebracht ist.5. Vertical power MOSFET according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that one of the additional zones (11, 12) is introduced as a p-pillar or as an n-pillar in an n- or p-epitaxial layer.
6. Vertikaler Leistungs-MOSFET nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t , daß die zusätzlichen Zonen (11, 12) als p- bzw. n-Säulen in eine n"- oder p"-Epitaxieschicht eingebracht sind. 6. Vertical power MOSFET according to one of claims 1 to 4, characterized in that the additional zones (11, 12) are introduced as p- or n-pillars in an n " - or p " epitaxial layer.
EP98947303A 1997-07-17 1998-07-17 Vertical power mosfet Withdrawn EP0929910A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19730759 1997-07-17
DE19730759A DE19730759C1 (en) 1997-07-17 1997-07-17 Vertical power MOSFET
PCT/DE1998/002020 WO1999004437A1 (en) 1997-07-17 1998-07-17 Vertical power mosfet

Publications (1)

Publication Number Publication Date
EP0929910A1 true EP0929910A1 (en) 1999-07-21

Family

ID=7836066

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98947303A Withdrawn EP0929910A1 (en) 1997-07-17 1998-07-17 Vertical power mosfet

Country Status (5)

Country Link
US (1) US6479876B1 (en)
EP (1) EP0929910A1 (en)
JP (1) JP4116098B2 (en)
DE (1) DE19730759C1 (en)
WO (1) WO1999004437A1 (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19840032C1 (en) 1998-09-02 1999-11-18 Siemens Ag Semiconductor device for compensation element
JP4169879B2 (en) * 1999-08-20 2008-10-22 新電元工業株式会社 High voltage transistor
JP3804375B2 (en) 1999-12-09 2006-08-02 株式会社日立製作所 Semiconductor device and power switching drive system using the same
JP2001210823A (en) * 2000-01-21 2001-08-03 Denso Corp Semiconductor device
DE10048345A1 (en) * 2000-09-29 2002-05-16 Eupec Gmbh & Co Kg Bodies made of semiconductor material with a reduced mean free path
DE10052004C1 (en) * 2000-10-20 2002-02-28 Infineon Technologies Ag Vertical field effect transistor has semiconductor layer incorporating terminal zones contacted at surface of semiconductor body provided with compensation zones of opposite type
JP3899231B2 (en) * 2000-12-18 2007-03-28 株式会社豊田中央研究所 Semiconductor device
EP1267415A3 (en) 2001-06-11 2009-04-15 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
JP3973395B2 (en) * 2001-10-16 2007-09-12 株式会社豊田中央研究所 Semiconductor device and manufacturing method thereof
US6825514B2 (en) 2001-11-09 2004-11-30 Infineon Technologies Ag High-voltage semiconductor component
US6819089B2 (en) 2001-11-09 2004-11-16 Infineon Technologies Ag Power factor correction circuit with high-voltage semiconductor component
GB0225812D0 (en) * 2002-11-06 2002-12-11 Koninkl Philips Electronics Nv Semiconductor devices and methods of manufacturing thereof
JP3634848B2 (en) 2003-01-07 2005-03-30 株式会社東芝 Power semiconductor device
DE10361136B4 (en) * 2003-12-23 2005-10-27 Infineon Technologies Ag Semiconductor diode and IGBT
JP4844371B2 (en) * 2006-12-04 2011-12-28 富士電機株式会社 Vertical superjunction semiconductor device
DE102007019551B9 (en) * 2007-04-25 2012-10-04 Infineon Technologies Austria Ag Semiconductor device and method of making the same
WO2010024433A1 (en) * 2008-09-01 2010-03-04 ローム株式会社 Semiconductor device and manufacturing method thereof
CN103383954A (en) * 2012-05-03 2013-11-06 朱江 Passive super-junction semiconductor device and manufacturing method for same
US9287371B2 (en) 2012-10-05 2016-03-15 Semiconductor Components Industries, Llc Semiconductor device having localized charge balance structure and method
US9219138B2 (en) 2012-10-05 2015-12-22 Semiconductor Components Industries, Llc Semiconductor device having localized charge balance structure and method
US9583578B2 (en) * 2013-01-31 2017-02-28 Infineon Technologies Ag Semiconductor device including an edge area and method of manufacturing a semiconductor device
US9306034B2 (en) * 2014-02-24 2016-04-05 Vanguard International Semiconductor Corporation Method and apparatus for power device with multiple doped regions
US9825128B2 (en) 2015-10-20 2017-11-21 Maxpower Semiconductor, Inc. Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings
US9768247B1 (en) 2016-05-06 2017-09-19 Semiconductor Components Industries, Llc Semiconductor device having improved superjunction trench structure and method of manufacture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3131914A1 (en) * 1981-08-12 1983-02-24 Siemens AG, 1000 Berlin und 8000 München POWER MOS FIELD EFFECT TRANSISTOR AND METHOD FOR PRODUCING THE SAME
CH668505A5 (en) * 1985-03-20 1988-12-30 Bbc Brown Boveri & Cie SEMICONDUCTOR COMPONENT.
IT1247293B (en) 1990-05-09 1994-12-12 Int Rectifier Corp POWER TRANSISTOR DEVICE PRESENTING AN ULTRA-DEEP REGION, AT A GREATER CONCENTRATION
CN1019720B (en) 1991-03-19 1992-12-30 电子科技大学 Power semiconductor device
DE4309764C2 (en) * 1993-03-25 1997-01-30 Siemens Ag Power MOSFET
DE69320033T2 (en) * 1993-06-10 1998-12-03 Cons Ric Microelettronica Monolithically integrated structure of a vertical bipolar and a vertical MOSFET transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9904437A1 *

Also Published As

Publication number Publication date
WO1999004437A1 (en) 1999-01-28
JP2001501042A (en) 2001-01-23
JP4116098B2 (en) 2008-07-09
DE19730759C1 (en) 1998-09-03
US6479876B1 (en) 2002-11-12

Similar Documents

Publication Publication Date Title
DE19730759C1 (en) Vertical power MOSFET
DE10259373B4 (en) Overcurrent Schottky diode with low reverse current
DE19811297B4 (en) High breakdown voltage MOS semiconductor device
EP0200863B1 (en) Semiconductor device with structures of thyristors and diodes
DE10250575B4 (en) IGBT with monolithically integrated antiparallel diode
EP0987766A1 (en) Edge structure for a field-effect transistor having a plurality of cells
DE19528998C2 (en) Bi-directional semiconductor switch and method for its control
EP0913000B1 (en) Field effect controllable semiconductor component
DE3631136C2 (en)
EP1097482B1 (en) J-fet semiconductor device
DE3131914A1 (en) POWER MOS FIELD EFFECT TRANSISTOR AND METHOD FOR PRODUCING THE SAME
EP1092238A1 (en) Universal semiconductor wafer for high-voltage semiconductor components
EP1116276B1 (en) Semiconductor component with field-forming regions
DE10360574B4 (en) Power semiconductor component with gentle turn-off behavior
EP0709899A2 (en) Semiconductor diode with electron injector
DE10245089A1 (en) Doping process used in the production of a transistor, IGBT, thyristor or diode comprises preparing a semiconductor body, producing crystal defects in the body, introducing hydrogen ions into the body, and heat treating
DE102005029263A1 (en) Semiconductor element has body with pn junction edge connections and doped semiconductor islands in field isolation
WO1991010265A1 (en) Field-effect-controlled semiconductor component
DE4240027A1 (en) MOS controlled diode
DE10223951A1 (en) High-voltage diode with optimized switch-off process and corresponding optimization process
EP0559945A1 (en) Turn-off power semi-conductor device
DE10126309A1 (en) Power semiconductor component for reverse blocking has a semiconductor body forming a drift track for a mode of conductivity, a body zone for another mode of conductivity and a source zone for one mode of conductivity.
DE10321222A1 (en) Semiconductor elements such as a mosfet jfet or schottky diode have electrodes with intermediate drift zone and embedded oppositely doped regions
DE10326739B3 (en) Semiconductor component with metal semiconductor junction has Schottky-metal contact bordering on drift zone and compensation zone
DE10038150B4 (en) By field effect controllable semiconductor element with integrated Schottky diode

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19990305

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IE IT

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

17Q First examination report despatched

Effective date: 20070717

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20071128