CN103383954A - Passive super-junction semiconductor device and manufacturing method for same - Google Patents
Passive super-junction semiconductor device and manufacturing method for same Download PDFInfo
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- CN103383954A CN103383954A CN2012101483274A CN201210148327A CN103383954A CN 103383954 A CN103383954 A CN 103383954A CN 2012101483274 A CN2012101483274 A CN 2012101483274A CN 201210148327 A CN201210148327 A CN 201210148327A CN 103383954 A CN103383954 A CN 103383954A
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Abstract
The invention discloses a passive super-junction semiconductor device. A super-junction structure is formed through second strip-shaped passive conductive semiconductor materials and first strip-shaped passive conductive semiconductor materials, the reverse breakdown voltage of the device is improved, or the forward conduction performance of the device is improved. The invention further provides a manufacturing method for the passive super-junction semiconductor device.
Description
Technical field
The present invention relates to a kind of passive super pn junction p n device, the invention still further relates to a kind of preparation method of passive super pn junction p n device.Semiconductor device of the present invention is the basic structure of making power rectifier device.
Background technology
Power semiconductor is used on power management and application of power in a large number, and the semiconductor device that specially refers to super knot has become the important trend of device development.
In traditional super junction device, super-junction structure and device surface active structure need to be carried out interconnectedly, have comparatively complicated manufacturing process; Have in addition floating empty semi-conducting material island is distributed in drift, but its charge compensation effect under reverse biased is not remarkable.
Summary of the invention
The present invention is directed to the problems referred to above and propose, a kind of passive super pn junction p n device and preparation method thereof is provided.
A kind of passive super pn junction p n device is characterized in that: comprising: substrate layer, for semi-conducting material consists of; Drift layer is the first conductive semiconductor material, is positioned on substrate layer; Passive the second conductive semiconductor material sections, for strip the second conductive semiconductor material, be arranged in drift layer, perpendicular to substrate layer, consist of with the first conductive semiconductor materials arranged in alternating, and passive the second conductive semiconductor material sections upper surface faces by insulating material or the first conductive semiconductor material; Active the second conductive semiconductor material sections is positioned at the drift layer upper surface, is the second conductive semiconductor material, and is not connected with passive the second conductive semiconductor material sections.
A kind of preparation method of passive super pn junction p n device semiconductor device is characterized in that: comprise the steps: that then the surface forms a kind of dielectric at substrate layer surface formation the first conductive semiconductor material layer; Carry out lithography corrosion process and remove the surface portion dielectric, then etching is removed part bare semiconductor material and is formed groove; Form the second conductive semiconductor material in groove, carry out surfacing; Form the first conductive semiconductor material layer at semiconductor material surface; Then implanted dopant carries out annealing process.
When semiconductor device connect certain reverse biased, the first conductive semiconductor material and passive the second conductive semiconductor material sections can form charge compensation, formed super-junction structure, improved the reverse breakdown voltage of device.
Since the existence of super-junction structures, thus the impurity doping content of drift region can be improved, also can reduce the forward conduction resistance of device, improve the forward conduction characteristic of device.
The present invention also provides a kind of preparation method of passive super pn junction p n device.
Description of drawings
Fig. 1 is a kind of passive super pn junction p n device generalized section of the present invention;
Fig. 2 is the passive super pn junction p n device generalized section of the second of the present invention.
Wherein,
1, substrate layer;
2, silicon dioxide
3, the first conductive semiconductor material;
4, passive the second conductive semiconductor material;
5, active the second conductive semiconductor material;
8, super-junction structure.
Embodiment
Fig. 1 is a kind of passive super pn junction p n device profile of the present invention, describes semiconductor device of the present invention in detail below in conjunction with Fig. 1.
A kind of passive super pn junction p n device comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the doping content of phosphorus atoms is 1E19/CM
3The first conductive semiconductor material 3 is positioned on substrate layer 1, is the semiconductor silicon material of N conduction type, and the doping content of phosphorus atoms is 1E16/CM
3Passive the second conductive semiconductor material 4 is arranged in the first conductive semiconductor material 3, is the semiconductor silicon material of P conduction type, and the doping content of boron atom is 1E16/CM
3Active the second conductive semiconductor material 5 is positioned at the surface of the first conductive semiconductor material 3, is semiconductor silicon material, and the doping content of boron atom is 1E18/CM
3
Its manufacture craft comprises the steps:
The first step, at substrate layer 1 surface formation the first conductive semiconductor material layer 3, then surface heat oxidation forms silicon dioxide 2;
Second step carries out lithography corrosion process, and semiconductor material surface is removed part silicon dioxide 2, and then etching is removed part bare semiconductor silicon materials and formed groove;
The 3rd step formed passive the second conductive semiconductor material 4 in groove, carry out the surfacing metallization processes;
The 4th step, deposit one deck the first conductive semiconductor material layer 3;
In the 5th step, then B Implanted impurity carry out annealing process, as shown in Figure 1.
Fig. 2 is a kind of passive super pn junction p n device profile of the present invention, describes semiconductor device of the present invention in detail below in conjunction with Fig. 2.
A kind of passive super pn junction p n device comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the doping content of phosphorus atoms is 1E19/CM
3The first conductive semiconductor material 3 is positioned on substrate layer 1, is the semiconductor silicon material of N conduction type, and the doping content of phosphorus atoms is 1E16/CM
3Passive the second conductive semiconductor material 4 is arranged in the first conductive semiconductor material 3, is the semiconductor silicon material of P conduction type, and the doping content of boron atom is 1E16/CM
3Silicon dioxide 2 is positioned on passive the second conductive semiconductor material 4; Active the second conductive semiconductor material 5 is positioned at the surface of the first conductive semiconductor material 3, is semiconductor silicon material, and the doping content of boron atom is 1E18/CM
3
Its manufacture craft comprises the steps:
The first step, at substrate layer 1 surface formation the first conductive semiconductor material layer 3, then surface heat oxidation forms silicon dioxide 2;
Second step carries out lithography corrosion process, and semiconductor material surface is removed part silicon dioxide 2, and then etching is removed part bare semiconductor silicon materials and formed groove;
The 3rd step formed passive the second conductive semiconductor material 4 in groove, anti-carve erosion;
In the 4th step, deposit silicon dioxide 2 anti-carves erosion;
In the 5th step, then B Implanted impurity carry out annealing process, as shown in Figure 2.
Set forth the present invention by above-mentioned example, also can adopt other example to realize the present invention simultaneously, the present invention is not limited to above-mentioned instantiation, so the present invention is by the claims circumscription.
Claims (10)
1. passive super pn junction p n device is characterized in that: comprising:
Substrate layer is for semi-conducting material consists of;
Drift layer is the first conductive semiconductor material, is positioned on substrate layer;
Passive the second conductive semiconductor material sections, for strip the second conductive semiconductor material, be arranged in drift layer, perpendicular to substrate layer, consist of with the first conductive semiconductor materials arranged in alternating, and passive the second conductive semiconductor material sections upper surface faces by insulating material or the first conductive semiconductor material;
Active the second conductive semiconductor material sections is positioned at the drift layer upper surface, is the second conductive semiconductor material, and is not connected with passive the second conductive semiconductor material sections.
2. semiconductor device as claimed in claim 1 is characterized in that: described substrate layer is the semi-conducting material of high concentration impurities doping.
3. semiconductor device as claimed in claim 1, it is characterized in that: the height of described passive the second conductive semiconductor material sections is more than or equal to 1/2nd of drift layer thickness.
4. semiconductor device as claimed in claim 1, it is characterized in that: the first conductive semiconductor material of described passive the second conductive semiconductor material sections and drift layer can form charge compensation when connecing reverse biased.
5. semiconductor device as claimed in claim 1, it is characterized in that: the vertical view of described passive the second conductive semiconductor material sections can be polygonized structure, honeycomb or list structure.
6. semiconductor device as claimed in claim 1, it is characterized in that: described insulating material can be silicon dioxide.
7. semiconductor device as claimed in claim 1 is characterized in that: described insulating material can be positioned at the semiconductor device surface.
8. semiconductor device as claimed in claim 1, it is characterized in that: described active the second conductive semiconductor material sections is the high concentration impurities doped region.
9. semiconductor device as claimed in claim 1 is characterized in that: be connected by the first conductive semiconductor material between described active the second conductive semiconductor material sections and passive the second conductive semiconductor material sections.
10. the preparation method of a kind of passive super pn junction p n device as claimed in claim 1, is characterized in that: comprise the steps:
1) at substrate layer surface formation the first conductive semiconductor material layer, then the surface forms a kind of dielectric;
2) carry out lithography corrosion process and remove the surface portion dielectric, then etching is removed part bare semiconductor material and is formed groove;
3) form the second conductive semiconductor material in groove, carry out surfacing;
4) form the first conductive semiconductor material layer at semiconductor material surface;
5) then implanted dopant carries out annealing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101483274A CN103383954A (en) | 2012-05-03 | 2012-05-03 | Passive super-junction semiconductor device and manufacturing method for same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2012101483274A CN103383954A (en) | 2012-05-03 | 2012-05-03 | Passive super-junction semiconductor device and manufacturing method for same |
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| CN103383954A true CN103383954A (en) | 2013-11-06 |
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| CN2012101483274A Pending CN103383954A (en) | 2012-05-03 | 2012-05-03 | Passive super-junction semiconductor device and manufacturing method for same |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4309764A1 (en) * | 1993-03-25 | 1994-09-29 | Siemens Ag | Power MOSFET |
| US6479876B1 (en) * | 1997-07-17 | 2002-11-12 | Gerald Deboy | Vertical power MOSFET |
| JP2003523087A (en) * | 2000-02-12 | 2003-07-29 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Semiconductor device with voltage divider for increasing reverse blocking voltage |
-
2012
- 2012-05-03 CN CN2012101483274A patent/CN103383954A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4309764A1 (en) * | 1993-03-25 | 1994-09-29 | Siemens Ag | Power MOSFET |
| US6479876B1 (en) * | 1997-07-17 | 2002-11-12 | Gerald Deboy | Vertical power MOSFET |
| JP2003523087A (en) * | 2000-02-12 | 2003-07-29 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Semiconductor device with voltage divider for increasing reverse blocking voltage |
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Application publication date: 20131106 |