EP1092238A1 - Universal semiconductor wafer for high-voltage semiconductor components - Google Patents

Universal semiconductor wafer for high-voltage semiconductor components

Info

Publication number
EP1092238A1
EP1092238A1 EP99915461A EP99915461A EP1092238A1 EP 1092238 A1 EP1092238 A1 EP 1092238A1 EP 99915461 A EP99915461 A EP 99915461A EP 99915461 A EP99915461 A EP 99915461A EP 1092238 A1 EP1092238 A1 EP 1092238A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
layer
universal
semiconductor wafer
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99915461A
Other languages
German (de)
French (fr)
Inventor
Jenö Tihanyi
Reinhard Ploss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1092238A1 publication Critical patent/EP1092238A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/6634—Vertical insulated gate bipolar transistors with a recess formed by etching in the source/emitter contact region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/261—Bombardment with radiation to produce a nuclear reaction transmuting chemical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a universal semiconductor wafer for high-voltage semiconductor components, in which at least one layer of the one conductivity type is provided on a semiconductor substrate of the one conductivity type.
  • a universal semiconductor wafer should be usable as the basic material for all of these components. So far, however, it has been necessary to optimize the respective base disks for the individual different high-voltage semiconductor components in accordance with the required voltage classes of the individual semiconductor components, for example by appropriate doping of the epitaxial layer and the wafer thickness.
  • IGBTs Current-switching semiconductor components for high voltages, such as IGBTs, are more sensitive to interference when the inductive loads are to be switched, the higher the blocking or blocking voltage. It is known, for example, that high-voltage IGBTs are particularly at risk of operational reliability due to high radiation. To eliminate this susceptibility to interference, it could be considered to dope the blocking region in the semiconductor wafer low, so that high voltages can be blocked. However, there are limits to such a procedure: if current flows when the voltage is high, the charge carriers are the ones that match the blocking area or the blocking distance at a speed of the order of about 10 7 cm / s. 2 Sieren, even at low current densities in extremely high con ⁇ concentration present.
  • This object is achieved according to the invention in a universal semiconductor wafer of the type mentioned at the outset in that a large number of floating semiconductor regions of the other conductivity type are embedded in the interfaces between the semiconductor substrate and layers and are dimensioned such that the dimension of a floating region is small compared to the layer thickness is the layer and essentially corresponds to or is less than the distance between the conductive regions in an interface.
  • the individual layers can be epitaxial layers or applied by direct wafer bonding.
  • the floating semiconductor regions are preferably introduced into the surface of the arrangement in question by diffusion or ion implantation or implantation and subsequent diffusion before the next layer is applied to it - be it by epitaxy or by direct wafer bonding.
  • the individual layers can preferably also be applied undoped and only subsequently doped by neutron transmutation.
  • the semiconductor regions which may also be interconnected like a grid, are preferably arranged in a plurality of planes which are essentially parallel to one another. These levels are easily created when the individual epitaxial layers are deposited or when these layers are applied by direct wafer bonding.
  • a semiconductor component using such a universal semiconductor wafer for example an IGBT, in which a positive voltage is applied between the gate and source, is switched on, a space charge zone first arises in the uppermost semiconductor layer adjacent to the gate or source. If this space charge zone reaches the floating semiconductor regions that delimit this uppermost semiconductor layer to the next semiconductor layer, then the voltage at these regions remains at the value V pt h then reached, which corresponds to the situation of a “punch-through”.
  • One line type is preferably the n line type, so that the other line type is given by the p line type and the floating semiconductor regions are thus p-type. 4 are. Of course, doping with reversed line types is also possible.
  • the highly doped semiconductor layer of one conductivity type that is to say preferably an n + -conducting buffer layer
  • another layer for example by a so-called “non-punch-through” structure.
  • the semiconductor regions are doped so that the space charge zones completely fill the individual semiconductor layers when a voltage is applied before a breakdown occurs.
  • the doping of the semiconductor regions is so high that they are not completely cleared out. This preferably applies to the central region of the semiconductor component, but not to the edge regions: there the doping of the semiconductor regions can be so low that they are removed when the voltage is applied.
  • the universal semiconductor wafer according to the invention is particularly advantageously suitable for the production of diodes, MOSFETs with field plate edges or IGBTs or GTOs with planar edge structures or for other semiconductor components, such as, for example, "non-punch-through-IGBTs" with a thinly ground back .
  • Fig. 1 is a sectional view through an inventive
  • FIG. 3 shows a sectional view through an IGBT with the universal semiconductor wafer according to the invention.
  • Fig. 4 is a sectional view through a modified
  • FIGS. 1 to 4 show sectional images, hatching is partially omitted there to simplify the illustration. Components that correspond to one another are also provided with the same reference symbols in the figures.
  • n-conducting substrate 4 with a doping concentration n 0 an n-conducting epitaxial layer 5 with a doping concentration ni, a second n-conducting layer epitaxial layer 6 with a doping concentration n 2 and a third n-conducting epitaxial layer 7 with a doping concentration n 3 are provided.
  • n-conducting epitaxial layer 5 with a doping concentration ni a second n-conducting layer epitaxial layer 6 with a doping concentration n 2
  • a third n-conducting epitaxial layer 7 with a doping concentration n 3 are provided.
  • the epitaxial layers 5, 6 and 7 corresponding layers can also be provided by direct wafer bonding.
  • the doping concentrations in the lithium substrate 4 and the epitaxial layers 5, 6 and 7 can also be identical to one another.
  • the epitaxial layers 5, 6 and 7 can be deposited undoped and subsequently doped by neutron transmutation.
  • These areas 8 are introduced by diffusion or ion implantation before the subsequent layer 5 or 6 or 7 is applied.
  • regions 8 of the lowest level in FIG. 1 are introduced into the surface of substrate 4 by diffusion or ion implantation before layer 5 is deposited epitaxially.
  • the regions 8 of the “middle” plane are introduced by diffusion or ion implantation.
  • the regions 8 of the top level are introduced before the layer 7 is subsequently deposited epitaxially.
  • Lifetime killers such as platinum and / or gold, can be implanted or otherwise introduced between the individual epitaxial layers in their interfaces.
  • the individual regions 8 "float", even if, as has already been mentioned, they can be connected at least partially or entirely in one plane.
  • the distance d between the individual areas 8 of a plane corresponds approximately to the diameter b of these areas or is somewhat larger than this.
  • the distance d between the individual areas 8 of a level is smaller than the distance Di, D 2 between the individual levels.
  • the universal semiconductor wafer according to the invention is advantageously suitable for diodes, MOSFETs with field plate edges, IGBTs, GTOs with planar edge structures or other semiconductor components, such as, for example, “non-punch-through IGBTs” with a thinly ground rear side 3. 7
  • FIG. 2 An example of a diode with aluminum electrodes 9, 10, a p-type zone 11, a field plate 12 and an insulating layer 13 made of silicon dioxide is shown in FIG. 2.
  • the doping concentration in the regions 8 in the region of the edge 14 of this diode is somewhat weaker than the doping concentration in the regions 8 in the central region of the diode, that is to say essentially in FIG. 2 below the zone 11.
  • the regions 8 in the central region are doped so highly that they are not completely cleared of charge carriers when a voltage is applied between the electrodes 9, 10. This does not apply to the area near the edge 14, where the regions 8 are only so heavily doped that they are actually cleared out when this voltage is applied.
  • a voltage + U is present at the electrode 9, for example, while the electrode 10 can be grounded.
  • the field plate 12 like the doping of the regions 8 which becomes weaker in the region of the edge 14, serves to prevent a breakdown in the region of the edge 14 of the diode.
  • Figs. 3 and 4 respectively show a sectional view of an IGBT with the inventive Universal wafer 1.
  • This universal semiconductor wafer 1 has, in addition, an n + - type layer 16 and a p + -type layer 17, on which a drain contact 15 for a drain connection D with a voltage + U D is plotted.
  • a source metalization 18, which is grounded gate electrodes 19 made of polycrystalline silicon, which are connected to one another and to which a gate voltage U G is applied, a field plate 20 made of polycrystalline silicon, which is connected to the source metalization 18, and a channel or channel stopper 21 made of polycrystalline silicon, which is electrically connected to the layer 7.
  • the gate electrodes 19, the field plate 20 and the channel stopper 21 are in an insulating layer 22 made of, for example, silicon dioxide and / or silicon nitride 8 embedded, which also forms the gate oxide below the gate electrodes 19.
  • an insulating layer 22 made of, for example, silicon dioxide and / or silicon nitride 8 embedded, which also forms the gate oxide below the gate electrodes 19.
  • n + -conducting areas 23 and p -conducting areas 24 which together form source zones which are in contact with the source metallization 18.
  • a space charge zone When the IGBT is switched on, i.e. when a voltage + U Gs is applied between gate electrodes 19 and source metallization 18, a space charge zone first forms in the top layer 7. If this space charge zone is the top level of the p-type semiconductor regions 8 between layers 6 and 7 in one When the voltage value V pth is reached, the voltage of these semiconductor regions 8 remains at the voltage value V pth , the situation of a "punch-through" occurring. With a further increase in the drain voltage U D , the space charge zone forms in the layer 6 and finally reaches the semiconductor regions between the layers 5 and 6. This continues until the space charge zone finally arrives at the n + -conducting layer 16. This achieves four times the dielectric strength of a structure that could be achieved with n-doping alone without the p-doped regions 8. The dielectric strength can be further increased by additional levels with semiconductor regions 8.
  • the p + -doped semiconductor layer 17 and the source zones 23, 24, other layers can also be provided in order to form a GTO, a MOSFET or other semiconductor components.
  • the weakening doping of the semiconductor regions 8 in the region of the edge 14 can also be achieved by additionally assigning n + -doped semiconductor regions 25 to the p + -doped semiconductor regions 8, as is shown in the exemplary embodiment in FIG. 4.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Thyristors (AREA)

Abstract

The invention relates to a universal semiconductor wafer for high-voltage semiconductor components in which at least one layer (5, 6, 7) of a first conduction type is provided on a semiconductor substrate (4) of a first conduction type. A plurality of floating semiconductor regions (8) of the other conduction type are embedded in the boundary surfaces between the semiconductor substrate (4) and the at least one layer. These semiconductor regions are measured such that the measurement of a semiconductor region (8) is smaller compared to the layer thickness of the semiconductor layer (5, 6, 7) and is essentially equal to or less than the distance between the floating semiconductor regions (8) in a boundary surface.

Description

1 1
Beschreibungdescription
Universal-Halbleiterscheibe für Hochvolt- HalbleiterbauelementeUniversal semiconductor wafer for high-voltage semiconductor components
Die vorliegende Erfindung betrifft eine Universal-Halbleiterscheibe für Hochvolt-Halbleiterbauelemente, bei der auf einem Halbleitersubstrat des einen Leitungstyps mindestens eine Schicht des einen Leitungstyps vorgesehen ist.The present invention relates to a universal semiconductor wafer for high-voltage semiconductor components, in which at least one layer of the one conductivity type is provided on a semiconductor substrate of the one conductivity type.
Um Hochvolt-Halbleiterbauelemente, wie beispielsweise Dioden, IGBT's (Bipolartransistoren mit isoliertem Gate), MOSFET's oder GTO's (Gate-Abschaltthyristoren) , mit möglichst wenig Aufwand herstellen zu können, sollte eine Universal-Halbleiterscheibe als Grundmaterial für alle diese Bauelemente einsetzbar sein. Bisher ist es aber erforderlich, für die einzelnen verschiedenen Hochvolt-Halbleiterbauelemente die jeweiligen Grundscheiben entsprechend den geforderten Spannungsklassen der einzelnen Halbleiterbauelemente beispielsweise durch entsprechende Dotierung der epitaktischen Schicht und der Scheibendicke zu optimieren.In order to be able to manufacture high-voltage semiconductor components such as diodes, IGBTs (bipolar transistors with insulated gate), MOSFETs or GTOs (gate switch-off thyristors) with as little effort as possible, a universal semiconductor wafer should be usable as the basic material for all of these components. So far, however, it has been necessary to optimize the respective base disks for the individual different high-voltage semiconductor components in accordance with the required voltage classes of the individual semiconductor components, for example by appropriate doping of the epitaxial layer and the wafer thickness.
Stromschaltende Halbleiterbauelemente für hohe Spannungen, wie beispielsweise IGBT's, sind, wenn speziell induktive Lasten zu schalten sind, für Störungen um so empfindlicher, je höher die Sperr- bzw. Blockierspannung ist. So weiß man, daß beispielsweise Hochvolt-IGBT' s durch Höhenstrahlung in ihrer Betriebszuverlässigkeit besonders gefährdet sind. Zur Beseitigung dieser Störanfälligkeit könnte daran gedacht werden, den Sperrbereich in der Halbleiterscheibe niedrig zu dotieren, damit hohe Spannungen gesperrt werden können. Einem derartigen Vorgehen sind aber Grenzen gesetzt: fließt nämlich bei hoher anliegender Spannung Strom, sind die Ladungsträger, die mit einer Grenzgeschwindigkeit in der Größenordnung von etwa 107 cm/s den Sperrbereich bzw. die Blockierstrecke pas- 2 sieren, bereits bei kleinen Stromdichten in extrem hoher Kon¬ zentration vorhanden. Diese hohe Konzentration kommt dann der Dotierung nahe, so daß eine Verzerrung des elektrischen Feldes eintritt, was zu einer Zerstörung des Halbleiterbauelementes führen kann, wenn der geschaltete Strom höhere Werte annimmt. Bisher halten nur Thyristoren hohe Ströme bei hoher Sperrspannung aus. Diese müssen aber bei einer kleinen anliegenden Spannung bzw. einer Spannungsumkehrung abgeschaltet werden und können daher nicht als "echte" Schalter betrachtet werden.Current-switching semiconductor components for high voltages, such as IGBTs, are more sensitive to interference when the inductive loads are to be switched, the higher the blocking or blocking voltage. It is known, for example, that high-voltage IGBTs are particularly at risk of operational reliability due to high radiation. To eliminate this susceptibility to interference, it could be considered to dope the blocking region in the semiconductor wafer low, so that high voltages can be blocked. However, there are limits to such a procedure: if current flows when the voltage is high, the charge carriers are the ones that match the blocking area or the blocking distance at a speed of the order of about 10 7 cm / s. 2 Sieren, even at low current densities in extremely high con ¬ concentration present. This high concentration then comes close to the doping, so that a distortion of the electric field occurs, which can lead to destruction of the semiconductor component if the switched current assumes higher values. So far, only thyristors can withstand high currents with high reverse voltage. However, these must be switched off when there is a small voltage or a voltage reversal and can therefore not be considered as "real" switches.
Es ist daher Aufgabe der vorliegenden Erfindung, eine Universal-Halbleiterscheibe für Hochvolt-Halbleiterbauelemente zu schaffen, die vielseitig einsetzbar ist und sich speziell für Hochvolt-Stromschalter eignet, die gegenüber Höhenstrahlung weitgehend unempfindlich sind.It is therefore an object of the present invention to provide a universal semiconductor wafer for high-voltage semiconductor components which can be used in a variety of ways and is particularly suitable for high-voltage current switches which are largely insensitive to high-level radiation.
Diese Aufgabe wird bei einer Universal-Halbleiterscheibe der eingangs genannten Art erfindungsgemäß dadurch gelöst, daß in die Grenzflächen zwischen Halbleitersubstrat und Schichten eine Vielzahl von floatenden Halbleitergebieten des anderen Leitungstyps eingebettet sind, die so bemessen sind, daß die Abmessung eines floatenden Gebiets klein gegenüber der Schichtdicke der Schicht ist und im wesentlichen dem Abstand zwischen den leitenden Gebieten in einer Grenzfläche entspricht oder kleiner als dieser ist.This object is achieved according to the invention in a universal semiconductor wafer of the type mentioned at the outset in that a large number of floating semiconductor regions of the other conductivity type are embedded in the interfaces between the semiconductor substrate and layers and are dimensioned such that the dimension of a floating region is small compared to the layer thickness is the layer and essentially corresponds to or is less than the distance between the conductive regions in an interface.
Die einzelnen Schichten können dabei epitaktische Schichten sein oder durch Direkt-Waferbonding aufgetragen sein. Die floatenden Halbleitergebiete sind in bevorzugter Weise durch Diffusion oder Ionenimplantation oder Implantation und nachfolgende Diffusion in die Oberfläche der gerade vorliegenden Anordnung eingebracht, bevor auf diese die nächste Schicht - sei es durch Epitaxie oder durch Direkt-Waferbondung - aufgetragen wird. Weiterhin können vorzugsweise die einzelnen Schichten auch undotiert aufgetragen und erst nachträglich durch Neutronentransmutation dotiert werden.The individual layers can be epitaxial layers or applied by direct wafer bonding. The floating semiconductor regions are preferably introduced into the surface of the arrangement in question by diffusion or ion implantation or implantation and subsequent diffusion before the next layer is applied to it - be it by epitaxy or by direct wafer bonding. Furthermore, the individual layers can preferably also be applied undoped and only subsequently doped by neutron transmutation.
Die Halbleitergebiete, die gegebenenfalls auch gitterartig zusammenhängen können, sind vorzugsweise in mehreren, im wesentlichen zueinander parallelen Ebenen angeordnet. Diese Ebenen entstehen ohne weiteres bei der Abscheidung der einzelnen epitaktischen Schichten bzw. beim Auftragen dieser Schichten durch Direkt-Waferbonding. Beim Einschalten eines eine solche Universal-Halbleiterscheibe verwendenden Halbleiterbauelementes, beispielsweise eines IGBT's, bei dem eine positive Spannung zwischen Gate und Source gelegt wird, entsteht zunächst eine Raumladungszone in der obersten, an Gate bzw. Source angrenzenden Halbleiterschicht. Erreicht diese Raumladungszone die diese oberste Halbleiterschicht zur nächsten Halbleiterschicht begrenzenden, floatenden Halbleitergebiete, so bleibt die Spannung an diesen Gebieten auf dem dann erreichten Wert Vpth stehen, was der Situation eines "punch- through" (Durchgriff) entspricht. Bei weiterer Erhöhung der an Drain liegenden Spannung bildet sich die Raumladungszone in der zweitobersten Halbleiterschicht aus und erreicht schließlich die zweite Ebene der Halbleitergebiete. Dieser Vorgang wiederholt sich, bis schließlich die Raumladungszone auf der Seite des Drainkontaktes eine hochdotierte Zone des einen Leitungstyps erreicht. Als Ergebnis kann so eine Struktur erhalten werden, die die (N+l) -fache Spannungsfestigkeit der gleichen Struktur ohne Halbleitergebiete hat, wenn die Anzahl der Ebenen der Halbleitergebiete durch N gegeben ist.The semiconductor regions, which may also be interconnected like a grid, are preferably arranged in a plurality of planes which are essentially parallel to one another. These levels are easily created when the individual epitaxial layers are deposited or when these layers are applied by direct wafer bonding. When a semiconductor component using such a universal semiconductor wafer, for example an IGBT, in which a positive voltage is applied between the gate and source, is switched on, a space charge zone first arises in the uppermost semiconductor layer adjacent to the gate or source. If this space charge zone reaches the floating semiconductor regions that delimit this uppermost semiconductor layer to the next semiconductor layer, then the voltage at these regions remains at the value V pt h then reached, which corresponds to the situation of a “punch-through”. As the voltage at the drain increases further, the space charge zone forms in the second uppermost semiconductor layer and finally reaches the second level of the semiconductor regions. This process is repeated until finally the space charge zone on the side of the drain contact reaches a highly doped zone of the one line type. As a result, a structure can be obtained which has (N + 1) times the dielectric strength of the same structure without semiconductor regions if the number of levels of the semiconductor regions is given by N.
Der eine Leitungstyp ist in bevorzugter Weise der n-Leitungs- typ, so daß der andere Leitungstyp durch den p-Leitungstyp gegeben ist und die floatenden Halbleitergebiete somit p-do- 4 tiert sind. Selbstverständlich ist aber auch eine Dotierung mit umgekehrten Leitungstypen möglich.One line type is preferably the n line type, so that the other line type is given by the p line type and the floating semiconductor regions are thus p-type. 4 are. Of course, doping with reversed line types is also possible.
Bei dem zuletzt genannten Beispiel eines IGBT's kann die hochdotierte Halbleiterschicht des einen Leitungstyps, also in bevorzugter Weise eine n+-leitende Pufferschicht, auch durch eine andere Schicht, beispielsweise durch eine sogenannte "Non-punch-through"-Struktur ersetzt werden.In the last-mentioned example of an IGBT, the highly doped semiconductor layer of one conductivity type, that is to say preferably an n + -conducting buffer layer, can also be replaced by another layer, for example by a so-called "non-punch-through" structure.
Die Halbleitergebiete sind so dotiert, daß die RaumladungsZonen die einzelnen Halbleiterschichten bei angelegter Spannung vollständig ausfüllen, bevor ein Durchbruch eintritt. Die Dotierung der Halbleitergebiete ist dabei so hoch, daß sie nicht vollständig ausgeräumt werden. Dies gilt bevorzugt für den Mittenbereich des Halbleiterbauelementes, jedoch nicht für die Randbereiche: dort kann die Dotierung der Halbleitergebiete so niedrig sein, daß sie bei anliegender Spannung ausgeräumt werden.The semiconductor regions are doped so that the space charge zones completely fill the individual semiconductor layers when a voltage is applied before a breakdown occurs. The doping of the semiconductor regions is so high that they are not completely cleared out. This preferably applies to the central region of the semiconductor component, but not to the edge regions: there the doping of the semiconductor regions can be so low that they are removed when the voltage is applied.
Die erfindungsgemäße Universal-Halbleiterscheibe eignet sich in besonders vorteilhafter Weise zur Herstellung von Dioden, MOSFET's mit Feldplattenrand oder IGBT's bzw. GTO's mit planaren Randstrukturen oder auch für andere Halbleiterbauelemente, wie beispielsweise "Non-punch-through-IGBT' s" mit dünn geschliffener Rückseite.The universal semiconductor wafer according to the invention is particularly advantageously suitable for the production of diodes, MOSFETs with field plate edges or IGBTs or GTOs with planar edge structures or for other semiconductor components, such as, for example, "non-punch-through-IGBTs" with a thinly ground back .
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 ein Schnittbild durch eine erfindungsgemäßeFig. 1 is a sectional view through an inventive
Universal-Halbleiterscheibe,Universal semiconductor wafer,
Fig. 2 ein Schnittbild durch eine Diode der erfindungsgemäßen Universal-Halbleiterscheibe, 52 shows a sectional view through a diode of the universal semiconductor wafer according to the invention, 5
Fig. 3 ein Schnittbild durch einen IGBT mit der er¬ findungsgemäßen Universal-Halbleiterscheibe, und3 shows a sectional view through an IGBT with the universal semiconductor wafer according to the invention, and
Fig. 4 ein Schnittbild durch einen abgewandeltenFig. 4 is a sectional view through a modified
IGBT mit der erfindungsgemäßen Universal- Halbleiterscheibe .IGBT with the universal semiconductor wafer according to the invention.
Obwohl die Fig. 1 bis 4 Schnittbilder zeigen, sind zur Vereinfachung der Darstellung dort Schraffuren teilweise weggelassen. Auch werden in den Figuren einander entsprechende Bauteile jeweils mit den gleichen Bezugszeichen versehen.Although FIGS. 1 to 4 show sectional images, hatching is partially omitted there to simplify the illustration. Components that correspond to one another are also provided with the same reference symbols in the figures.
Fig. 1 zeigt eine Universal-Halbleiterscheibe 1 mit einer Vorderseite 2 und einer Rückseite 3, bei der auf einem n- leitenden Substrat 4 mit einer Dotierungskonzentration n0 nacheinander eine n-leitende epitaktische Schicht 5 mit einer Dotierungskonzentration ni, eine zweite n-leitende epitaktische Schicht 6 mit einer Dotierungskonzentration n2 und eine dritte n-leitende epitaktische Schicht 7 mit einer Dotierungskonzentration n3 vorgesehen sind. Anstelle der epitaktischen Schichten 5, 6 und 7 können auch entsprechende Schichten durch Direkt-Waferbonden vorgesehen werden. Auch können die Dotierungskonzentrationen im Lithium-Substrat 4 und den epitaktischen Schichten 5, 6 und 7 jeweils gleich zueinander sein.1 shows a universal semiconductor wafer 1 with a front side 2 and a rear side 3, in which, on an n-conducting substrate 4 with a doping concentration n 0 , an n-conducting epitaxial layer 5 with a doping concentration ni, a second n-conducting layer epitaxial layer 6 with a doping concentration n 2 and a third n-conducting epitaxial layer 7 with a doping concentration n 3 are provided. Instead of the epitaxial layers 5, 6 and 7, corresponding layers can also be provided by direct wafer bonding. The doping concentrations in the lithium substrate 4 and the epitaxial layers 5, 6 and 7 can also be identical to one another.
Die epitaktischen Schichten 5, 6 und 7 können undotiert abgeschieden und nachträglich durch Neutronen-Transmutation dotiert sein.The epitaxial layers 5, 6 and 7 can be deposited undoped and subsequently doped by neutron transmutation.
Erfindungsgemäß befinden sich zwischen dem Substrat 4 und der Schicht 5, sowie zwischen der Schicht 5 und der Schicht 6 und zwischen der Schicht 6 und der Schicht 7 jeweils p-leitende Gebiete 8, die jeweils "Inseln" bilden oder auch gitterähn- 6 lieh zusammenhängen können. Diese Gebiete 8 werden durch Diffusion oder Ionenimplantation vor dem Auftragen der jeweils nachfolgenden Schicht 5 bzw. 6 bzw. 7 eingebracht. So werden beispielsweise die Gebiete 8 der in Fig. 1 untersten Ebene durch Diffusion oder Ionenimplantation in die Oberfläche des Substrates 4 eingebracht, bevor die Schicht 5 epitaktisch abgeschieden wird. Nach dem Abscheiden der Schicht 5 werden die Gebiete 8 der "mittleren" Ebene durch Diffusion oder Ionenimplantation eingebracht. Schließlich werden nach dem Abscheiden der epitaktischen Schicht 6 die Gebiete 8 der obersten Ebene eingebracht, bevor anschließend die Schicht 7 epitaktisch abgeschieden wird.According to the invention, there are p-type regions 8 between the substrate 4 and the layer 5, as well as between the layer 5 and the layer 6 and between the layer 6 and the layer 7, each of which form "islands" or also lattice-like 6 may be related. These areas 8 are introduced by diffusion or ion implantation before the subsequent layer 5 or 6 or 7 is applied. For example, regions 8 of the lowest level in FIG. 1 are introduced into the surface of substrate 4 by diffusion or ion implantation before layer 5 is deposited epitaxially. After the layer 5 has been deposited, the regions 8 of the “middle” plane are introduced by diffusion or ion implantation. Finally, after the epitaxial layer 6 has been deposited, the regions 8 of the top level are introduced before the layer 7 is subsequently deposited epitaxially.
Zwischen die einzelnen epitaktischen Schichten können in deren Grenzflächen Lebensdauer-Killer, wie beispielsweise Platin und/oder Gold, implantiert oder auf sonstige Weise eingebracht werden.Lifetime killers, such as platinum and / or gold, can be implanted or otherwise introduced between the individual epitaxial layers in their interfaces.
Die einzelnen Gebiete 8 "floaten", auch wenn sie, was bereits erwähnt wurde, wenigstens teilweise oder ganz in einer Ebene zusammenhängen können.The individual regions 8 "float", even if, as has already been mentioned, they can be connected at least partially or entirely in one plane.
Der Abstand d zwischen den einzelnen Gebieten 8 einer Ebene entspricht etwa dem Durchmesser b dieser Gebiete oder ist etwas größer als dieser. Außerdem ist der Abstand d zwischen den einzelnen Gebieten 8 einer Ebene kleiner als der Abstand Di, D2 zwischen den einzelnen Ebenen.The distance d between the individual areas 8 of a plane corresponds approximately to the diameter b of these areas or is somewhat larger than this. In addition, the distance d between the individual areas 8 of a level is smaller than the distance Di, D 2 between the individual levels.
Die erfindungsgemäße Universal-Halbleiterscheibe eignet sich in vorteilhafter Weise für Dioden, MOSFET's mit Feldplattenrand, IGBT', GTO's mit planaren Randstrukturen oder andere Halbleiterbauelemente, wie beispielsweise "Non-punch-through- IGBT's" mit dünn geschliffener Rückseite 3. 7The universal semiconductor wafer according to the invention is advantageously suitable for diodes, MOSFETs with field plate edges, IGBTs, GTOs with planar edge structures or other semiconductor components, such as, for example, “non-punch-through IGBTs” with a thinly ground rear side 3. 7
Ein Beispiel einer Diode mit Aluminium-Elektroden 9, 10, einer p-leitenden Zone 11, einer Feldplatte 12 und einer Isolierschicht 13 aus Siliziumdioxid ist in Fig. 2 gezeigt. Die Dotierungskonzentration in den Gebieten 8 im Bereich des Randes 14 dieser Diode ist etwas schwächer als die Dotierungskonzentration der Gebiete 8 im Mittenbereich der Diode, also in Fig. 2 im wesentlichen unterhalb der Zone 11. So sind im Mittenbereich die Gebiete 8 so hoch dotiert, daß sie bei Anlegen einer Spannung zwischen die Elektroden 9, 10 nicht vollständig von Ladungsträgern ausgeräumt werden. Dies gilt nicht für den Bereich in der Nähe des Randes 14, wo die Gebiete 8 nur so stark dotiert sind, daß sie bei Anlegen dieser Spannung tatsächlich ausgeräumt sind.An example of a diode with aluminum electrodes 9, 10, a p-type zone 11, a field plate 12 and an insulating layer 13 made of silicon dioxide is shown in FIG. 2. The doping concentration in the regions 8 in the region of the edge 14 of this diode is somewhat weaker than the doping concentration in the regions 8 in the central region of the diode, that is to say essentially in FIG. 2 below the zone 11. The regions 8 in the central region are doped so highly that they are not completely cleared of charge carriers when a voltage is applied between the electrodes 9, 10. This does not apply to the area near the edge 14, where the regions 8 are only so heavily doped that they are actually cleared out when this voltage is applied.
An der Elektrode 9 liegt beispielsweise eine Spannung +U, während die Elektrode 10 geerdet sein kann. Die Feldplatte 12 dient wie die im Bereich des Randes 14 schwächer werdende Dotierung der Gebiete 8 dazu, einen Durchbruch im Bereich des Randes 14 der Diode zu verhindern.A voltage + U is present at the electrode 9, for example, while the electrode 10 can be grounded. The field plate 12, like the doping of the regions 8 which becomes weaker in the region of the edge 14, serves to prevent a breakdown in the region of the edge 14 of the diode.
Die Fig. 3 und 4 zeigen jeweils einen Schnitt durch einen IGBT mit der erfindungsgemäßen Universal-Halbleiterscheibe 1. Diese Universal-Halbleiterscheibe 1 weist zusätzlich eine n+- leitende Schicht 16 und eine p+-leitende Schicht 17 auf, auf der ein Drainkontakt 15 für «inen Drainanschluß D mit einer Spannung +UD aufgetragen ist. Außerdem sind eine Sourcemetal- lisierung 18, die geerdet ist, Gateelektroden 19 aus polykristallinem Silizium, die untereinander verbunden sind und an denen eine Gatespannung UG liegt, eine Feldplatte 20 aus polykristallinem Silizium, die mit der Sourcemetallisierung 18 verbunden ist, und ein Kanal- bzw. Channel-Stopper 21 aus polykristallinem Silizium, der elektrisch mit der Schicht 7 verbunden ist, gezeigt. Die Gateelektroden 19, die Feldplatte 20 und der Channel-Stopper 21 sind in einer Isolierschicht 22 aus beispielsweise Siliziumdioxid und/oder Siliziumnitrid 8 eingebettet, die unterhalb der Gateelektroden 19 auch das Gateoxid bildet. Im Oberflächenbereich der Schicht 7 befinden sich noch n+-leitende Bereiche 23 sowie p-leitende Bereiche 24, die zusammen jeweils Sourcezonen bilden, die mit der Sourcemetallisierung 18 kontaktiert sind.Figs. 3 and 4 respectively show a sectional view of an IGBT with the inventive Universal wafer 1. This universal semiconductor wafer 1 has, in addition, an n + - type layer 16 and a p + -type layer 17, on which a drain contact 15 for a drain connection D with a voltage + U D is plotted. In addition, a source metalization 18, which is grounded, gate electrodes 19 made of polycrystalline silicon, which are connected to one another and to which a gate voltage U G is applied, a field plate 20 made of polycrystalline silicon, which is connected to the source metalization 18, and a channel or channel stopper 21 made of polycrystalline silicon, which is electrically connected to the layer 7. The gate electrodes 19, the field plate 20 and the channel stopper 21 are in an insulating layer 22 made of, for example, silicon dioxide and / or silicon nitride 8 embedded, which also forms the gate oxide below the gate electrodes 19. In the surface area of the layer 7 there are also n + -conducting areas 23 and p -conducting areas 24, which together form source zones which are in contact with the source metallization 18.
Bei Einschalten des IGBT's, also bei Anlegen einer Spannung +UGs zwischen Gateelektroden 19 und Sourcemetallisierung 18 bildet sich zuerst eine Raumladungszone in der obersten Schicht 7. Wenn diese Raumladungszone die oberste Ebene der p-leitenden Halbleitergebiete 8 zwischen den Schichten 6 und 7 bei einem Spannungswert Vpth erreicht, bleibt die Spannung dieser Halbleitergebiete 8 auf dem Spannungswert Vpth stehen, wobei die Situation eines "punch-through" (Durchgriff) auftritt. Bei weiterer Erhöhung der Drainspannung UD bildet sich die Raumladungszone in der Schicht 6 aus und erreicht schließlich die Halbleitergebiete zwischen den Schichten 5 und 6. Dies geht so weiter, bis die Raumladungszone schließlich an der n+-leitenden Schicht 16 ankommt. Damit wird die vierfache Spannungsfestigkeit einer Struktur erreicht, die mit allein einer n-Dotierung ohne die p-dotierten Gebiete 8 zu erreichen wäre. Durch zusätzliche Ebenen mit Halbleitergebieten 8 kann die Spannungsfestigkeit weiter gesteigert werden.When the IGBT is switched on, i.e. when a voltage + U Gs is applied between gate electrodes 19 and source metallization 18, a space charge zone first forms in the top layer 7. If this space charge zone is the top level of the p-type semiconductor regions 8 between layers 6 and 7 in one When the voltage value V pth is reached, the voltage of these semiconductor regions 8 remains at the voltage value V pth , the situation of a "punch-through" occurring. With a further increase in the drain voltage U D , the space charge zone forms in the layer 6 and finally reaches the semiconductor regions between the layers 5 and 6. This continues until the space charge zone finally arrives at the n + -conducting layer 16. This achieves four times the dielectric strength of a structure that could be achieved with n-doping alone without the p-doped regions 8. The dielectric strength can be further increased by additional levels with semiconductor regions 8.
Anstelle der n+-dotierten Halbleiterschicht 16, der p+-do- tierten Halbleiterschicht 17 und der Sourcezonen 23, 24 können auch andere Schichten vorgesehen werden, um einen GTO, einen MOSFET oder andere Halbleiterbauelemente zu bilden.Instead of the n + -doped semiconductor layer 16, the p + -doped semiconductor layer 17 and the source zones 23, 24, other layers can also be provided in order to form a GTO, a MOSFET or other semiconductor components.
Die schwächer werdende Dotierung der Halbleitergebiete 8 im Bereich des Randes 14 kann auch dadurch erreicht werden, daß zusätzlich n+-hochdotierte Halbleitergebiete 25 den p+-do- tierten Halbleitergebieten 8 zugeordnet werden, wie dies im Ausführungsbeispiel von Fig. 4 gezeigt ist. The weakening doping of the semiconductor regions 8 in the region of the edge 14 can also be achieved by additionally assigning n + -doped semiconductor regions 25 to the p + -doped semiconductor regions 8, as is shown in the exemplary embodiment in FIG. 4.

Claims

9Patentansprüche 9 Patent claims
1. Universal-Halbleiterscheibe für Hochvolt-Halbleiterbauelemente, bei der auf einem Halbleitersubstrat (4) des einen Leitungstyps mindestens eine epitaktische Schicht (5, 6, 7) des einen Leitungstyps vorgesehen ist, d a d u r c h g e k e n n z e i c h n e t , daß in den Grenzflächen zwischen dem Halbleitersubstrat (4) und der mindestens einen Schicht (5, 6, 7) eine Vielzahl von floatenden Halbleitergebieten (8) des anderen Leitungstyps eingebettet sind, die so bemessen sind, daß die Abmessung eines floatenden Halbleitergebietes (8) klein gegenüber der Schichtdicke der mindestens einen Schicht (5, 6, 7) ist und im wesentlichen dem Abstand zwischen den floatenden Gebieten (8) in einer Grenzfläche entspricht oder kleiner als dieser ist.1. Universal semiconductor wafer for high-voltage semiconductor components in which at least one epitaxial layer (5, 6, 7) of one conductivity type is provided on a semiconductor substrate (4) of one conductivity type, characterized in that in the interfaces between the semiconductor substrate (4) and the at least one layer (5, 6, 7) is embedded with a multiplicity of floating semiconductor regions (8) of the other conductivity type, which are dimensioned such that the dimension of a floating semiconductor region (8) is small compared to the layer thickness of the at least one layer (5 , 6, 7) and essentially corresponds to the distance between the floating regions (8) in an interface or is smaller than this.
2. Universal-Halbleiterscheibe nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß die mindestens eine Schicht (5, 6, 7) eine epitaktische Schicht ist.2. Universal semiconductor wafer according to claim 1, so that the at least one layer (5, 6, 7) is an epitaxial layer.
3. Universal-Halbleiterscheibe nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß die mindestens eine Schicht (5, 6, 7) durch Direkt- Waferbonding aufgetragen ist.3. Universal semiconductor wafer according to claim 1, so that the at least one layer (5, 6, 7) is applied by direct wafer bonding.
4. Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 3, d a d u r c h g e k e n n z e i c h n e t , daß die floatenden Halbleitergebiete (8) durch Diffusion oder Ionenimplantation oder Implantation und nachfolgende Ausdiffusion vor Abscheidung der folgenden Schicht (5, 6, 7) eingebracht sind. 104. Universal semiconductor wafer according to one of claims 1 to 3, characterized in that the floating semiconductor regions (8) by diffusion or ion implantation or implantation and subsequent diffusion are introduced before deposition of the following layer (5, 6, 7). 10
5. Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t , daß die mindestens eine Schicht (5, 6, 7) undotiert aufgetragen und nachträglich durch Neutronentransmutation dotiert ist.5. Universal semiconductor wafer according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the at least one layer (5, 6, 7) is applied undoped and subsequently doped by neutron transmutation.
6. Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 5, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete (8) ein Gitter bilden.6. Universal semiconductor wafer according to one of claims 1 to 5, d a d u r c h g e k e n n z e i c h n e t that the semiconductor regions (8) form a grid.
7. Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 6, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete (8) in mehreren, im wesentlichen zueinander parallelen Ebenen zwischen den einzelnen Schichten angeordnet sind.7. Universal semiconductor wafer according to one of claims 1 to 6, d a d u r c h g e k e n n z e i c h n e t that the semiconductor regions (8) are arranged in several, essentially mutually parallel planes between the individual layers.
8. Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 7, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete (8) im Bereich des Randes (14) der Universal-Halbleiterscheibe schwächer als in deren Mittenbereich dotiert sind.8. Universal semiconductor wafer according to one of claims 1 to 7, d a d u r c h g e k e n n z e i c h n e t that the semiconductor regions (8) in the region of the edge (14) of the universal semiconductor wafer are less doped than in the central region.
9. Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 8, d a d u r c h g e k e n n z e i c h n e t , daß zwischen die Halbleitergebiete (8) in deren jeweiligen Ebenen noch vereinzelt Halbleitergebiete (25) des einen Leitungstyps eingebracht sind, die höher dotiert sind als die jeweiligen Schichten (5, 6, 7) . 119. Universal semiconductor wafer according to one of claims 1 to 8, characterized in that between the semiconductor regions (8) in their respective planes are still occasionally introduced semiconductor regions (25) of one conduction type which are doped higher than the respective layers (5, 6 , 7). 11
10. Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 9, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete im Mittenbereich bzw. im Randbereich so hoch dotiert sind, daß bei Anlegung einer Spannung diese nicht ausgeräumt bzw. ausgeräumt sind.10. Universal semiconductor wafer according to one of claims 1 to 9, d a d u r c h g e k e n n z e i c h n e t that the semiconductor regions in the central region or in the edge region are doped so high that they are not cleared or applied when a voltage is applied.
11. Verfahren zum Herstellen der Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 10, d a d u r c h g e k e n n z e i c h n e t , daß vor dem Anbringen einer Halbleiterschicht (5, 6, 7) auf das Halbleitersubstrat (4) bzw. auf eine zuvor aufgebrachte Halbleiterschicht (5, 6) in die Oberfläche des Halbleitersubstrates (4) bzw. der bereits aufgebrachten Halbleiterschicht (5, 6) durch Diffusion oder Ionenimplantation die Halbleitergebiete (8) des anderen Leitungstyps eingebracht werden.11. A method for producing the universal semiconductor wafer according to one of claims 1 to 10, characterized in that before the application of a semiconductor layer (5, 6, 7) on the semiconductor substrate (4) or on a previously applied semiconductor layer (5, 6) the semiconductor regions (8) of the other conductivity type are introduced into the surface of the semiconductor substrate (4) or the already applied semiconductor layer (5, 6) by diffusion or ion implantation.
12. Verfahren nach Anspruch 11, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete (8) derart eingebracht werden, daß diese im Bereich des Randes (14) der Halbleiterscheibe (1) schwächer als in deren Mittenbereich dotiert sind.12. The method according to claim 11, so that the semiconductor regions (8) are introduced such that they are less doped in the region of the edge (14) of the semiconductor wafer (1) than in the central region thereof.
13. Verfahren nach Anspruch 11 oder 12, d a d u r c h g e k e n n z e i c h n e t , daß die Grenzflächen zwischen den Schichten (5, 6, 7) mit Lebensdauer-Killern versehen werden.13. The method according to claim 11 or 12, so that the interfaces between the layers (5, 6, 7) are provided with lifetime killers.
14. Verfahren nach Anspruch 13, d a d u r c h g e k e n n z e i c h n e t , daß die Lebensdauer-Killer in die Grenzflächen eingebracht werden.14. The method according to claim 13, d a d u r c h g e k e n n z e i c h n e t that the lifetime killers are introduced into the interfaces.
15. Verfahren nach Anspruch 14, 12 d a d u r c h g e k e n n z e i c h n e t , daß die Lebensdauer-Killer implantiert werden.15. The method according to claim 14, 12 characterized in that the lifetime killers are implanted.
16. Verfahren nach einem der Ansprüche 13 bis 15, d a d u r c h g e k e n n z e i c h n e t , daß als Lebensdauer-Killer Platin und/oder Gold verwendet werden.16. The method according to any one of claims 13 to 15, d a d u r c h g e k e n n z e i c h n e t that platinum and / or gold are used as lifespan killers.
17. Verwendung der Universal-Halbleiterscheibe nach einem der Ansprüche 1 bis 10 in einer Diode, einem MOSFET, einem IGBT, einem GTO oder einem anderen Schalter. 17. Use of the universal semiconductor wafer according to one of claims 1 to 10 in a diode, a MOSFET, an IGBT, a GTO or another switch.
EP99915461A 1998-04-14 1999-02-08 Universal semiconductor wafer for high-voltage semiconductor components Withdrawn EP1092238A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19816448A DE19816448C1 (en) 1998-04-14 1998-04-14 Universal semiconductor wafer for high-voltage semiconductor components, their manufacturing process and their use
DE19816448 1998-04-14
PCT/DE1999/000327 WO1999053549A1 (en) 1998-04-14 1999-02-08 Universal semiconductor wafer for high-voltage semiconductor components

Publications (1)

Publication Number Publication Date
EP1092238A1 true EP1092238A1 (en) 2001-04-18

Family

ID=7864450

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99915461A Withdrawn EP1092238A1 (en) 1998-04-14 1999-02-08 Universal semiconductor wafer for high-voltage semiconductor components

Country Status (5)

Country Link
US (1) US6646304B1 (en)
EP (1) EP1092238A1 (en)
JP (1) JP2002511657A (en)
DE (1) DE19816448C1 (en)
WO (1) WO1999053549A1 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19830332C2 (en) * 1998-07-07 2003-04-17 Infineon Technologies Ag Vertical semiconductor device with reduced electrical surface field
US6642558B1 (en) 2000-03-20 2003-11-04 Koninklijke Philips Electronics N.V. Method and apparatus of terminating a high voltage solid state device
DE10061528C1 (en) * 2000-12-11 2002-07-25 Infineon Technologies Ag Semiconductor component controllable by field effect
DE10108046B4 (en) * 2001-02-20 2006-10-19 Infineon Technologies Ag Semiconductor device
DE10117801B4 (en) * 2001-04-10 2005-12-22 Robert Bosch Gmbh Semiconductor power device and corresponding manufacturing method
DE10117802A1 (en) * 2001-04-10 2002-10-24 Bosch Gmbh Robert Semiconductor power component e.g. emitter switched thyristor as ignition transistor of ignition coil of combustion engine, has drift zone joined to rear face emitter zone
US7161208B2 (en) * 2002-05-14 2007-01-09 International Rectifier Corporation Trench mosfet with field relief feature
GB0417749D0 (en) * 2004-08-10 2004-09-08 Eco Semiconductors Ltd Improved bipolar MOSFET devices and methods for their use
DE102005046707B3 (en) * 2005-09-29 2007-05-03 Siced Electronics Development Gmbh & Co. Kg SiC-PN power diode
JP4453671B2 (en) 2006-03-08 2010-04-21 トヨタ自動車株式会社 Insulated gate semiconductor device and manufacturing method thereof
US7955929B2 (en) 2007-01-10 2011-06-07 Freescale Semiconductor, Inc. Method of forming a semiconductor device having an active area and a termination area
JP6139356B2 (en) * 2013-09-24 2017-05-31 トヨタ自動車株式会社 Semiconductor device
EP2889914A1 (en) * 2013-12-30 2015-07-01 ABB Technology AG Bipolar semiconductor device
US10468510B2 (en) 2015-07-16 2019-11-05 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of the same
CN112259599B (en) * 2020-10-21 2021-10-12 清华大学 Silicon wafer bonding type IGBT device and manufacturing method thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2439430C2 (en) * 1974-08-16 1983-02-17 Siemens AG, 1000 Berlin und 8000 München Process for the production of homogeneously doped semiconductor material with p-conductivity
DE2617320A1 (en) * 1976-04-21 1977-11-03 Siemens Ag Homogeneous phosphorus doping of silicon using thermal neutrons - calculating dosage using reactor-specific constant to increase accuracy
US4431848A (en) 1982-04-26 1984-02-14 Koppers Company, Inc. Preparation of resorcinol and substituted resorcinols by liquid-phase dehydrogenation of 1,3-cyclic diones derived by vapor-phase cyclization of delta-keto carboxylic acid esters
FR2526587B1 (en) * 1982-05-10 1987-02-27 Gen Electric BIDIRECTIONAL POWER, OXIDE-SILICON METAL FIELD TRANSISTOR DEVICE
US4656493A (en) 1982-05-10 1987-04-07 General Electric Company Bidirectional, high-speed power MOSFET devices with deep level recombination centers in base region
IT1214805B (en) * 1984-08-21 1990-01-18 Ates Componenti Elettron SEMICONDUCTOR WITH JUNPROCESS DEVICES FOR THE MANUFACTURE OF VARIABLE CHARGE CONCENTRATION PLANAR DIRECTIONS AND VERY HIGH BREAKDOWN VOLTAGE
GB2237930A (en) * 1989-11-01 1991-05-15 Philips Electronic Associated A semiconductor device and method of manufacturing a semiconductor device
JP2701502B2 (en) * 1990-01-25 1998-01-21 日産自動車株式会社 Semiconductor device
US5111254A (en) * 1990-08-17 1992-05-05 Gte Laboratories Incorporated Floating gate array transistors
DE4309764C2 (en) * 1993-03-25 1997-01-30 Siemens Ag Power MOSFET
JP2801127B2 (en) * 1993-07-28 1998-09-21 日本碍子株式会社 Semiconductor device and manufacturing method thereof
US6037632A (en) * 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
KR100206555B1 (en) * 1995-12-30 1999-07-01 윤종용 Power transistor
DE19604044C2 (en) * 1996-02-05 2002-01-17 Siemens Ag Semiconductor component controllable by field effect
EP0879481B1 (en) 1996-02-05 2002-05-02 Infineon Technologies AG Field effect controlled semiconductor component

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9953549A1 *

Also Published As

Publication number Publication date
DE19816448C1 (en) 1999-09-30
US6646304B1 (en) 2003-11-11
WO1999053549A1 (en) 1999-10-21
JP2002511657A (en) 2002-04-16

Similar Documents

Publication Publication Date Title
EP0057256B1 (en) Vertical mis field effect transistor with low forward resistance
DE19811297B4 (en) High breakdown voltage MOS semiconductor device
DE102013113939B4 (en) Semiconductor devices with stepped edge termination and method for manufacturing a semiconductor device
WO2000014807A1 (en) High-voltage semiconductor component
EP0996981A1 (en) High-voltage edge termination for planar structures
EP1051756A1 (en) Mos field effect transistor with an auxiliary electrode
DE19816448C1 (en) Universal semiconductor wafer for high-voltage semiconductor components, their manufacturing process and their use
DE19830332A1 (en) Vertical semiconductor device with reduced electrical surface field
DE3787484T2 (en) Wiring design for bipolar and unipolar insulated gate transistors.
EP0913000B1 (en) Field effect controllable semiconductor component
DE10245049B4 (en) Compensation semiconductor component
EP1097482B1 (en) J-fet semiconductor device
DE2904424A1 (en) THYRISTOR CONTROLLED BY FIELD EFFECT TRANSISTOR
DE4310606C2 (en) GTO thyristors
DE102004002723A1 (en) Semiconductor component with an SOI structure
DE102006002438A1 (en) Semiconductor device and method for its production
EP0768717A2 (en) Power semiconductor device
DE112014006158T5 (en) Power semiconductor device
EP0600241A2 (en) MOS driven diode
EP0389942B1 (en) High blocking voltage semiconductor device
DE102020202036A1 (en) Vertical field effect transistor and method of forming the same
DE19638437A1 (en) Semiconductor component controllable by field effect
EP0658940A1 (en) Semiconductor element controlled by field effect
WO2000035020A1 (en) Lateral high-voltage semiconductor component with reduced specific closing resistor
EP3387677B1 (en) Semiconductor transistor comprising superlattice structures

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20001019

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IE IT

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20030829