EP0919982B1 - Circuit de command d'affichage à cristaux liquides avec commande des sous trames - Google Patents

Circuit de command d'affichage à cristaux liquides avec commande des sous trames Download PDF

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Publication number
EP0919982B1
EP0919982B1 EP19980121762 EP98121762A EP0919982B1 EP 0919982 B1 EP0919982 B1 EP 0919982B1 EP 19980121762 EP19980121762 EP 19980121762 EP 98121762 A EP98121762 A EP 98121762A EP 0919982 B1 EP0919982 B1 EP 0919982B1
Authority
EP
European Patent Office
Prior art keywords
data
display
buffer
controller
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19980121762
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German (de)
English (en)
Other versions
EP0919982A1 (fr
Inventor
On Ki Andrew Chu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
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Motorola Inc
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Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0919982A1 publication Critical patent/EP0919982A1/fr
Application granted granted Critical
Publication of EP0919982B1 publication Critical patent/EP0919982B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/08—Cursor circuits

Definitions

  • This invention relates to a controller for a display and in particular to a LCD controller that requires a reduced amount of memory.
  • a LCD has a matrix of picture elements or pixels. Each pixel can be switched to an opaque state or a clear state by application of corresponding voltage levels, and by selectively applying the voltage levels to each of the pixels, information is presented on the display.
  • N denotes the number of different shades or levels from the opaque to the clear states.
  • information indicating the grey level for each pixel is stored in a memory known as a pixel buffer which is located in the LCD controller.
  • the pixel buffer In a binary based system, the pixel buffer must store log 2 N bits per pixel for a display to have N grey levels. For example, when 4 grey levels are required, the pixel buffer needs to store 2 binary digits or bits per pixel, and when 16 grey levels are required, the pixel buffer stores 4 bits per pixel. Consequently, the larger the number of grey levels the larger the amount of memory required for a pixel buffer.
  • European patent application EP0766222 teaches a display controller having a memory for storing a display frame of bit plane data, which switches the pixels on a display.
  • the size of the memory which is required must accommodate at least the number of pixels to fill one frame on the display, and when displays having different numbers of pixels are used with the controller, the memory may need to be changed to match the display.
  • PCT patent application WO9209064 also teaches a display memory which stores at least two frames of switching data which switches the pixels on a display.
  • the size of the memory is greater than a single frame of the display.
  • DMA direct memory access
  • the present invention therefore seeks to provide a LCD controller whose memory requirement does not increase substantially in proportion to the number of grey levels to be displayed.
  • the invention provides a display comprising:
  • the invention provides a method in a liquid crystal display (LCD) controller comprising the steps of:
  • a liquid crystal display (LCD) controller 10 receives information from a central processing unit (CPU) 12 which includes information for display on a display 25, and information on how the information for display is to be displayed.
  • the information for display indicates which picture elements (pixels) on the display 25 of the display module 23 are to be turned ON and which are to be turned OFF, and when this information is provided to a display, the information is displayed in "black” and "white” only.
  • the information on how the information for display is to be displayed includes pixel intensity data that indicate the selected frequency at which each pixel is to be switched ON and OFF, the particular pixels can be displayed having selected "grey" levels or tones.
  • the LCD controller 10 is coupled to the CPU 12 and a memory 16 via an address bus 18 and a data bus 21.
  • a memory controller 14 is coupled between the memory 16 and the CPU 12 to control access by the CPU 12 to the memory 16.
  • the LCD controller 10 is also coupled to a display module 23 having the display 25 with a matrix of pixels thereon.
  • the LCD controller 10 includes control registers 31 that are coupled to the address bus 18 and the data bus 21, and to provide an output to a direct memory access (DMA) controller 33.
  • the control registers 31 receive, store, and provide control information to and from the CPU 12, and the control information determines the operation of the LCD controller 10.
  • the DMA controller 33 is also coupled to the address bus 18 and the data bus 21, and is coupled to provide an output to a screen panning circuit 35.
  • the DMA controller 33 controls the transfer of data from the memory 16 to the LCD controller 10.
  • the DMA controller 33 also has an input that is coupled to receive control information from the control registers 31 that determines the operation of the DMA controller 33.
  • the DMA controller 33 also has an input for receiving a low data signal and an input for receiving a buffer full signal. Upon receipt of the low data signal the DMA controller 33 will transfer more data from the memory 16 to the LCD controller 10, and upon receiving the buffer full signal the DMA controller 33 stops transferring data from the memory to the LCD controller 10.
  • the screen panning circuit 35 shifts the information displayed on the display 25 horizontally by a number of pixels, where the number of pixels is programmed in the control registers 31.
  • the screen panning circuit 35 has an output which is coupled to a frame rate controller 37.
  • the frame rate controller 37 receives a frame synchronising signal (32 in FIG. 2) and information including pixel intensity data from the memory 16, and controls the switching or ON/OFF frequency of the pixels on the display 25 so that the pixels will be displayed in accordance with the pixel intensity data.
  • the frame rate controller 37 provides an output to a cursor logic circuit 39 which provides an output to a pixels buffer 41.
  • the cursor logic circuit 39 adds the cursor to the information displayed on the display 25 and is implemented by overlay or logic operation of the pixels with a predefined cursor bitmap.
  • the pixels buffer 41 is a first-in-first-out (FIFO) structure that holds information being displayed on the display 25.
  • the information provided from the output of the pixels buffer 41 is only the ON/OFF switching information for each of the pixels on the display 25.
  • the number of storage locations for storing bits in the pixel buffer 41 can equal the number of pixels on the display 25.
  • the number of storage locations in the pixel buffer 41 is less than the number of pixels on the display 25, and several transfers of pixel intensity data are made from the memory 16 to the frame rate controller 37 under the control of the DMA controller 31 to provide switching data for all the pixels on the display 25.
  • a trade off is made based upon the amount of data traffic caused by the frequency of data transfer and the size of the pixel buffer 41.
  • the pixels buffer 41 has an output that provides the low data signal and an output that provides the buffer full signal, to the DMA controller 33.
  • the pixels buffer provides the low data signal when the switching data in the pixels buffer 41 is less than a predetermined level. For example, when the predetermined level is 2 data words for a pixels buffer having a 4 data word capacity, the pixels buffer will generate the low data signal when 2 or less data words remain in the pixels buffer. When there are 4 data words in the pixels buffer, the pixels buffer will stop transferring data from the memory 16 to the frame rate controller 37.
  • the output of the pixels buffer 41 is provided to a LCD interface 42 that packs the display data so that it matches control signals, data bus width and polarity of the display module 23.
  • the LCD interface 42 converts the output of the pixels buffer 41 into a form suitable for switching pixels on the display 25, and provides the converted information to the display module 23.
  • FIG. 2 the simplified block diagram will be used to describe the operation of the LCD controller 10 for a 4 level grey scale display.
  • pixels 45 on the display can have one of four intensity levels.
  • 4 complete screens of pixels, each referred to as a frame 50, 50A, 50B and 50C, are displayed sequentially in accordance with a frame synchronising signal.
  • the number of frames of the four frames 50, 50A, 50B and 50C in which the pixels 45 are switched ON determines the intensity of those pixels on the display (25 in FIG. 1).
  • a pixel has the highest intensity when it is switched ON in all the four frames 50, 50A, 50B and 50C.
  • a pixel has an even lower intensity when it is switched ON in every third frame of the four frames 50, 50A, 50B and 50C.
  • a pixel has the lowest intensity when it is switched OFF in all of the four frames 50, 50A, 50B and 50C.
  • Two binary digits or bits are required to select each of the 4 intensity levels for each of the pixels 45.
  • 8 bits are required, and these are stored as display intensity data 60 in the memory 16.
  • the eight bits constitute 4 pairs of 2 bits, where each pair is for each of the 4 pixels 45 in the top row 47 of the display (25 in FIG. 1).
  • the pixels buffer 41 stores one bit 42 for each pixel 45, hence, the pixel buffer 41 stores 4 bits for the 4 pixels 45 in the top row 47 of the display (25 in FIG. 1).
  • Each bit 42 in the pixels buffer 41 represents the switching status of corresponding pixels 45 in the top row 47 of the display (25 in FIG. 1).
  • a bit 42 in the pixels buffer 41 is 1 (binary) the corresponding pixel on the display (25 in FIG. 1) is switched ON, and when the bit 42 is 0(binary) that pixel is switched OFF.
  • the pixel buffer here described advantageously stores only one bit for each pixel. Consequently, the total number of bits stored in the pixel buffer is equal to the number of pixels on a display, and is independent of the number of grey levels displayed.
  • the DMA controller 33 transfers the display intensity data 60 from the memory 16 to the frame rate controller 37 in accordance with the low data and buffer full signals received from the pixels buffer 41.
  • the frame rate controller 37 sequentially loads the pixels buffer 41 four times with display data bits 42. This is indicated by the contents of the pixels buffer 41, and the subsequent contents of the pixels buffer 41 as shown in broken lines and labelled 41A, 41B, and 41C.
  • the frame 50 shows the pixels 45 in the top row 47 switched in accordance with the contents of the pixel buffer 41.
  • Corresponding frames 50A, 50B and 50C show the pixels 45 in the top row 47 switched in accordance with the subsequent contents of the pixels buffer 41 as shown in broken lines and labelled 41A, 41B, and 41C.
  • the frame rate controller 37 determines that the first 2 bits of the display intensity data 60 are 11 (binary) indicating the highest intensity level, it stores 1 (binary) in the first bit location in the pixel buffer 41 for each of the 4 frames 50, 50A, 50B and 50C. Similarly, when the next 2 bits of the display intensity data 60 are 10 (binary) indicating the lower intensity level, the frame rate controller 37 stores 1 (binary) in the second bit location in the pixel buffer 41 for each alternate frame 50A and 50C of the four frames 50, 50A, 50B and 50C.
  • the frame rate controller 37 stores a 1 (binary) in the third bit location in the pixel buffer 41 in one frame 50 of the four frames 50, 50A, 50B and 50C.
  • the frame rate controller 37 does not set the fourth bit in the pixel buffer 41 in any of the four frames 50, 50A, 50B and 50C.
  • the described LCD controller advantageously utilises a fixed and limited amount of memory to provide "grey" levels on a display. This is accomplished by storing only one switching data bit for each of the pixels on the display.
  • the present invention therefore provides a display controller whose memory requirements are relatively constant and substantially independent of the number of grey levels to be displayed.

Claims (5)

  1. Dispositif (10) de commande de dispositif d'affichage, comprenant :
    un dispositif (33) de commande d'accès direct en mémoire, destiné à recevoir des données d'intensité de pixels de la part d'une mémoire externe (16) et à fournir des données d'intensité de pixels, et ayant une entrée de données de niveau bas servant à recevoir un signal de données de niveau bas et une entrée de données de tampon plein servant à recevoir un signal de tampon plein, le dispositif (33) de commande d'accès direct en mémoire servant à commander le transfert des données d'intensité de pixels, de la mémoire externe (16) à la sortie de données d'intensité de pixels, en fonction des signaux de données de niveau bas et de tampon plein ;
    un dispositif (37) de commande d'image complète destiné à recevoir des données d'intensité de pixels et ayant une entrée servant à recevoir un signal de synchronisation d'image complète et une sortie servant à produire des données de commutation, le dispositif (37) de commande d'image complète servant à décoder les données d'intensité de pixels et à fournir des données de commutation, et
    un tampon de données d'affichage (41) ayant une entrée couplée à la sortie du dispositif (37) de commande d'image complète, une première sortie servant à fournir le signal de données de niveau bas lorsque les données de commutation stockées dans le tampon sont en deçà d'un niveau prédéterminé inférieur, une deuxième sortie servant à fournir un signal de tampon plein lorsque les données de commutation stockées dans le tampon sont au-delà d'un niveau prédéterminé supérieur, et une troisième sortie servant à fournir les données de commutation qui y sont stockées pour faire commuter les pixels d'un dispositif d'affichage (23).
  2. Dispositif (10) de commande de dispositif d'affichage selon la revendication 1, où le nombre prédéterminé d'intensités d'affichage de pixels est donné par 2N lorsque les données d'intensité de pixels comprennent N bits.
  3. Dispositif (10) de commande de dispositif d'affichage selon la revendication 1, où la fréquence des signaux de synchronisation d'image complète est proportionnelle au nombre d'intensités d'affichage de pixels.
  4. Dispositif (10) de commande de dispositif d'affichage selon la revendication 1, comprenant en outre des registres de commande (31) couplés au dispositif (33) de commande de DMA afin de recevoir des informations de commande qui commandent le fonctionnement du dispositif (10) de commande d'affichage et de fournir au moins certaines des informations de commande au dispositif (33) de commande de DMA afin de commander le transfert des données d'intensité de pixels au dispositif (37) de commande d'image complète.
  5. Procédé à utiliser dans un dispositif de commande pour dispositif d'affichage à cristal liquide (LCD), comprenant les opérations suivantes :
    a) recevoir des données d'intensité de pixels relatives à au moins un pixel présent sur le dispositif d'affichage en fonction d'un signal de données de niveau bas ;
    b) réduire la réception des données d'intensité de pixels relatives au ou aux pixels se trouvant sur le dispositif d'affichage en fonction d'un signal de tampon plein ;
    c) recevoir un signal de synchronisation d'image complète ;
    d) produire des données de commutation relatives au ou aux pixels en fonction des données d'intensité de pixels ;
    e) stocker les données de commutation dans un tampon de données d'affichage en fonction du signal de synchronisation d'image complète ; et
    f) fournir les données de commutation stockées dans le tampon de données d'affichage afin de faire commuter les pixels du dispositif d'affichage ;
    g) produire le signal de données de niveau bas lorsque les données de commutation stockées dans le tampon sont en deçà d'un niveau prédéterminé inférieur ; et
    h) produire le signal de tampon plein lorsque les données de commutation stockées dans le tampon sont au-delà d'un niveau prédéterminé supérieur.
EP19980121762 1997-11-26 1998-11-16 Circuit de command d'affichage à cristaux liquides avec commande des sous trames Expired - Lifetime EP0919982B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG4104097 1997-11-26
SG9741040 1997-11-26

Publications (2)

Publication Number Publication Date
EP0919982A1 EP0919982A1 (fr) 1999-06-02
EP0919982B1 true EP0919982B1 (fr) 2002-08-21

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DE (1) DE69807304T2 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9024978D0 (en) * 1990-11-16 1991-01-02 Rank Cintel Ltd Digital mirror spatial light modulator
GB2251511A (en) * 1991-01-04 1992-07-08 Rank Brimar Ltd Display device.
CA2137723C (fr) * 1993-12-14 1996-11-26 Canon Kabushiki Kaisha Dispositif d'affichage
US5900886A (en) * 1995-05-26 1999-05-04 National Semiconductor Corporation Display controller capable of accessing an external memory for gray scale modulation data
CA2185830A1 (fr) * 1995-09-27 1997-03-28 Donald B. Doherty Optimisation de configurations de modulation d'impulsions en duree pour modulateur de lumiere spatial

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EP0919982A1 (fr) 1999-06-02
DE69807304T2 (de) 2003-04-10
DE69807304D1 (de) 2002-09-26

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