EP0917736A1

EP0917736A1 - Led-array in a matrix structure

Info

Publication number: EP0917736A1
Application number: EP97936580A
Authority: EP
Inventors: Ernst Nirschl; Walter Wegleiter
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1996-08-07
Filing date: 1997-07-31
Publication date: 1999-05-26
Also published as: WO1998006134A1; CN1231769A; JP2000516035A; DE19631907A1

Abstract

The invention concerns an LED-array mounted on a semiconductor substrate which is particularly suitable for using in printers and enables easy individual control of the LED's. To this end, the LED's are connected by an electrical layer which is situated on the semiconductor and divided into conductors in columns. Serial control occurs through an electroconductive layer (12, 13) which is situated in the semiconductor substrate and divided into individual conductors by trenches (10).

Description

description

LED array in matrix arrangement

The invention relates to an LED array with a plurality of rows and _S columns, of LEDs on a semiconductor substrate, the LEDs being individually controllable and for this purpose a common electrical connection via a first conductive layer in the semiconductor substrate.

The use of LEDs (Light E itting Diode), also called luminescent diodes, in matrix arrangements is widespread. Such LED arrays can be found, for example, in LED screens and LED printer applications. The LEDs are produced on a semiconductor substrate and a common electrical connection is implemented via a conductive layer in the semiconductor substrate. In order to be able to control the LEDs separately, each LED is also connected individually with a bond connection. A large number of wire bond connections are therefore required for this technology, which leads to extreme demands on the LED contacts and the bond technology. These difficulties also limit the yield.

The invention is based on the objective of creating an LED array on a semiconductor substrate of the type mentioned at the outset, which manages with the smallest possible number of bond connections and is particularly easy to produce.

The object is achieved in that an at least semi-insulating layer is arranged below the first conductive layer in the semiconductor substrate, the first conductive layer is interrupted by trenches in such a way that the trenches extend to the at least semi-insulating layer such that the first conductive layer underneath Formation of conductor tracks in longitudinal strips for row-wise electrical connection of the LEDs is divided that each conductor track of the first conductive Layer is connected to an electrical connection contact, so that for the column-wise connection of the LEDs there is a second electrically conductive layer running on the semiconductor substrate, which is subdivided into transverse strips to form further separate conductor tracks, that between the second electrically conductive one running on the semiconductor substrate Layer and the first conductive layer in the semiconductor substrate, an insulating layer is arranged.

The basic idea of the invention is therefore to enable individual LEDs to be controlled by two interconnect levels. The one below the conductor track level is divided into the required individual tracks by trench isolation. In this way, the number of bond connections required is greatly reduced and an LED array with particularly small dimensions is created.

The LED array is preferably designed such that the first conductive layer in the semiconductor substrate forms p-contacts for the LEDs and the second conductive layer on the semiconductor substrate forms n-contacts for the LEDs. This assignment can be realized particularly easily by the properties of the layers used in the semiconductor.

The second conductive layer on the semiconductor substrate is preferably metallic, since on the one hand a metallization lying on the semiconductor substrate is easy to produce and on the other hand can be used particularly advantageously as an n-contact. The insulating layer between the conductive layer on the semiconductor substrate and the first conductive layer in the semiconductor substrate is preferably formed as an oxide layer. A1 ₂ 0 _{3 is} used for this purpose, for example. As an alternative to this, Si3 ₄ can also be used, for example.

In a preferred embodiment, the semiconductor substrate is on gallium arsenide (GaAs), the second conductive layer in the semiconductor substrate is p-doped GaAs and the at least semi-iso- layer undoped semi-insulating GaAs. In principle, there is also the possibility of designing the LED array using silicon technology.

The trenches for separating the second conductive layer in the semiconductor substrate are preferably produced using a separation etch. The subsequently generated insulating layer between the conductive layers follows the course of the trenches. The second conductive layer on the semiconductor substrate can also follow the course of the trenches, but it is preferred to fill the trenches with a filling technique and to execute the second conductive layer over the trenches.

In a preferred development of the invention, the connection contacts of the first conductive layer in the semiconductor are produced using a via-hole technique. As a result, any number of connections can be made via the back of the chip. The connections can be made on one side to the LED side either via the rear or via parallel electrical connections. In another development of the invention, the at least semi-insulating layer is produced using buried isolation layer technology.

The LED arrays according to the invention can be used for screens and a large number of other applications. A particularly preferred use of the LED arrays according to the invention is, however, use in an LED printer with two rows of LEDs, the rows forming a print line. The two rows of LEDs are preferably arranged offset to one another in order to compensate for the geometrical spacing of the LEDs in a row and to be able to produce a continuous pressure line. The two connection contacts per LED pair required for the two rows are preferably arranged on opposite sides of an LED array, since in this way a particularly simple routing of the connection contacts is possible. In this application, the number of wire bond connections required is reduced by 50% + 2 wire bond connections.

The invention is explained in more detail below on the basis of four exemplary embodiments. The schematic representations show in detail in:

1A shows a plan view of an LED array according to the invention produced with a separation etching according to a first example;

Fig. 1B is a cross section through the LED array according to ^'Fig. 1A;

2A shows a plan view of an LED array according to the invention produced with a filling technology according to a second example;

Fig. 2B shows a cross section through the LED array

Fig. 2A;

3A shows a plan view of a LED according to the invention manufactured using a via-hole technique

Array according to a third example;

Fig. 3B shows a cross section through the LED array

Fig. 3A;

4A shows a plan view of an LED array produced using a buried isolation layer technology according to a fourth example, and

FIG. 4B is a cross-sectional view of the LED array according ^~~ Fig. 4A.

CORRECTED SHEET (RULE 91) ISA / EP 1A, LEDs 1 to 6 are shown, the LEDs 1, 3 and 5 forming a first row and the LEDs 2, 4 and 6 forming a second row. Adjacent LEDs of the parallel rows are each connected by a common n-type metallization, which has an n-type contact 7 at one end. Furthermore, p-connection contacts 8 and 9 are provided, which are arranged on opposite sides of the LED array. A potential A becomes the first row of LEDs (LED 1, LED 3, LED 5) via the p-connector 8 and a potential B becomes the second row of LEDs (LED 2, LED 4) via the second p-connector 9 , LED 6).

FIG. 1B shows a cross section along a line through LEDs 1 and 2 of the LED array shown in FIG. 1A. A conductive layer, which consists of p-doped GaAs, is arranged on a semi-insulating GaAs layer 14. A trench 10 separates the p-doped GaAs layer into two regions, the p-doped GaAs layer 12 being at a potential A and the p-doped GaAs layer 13 being at a potential B. Above the p-doped GaAs layer are n-doped GaAs regions 15 which form pn junctions with the p-doped GaAs layer and which form the LEDs 1 and 2. A metal layer 16, which ends in the n-contact 7, contacts the LEDs 1 and 2 and follows the structures of the trench 10. As shown in FIG. 1A, the connection of the LEDs 1 and 2 is electrical from that of the LEDs 3 and 4 isolated. The metal layer 16 is separated from the underlying p-doped GaAs layer by an oxide layer 11. As a result, the contact takes place exclusively at the LEDs 1 and 2. The p-terminal contact 8 serves to apply a potential A to the p-doped GaAs region 12. The p-terminal contact 9 serves to apply a potential B to the p-doped GaAs - Area 13.

To produce this LED array, a p-doped GaAs is first epitaxially placed on the semi-insulating GaAs layer 14.

CORRECTED SHEET (RULE 91) ISA / EP Layer 12, 13 and then an n-doped GaAs layer 15 grew. This produces a pn junction in situ, which is used to form LEDs 1 and 2. In a first etching step, the LEDs 1 and 2 are separated, a separation etching being carried out into the p-doped GaAs layer 12, 13, which is also called the epitaxial layer. In the second etching step, the trench 10 is produced by separating the p-doped epitaxial layer and thus producing two separate potential connections 12 and 13 for the two rows of LEDs. An insulating layer is applied thereon, which can consist, for example, of aluminum oxide (A1.0 ₃ ) or silicon nitride (Si ₃ N ₄ ). An n-metallization 16 is then applied, with which two adjacent LEDs are contacted.

FIGS. 2A and 2B show a top view of an LED array which is produced using separation etching and filling technology. Insofar as the same reference symbols are used here and in the following as in FIGS. 1A and 1B, the meaning is analogous to the reference symbols used in FIGS. 1A and 1B. In contrast to the embodiment shown in FIGS. 1A and 1B, a filling technique was first carried out here in the trench 10 after the oxide deposition, the trench having been filled with a filler 17, so that the metallization and structuring of the metal layer 16 to form the columns Contacts is particularly easy to carry out. In addition, during the etching of the n-doped GaAs layer 15 to form the LEDs 1 and 2, a region 18 has also been preserved on which the n-contact 7 is formed. As a result, the connection contact 7 with the LEDs 1 and 2 is at the same level. The resulting small trench 19 is also filled with the backfill technology, so that the n-metallization is performed on one level over its entire length. The metallization also ends in the region of the LEDs 2, 4 and 6 and does not extend beyond them, as is the case, for example, in the embodiment described in FIGS. 1A and 1B.

CORRECTED SHEET (RULE 91)

ISA / EP In the exemplary embodiments shown in FIGS. 1A to 2B, the p-terminal contacts 8 and 9 are arranged in a plane on opposite sides of the LED array and in direct contact with the underlying conductive layer 12, 13. Another form of contacting, in particular when used of an array with more than two rows of LEDs is necessary, a contact hole technique (via-hole technique) shown in FIG. 3A. The p-terminal contacts 8 and 9 are arranged on the same side of the LED array, but at different levels. The p-terminal contact 9 for the potential B is guided by means of a via-hole technique through a via-hole 20 through the semi-insulating GaAs layer 14 and is on the back of the semiconductor substrate with an electrical layer 21 or path to the p-doped GaAs Layer 13 performed. The electrically conductive layer 21 on the back of the chip is protected by a back passivation 25 made of aluminum oxide or silicon nitride. With a second hole 22, the electrical conductor is guided through the semi-insulating GaAs layer 14 into an additionally p'-doped GaAs layer 23, 24. This is in direct connection with the p-doped GaAs layer 13. The additional p ⁺ -doped GaAs layer 24 is introduced for better contact with the electrical conductor 21 via the via-hole 22 and is exactly like the p-doped GaAs Layer 13 interrupted by trench 10. The p ^* -doped GaAs layer 23 is at the potential A and the p "-doped GaAs layer 24 is at the potential B. If several rows of LEDs are provided, different electrically conductive ones must be parallel to each other on the back of the chip Lanes 21 are produced which each contact the corresponding row of LEDs via via-holes In addition to the p-connection contact 9 for the potential B, a number of further p-connection contacts are then necessary on the semi-insulating GaAs 14. Alternatively, the connection contacts could be used can also be created directly through the via holes on the back of the chip.

Another embodiment of the LED array according to the invention is shown in FIGS. 4A and 4B. The min-

CORRECTED SHEET (RULE 91)

ISA / EP least semi-insulating GaAs layer formed as a buried insulation layer and not as a substrate as in the previous examples. Here, a p-doped GaAs substrate 26 is used, on which an undoped semi-insulating GaAε layer 14 is grown epitaxially. This is followed in the usual way by a p- or p ⁺ -doped GaAs layer 12, 13 and an n-doped GaAs layer 15. These layers are also grown epitaxially. As already described above, there is an etching to separate the LEDs and LED rows and a trench etching, which must extend at least into the semi-insulating GaAs layer 13 and in the exemplary embodiment shown even into the p-doped GaAs substrate 26 enough. The semi-insulating GaAs layer 13 has been produced here as a buried insulation layer. The p-terminal contact 8 contacts the p ⁺ -doped GaAs layer 12 and thus forms the p-contact for the LED 1. The p-terminal contact 9 for the potential B is at a lower level directly on the p-doped GaAs substrate 26 arranged, which serves as a conductor and makes contact with the LED 2. This takes place via a p-doped diffusion region 27, which connects the p-doped GaAs substrate 26 and the p ⁺ -doped GaAs layer 13 and thereby bridges the semi-insulating GaAs layer 14.

CORRECTED SHEET (RULE 91)

ISA / EP Reference list

1 to 6 LEDs

7 n connector

8 p connection contact (potential A)

9 p-connection contact (potential B)

10 trench 11 oxide layer

12 p-doped GaAs layer (potential A)

13 p-doped GaAs layer (potential B)

14 semi-insulating GaAs layer

15 n-doped GaAs layer 16 metal layer

17 filling material

18 Area under n connection contact

19 small trench

20 Via-hole 21 electrically conductive track

22 via-hole

23 p ⁺ -doped GaAs layer (potential A)

24 p ⁺ -doped GaAs layer (potential B)

25 rear passivation 26 p-doped GaAs substrate

27 p-doped diffusion region

Claims

claims

1. LED array with several rows and columns of LEDs on a semiconductor substrate, the LEDs (1, 2,... 6) being individually controllable and for this purpose an electrically conductive connection via a first conductive layer in the semiconductor substrate, characterized in that that an at least semi-insulating layer is arranged below the first conductive layer in the semiconductor substrate, that the first conductive layer is interrupted by trenches (10) in such a way that the trenches (10) extend to the at least semi-insulating layer such that the first conductive layer Layer with the formation of separate conductor tracks in longitudinal strips for rows of electrical connection of the LEDs (1, 3, 5; 2, 4, 6) is divided so that each conductor track of the first conductive layer is connected to a connection contact (8, 9) that for column-wise connection (1, 2, 3, 4; 5, 6) of the LEDs, there is a second electrically conductive layer running on the semiconductor substrate s, which is subdivided into transverse strips to form further separate conductor tracks, that an insulating layer is provided below the second conductive layer and above the first conductive layer.

2. LED array according to claim 1, characterized in that the first conductive layer in the semiconductor substrate forms p-contacts for the LEDs (1 to 6) and that the second conductive layer on the semiconductor substrate n-contacts for the LEDs (1 to 6) forms.

3. LED array according to claim 1 or 2, so that the second conductive layer on the semiconductor substrate is formed by a metal layer (16).

4. LED array according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the insulating layer is an oxide layer (11).

5. LED array according to one of the preceding claims, that the second conductive layer is formed by p-doped GaAs (12, 13).

6. LED array according to any one of the preceding claims, that the at least semi-insulating layer is formed from a semi-insulating GaAs layer (14).

7. LED array according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the trenches (10) are made with a separation etching.

8. LED array according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the insulating layer is adapted in its course to the trench (10).

9. LED array according to one of the preceding claims, characterized in that the trenches (10) are filled with a filling technique.

10. LED array according to one of the preceding claims, that the connection contacts (8, 9) of the first conductive layer in the semiconductor are produced using a contact hole technique.

11. LED array according to one of the preceding claims, that the at least semi-insulating layer is produced using buried insulation layer technology.

12. LED array according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the LED array is used for an LED printer with two rows of LEDs.

13. LED array according to claim 12, so that the two rows of LEDs are arranged offset to one another in the longitudinal direction.

14. LED array according to one of claims 12 or 13, d a d u r c h g e k e n n z e i c h n e t that two connection contacts (8, 9) are provided and that the connection contacts are arranged on opposite sides of the LED array.