EP0892350A3 - Procédé de replacement redondant dans un dispositif de mémoire - Google Patents

Procédé de replacement redondant dans un dispositif de mémoire Download PDF

Info

Publication number
EP0892350A3
EP0892350A3 EP98303690A EP98303690A EP0892350A3 EP 0892350 A3 EP0892350 A3 EP 0892350A3 EP 98303690 A EP98303690 A EP 98303690A EP 98303690 A EP98303690 A EP 98303690A EP 0892350 A3 EP0892350 A3 EP 0892350A3
Authority
EP
European Patent Office
Prior art keywords
domain
domains
redundancy
fault
faults
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP98303690A
Other languages
German (de)
English (en)
Other versions
EP0892350B1 (fr
EP0892350A2 (fr
Inventor
Toshiaki Kirihata
Gabriel Daniel
Jean-Marc Dortu
Karl-Peter Pfefferl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Publication of EP0892350A2 publication Critical patent/EP0892350A2/fr
Publication of EP0892350A3 publication Critical patent/EP0892350A3/fr
Application granted granted Critical
Publication of EP0892350B1 publication Critical patent/EP0892350B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/804—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout to prevent clustered faults
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme
EP98303690A 1997-07-16 1998-05-12 Procédé de replacement redondant dans un dispositif de mémoire Expired - Lifetime EP0892350B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US895249 1997-07-16
US08/895,249 US5881003A (en) 1997-07-16 1997-07-16 Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration

Publications (3)

Publication Number Publication Date
EP0892350A2 EP0892350A2 (fr) 1999-01-20
EP0892350A3 true EP0892350A3 (fr) 2000-02-02
EP0892350B1 EP0892350B1 (fr) 2003-02-05

Family

ID=25404214

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98303690A Expired - Lifetime EP0892350B1 (fr) 1997-07-16 1998-05-12 Procédé de replacement redondant dans un dispositif de mémoire

Country Status (6)

Country Link
US (1) US5881003A (fr)
EP (1) EP0892350B1 (fr)
JP (1) JP3850988B2 (fr)
KR (1) KR100305936B1 (fr)
DE (1) DE69811155T2 (fr)
TW (1) TW410288B (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5970000A (en) * 1998-02-02 1999-10-19 International Business Machines Corporation Repairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domains
US6018483A (en) * 1998-12-10 2000-01-25 Siemens Aktiengesellschaft Distributed block redundancy for memory devices
US6101138A (en) * 1999-07-22 2000-08-08 Eton Technology, Inc. Area efficient global row redundancy scheme for DRAM
US6484271B1 (en) 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6243306B1 (en) 2000-07-19 2001-06-05 International Business Machines Corporation Defect management engine for generating a unified address to access memory cells in a primary and a redundancy memory array
US6901498B2 (en) * 2002-12-09 2005-05-31 Sandisk Corporation Zone boundary adjustment for defects in non-volatile memories
TWI262504B (en) * 2003-04-15 2006-09-21 Ibm Dynamic semiconductor memory device
US9017374B2 (en) * 2004-04-09 2015-04-28 Cardiva Medical, Inc. Device and method for sealing blood vessels
US7145816B2 (en) * 2004-08-16 2006-12-05 Micron Technology, Inc. Using redundant memory for extra features
JP5137408B2 (ja) * 2007-02-05 2013-02-06 パナソニック株式会社 電気ヒューズ回路
US8879295B1 (en) 2013-08-05 2014-11-04 International Business Machines Corporation Electronic circuit for remapping faulty memory arrays of variable size
US9343185B2 (en) 2013-09-26 2016-05-17 International Business Machines Corporation Electronic circuit for fitting a virtual address range to a physical memory containing faulty address
US10141065B1 (en) * 2017-08-29 2018-11-27 Cypress Semiconductor Corporation Row redundancy with distributed sectors
KR102640830B1 (ko) 2022-04-22 2024-02-23 염선해 워터젯 가공에 사용된 연마재의 대용량 재생 시스템 및 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465808A1 (fr) * 1990-06-19 1992-01-15 Texas Instruments Incorporated Schéma de redondance associatif de DRAM avec grandeur de groupe variable
EP0660237A2 (fr) * 1993-12-22 1995-06-28 Hitachi, Ltd. Dispositif de mémoire à semi-conducteur à réseau de cellules de mémoire de réserve

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831279B2 (ja) * 1990-12-20 1996-03-27 インターナショナル・ビジネス・マシーンズ・コーポレイション 冗長システム
US5295101A (en) * 1992-01-31 1994-03-15 Texas Instruments Incorporated Array block level redundancy with steering logic
JP3040625B2 (ja) * 1992-02-07 2000-05-15 松下電器産業株式会社 半導体記憶装置
EP0636258B1 (fr) * 1992-04-16 1996-03-27 Siemens Aktiengesellschaft Memoire a semi-conducteurs integre a redondance
US5491664A (en) * 1993-09-27 1996-02-13 Cypress Semiconductor Corporation Flexibilitiy for column redundancy in a divided array architecture
KR960008825B1 (en) * 1993-11-18 1996-07-05 Samsung Electronics Co Ltd Row redundancy circuit and method of semiconductor memory device with double row decoder
JP2570203B2 (ja) * 1994-11-22 1997-01-08 日本電気株式会社 半導体記憶装置
US5513144A (en) * 1995-02-13 1996-04-30 Micron Technology, Inc. On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465808A1 (fr) * 1990-06-19 1992-01-15 Texas Instruments Incorporated Schéma de redondance associatif de DRAM avec grandeur de groupe variable
EP0660237A2 (fr) * 1993-12-22 1995-06-28 Hitachi, Ltd. Dispositif de mémoire à semi-conducteur à réseau de cellules de mémoire de réserve

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KIRIHATA T ET AL: "FAULT-TOLERANT DESIGNS FOR 256 MB DRAM", IEICE TRANSACTIONS ON ELECTRONICS,JP,INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, vol. E79-C, no. 7, pages 969-977, XP000632352, ISSN: 0916-8524 *

Also Published As

Publication number Publication date
EP0892350B1 (fr) 2003-02-05
EP0892350A2 (fr) 1999-01-20
TW410288B (en) 2000-11-01
JP3850988B2 (ja) 2006-11-29
KR100305936B1 (ko) 2001-11-05
DE69811155D1 (de) 2003-03-13
US5881003A (en) 1999-03-09
JPH1196799A (ja) 1999-04-09
DE69811155T2 (de) 2003-10-23
KR19990013942A (ko) 1999-02-25

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