Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/50—Overload detection or protection within a single switching element
  • H04L49/505—Corrective measures
  • H04L49/506—Backpressure
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/30—Peripheral units, e.g. input or output ports
  • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/50—Overload detection or protection within a single switching element
  • H04L49/501—Overload detection
  • H04L49/503—Policing
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5629—Admission control
  • H04L2012/5631—Resource management and allocation
  • H04L2012/5632—Bandwidth allocation
  • H04L2012/5635—Backpressure, e.g. for ABR
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5629—Admission control
  • H04L2012/5631—Resource management and allocation
  • H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
  • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
  • H04L2012/5647—Cell loss
  • H04L2012/5648—Packet discarding, e.g. EPD, PTD
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
  • H04L2012/5681—Buffer or queue management
  • H04L2012/5682—Threshold; Watermark
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/30—Peripheral units, e.g. input or output ports
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/30—Peripheral units, e.g. input or output ports
  • H04L49/3009—Header conversion, routing tables or routing tags

Definitions

• This invention relates to an Asynchronous Transfer Mode (ATM) network switch having a buffer for buffering the flow of ATM cells and a congestion control mechanism associated there ⁇ with.
• ATM Asynchronous Transfer Mode
• the invention also relates to a method of controlling congestion in an ATM network switch.
• ATM cells may either carry individual data or be part of a segmented larger data packet in accordance with AAL5 (ATM Adaptation Layer 5) . Indi ⁇ vidual data cells may be discarded at random when a switch is congested.
• AAL5 ATM Adaptation Layer 5
• all ATM cells which comprise a single packet must be delivered through the network to the destination without loss. If a single cell is lost within a packet, the destination will not be able to reconstitute (or reassemble) the packet, and all the other cells received within that packet will be worthless and must be discarded. It will be noted that packets may comprise dozens, or even hundreds of cells.
• Intelligent cell discard schemes detect the end of a packet by reading the 3-bit Payload Type (PT) field value of 0X1 (hexadec ⁇ imal 1) in the ATM cell header, and then setting a flag.
• PT Payload Type
• the level of congestion in the switch is assessed to determine whether there is capacity to accept the entire packet without cell loss.
• a flag is then set to indicate either accep ⁇ tance of the whole packet, or that the whole packet is to be discarded. In this way, individual cells within a packet should not be discarded.
• Switches become congested when the total input bandwidth exceeds the output bandwidth at a particular switch queuing point.
• congestion may occur on the receive side (input to the switch fabric) if the switch fabric is congested and will not allow further cells to be input. It may also occur on the transmit side (output from the switch fabric) where cells arrive faster than they can be transmitted.
• An ATM network switch includes a buffer for buffering the flow of ATM cells and a congestion control mechanism which includes means for allocating buffer space to each virtual connection and means for determining the amount of buffer space available for each virtual connection
• the congestion control mechanism includes means for storing a predetermined value Max, representing the maximum permissible number of ATM cells which may be stored in the buffer for each virtual connec ⁇ tion (VC) through the switch, and a predetermined offset value K, which determines the maximum occupancy of the buffer for the VC; means responsive to the arrival of a new ATM cell at the buffer means for determining the total number of cells TSC currently stored in the buffer and the number of cells VcCnt stored for the respective VC for the cell; means for determining the remaining capacity BS of the buffer; calculating means for calculating an adjusted value Max' of Max in accordance with the formula:
• BS+KJ means for comparing Max' with VcCnt and for discarding the cell if VcCnt is greater than or equal to Max' .
• the con ⁇ area control mechanism includes means for storing an EFCI (Explicit Forward Congestion Indication) Threshold value for each virtual connection (VC) through the switch, and a predetermined offset value K, which determines the maximum occupancy of the buffer for the VC; means responsive to the arrival of a new ATM cell at the buffer for determining the total number of cells TSC currently stored in the buffer and the number of cells VcCnt stored for the respective VC for the cell; means for determining the remaining capacity BS of the buffer; calculating means for calculating an adjusted value EFCIThr' of the EFCI Threshold EFCIThr in accordance with the formula:
• the switch includes both of the congestion control mechanisms described above.
• the invention also provides a method of controlling conges ⁇ tion in an ATM network switch having a buffer for buffering the flow of ATM cells therethrough, the method including discarding cells according to the congestion control mechanism described above and setting EFCI bits according to the congestion control mechanism described above.
• Non user data cells are not arranged in packets and may therefore be discarded on an individual basis.
• the congestion control mechanism may be implemented on each side of the switch fabric in a network switch, at each point where congestion may occur.
• the algorithm for discarding cells allocates a maximum number (Max) of stored cell positions in the buffer for each VC, this number being reduced as the buffer fill increases as cells are stored on other connections.
• the offset parameter K which may be positive or negative, can be set to determine the level of buffer fill at which all cells are discarded. The value will be set differently depending on the class of traffic. For low priority traffic classes, such as UBR (Uncommitted Bit Rate) , K may be set to zero, for example, so as not to allow any UBR cells into the buffer when it is half full or more. A negative value of K would cause cell discarding at less than half full.
• UBR Uncommitted Bit Rate
• the Max parameter may, however, be set quite high to allow plenty of buffering when space is available.
• Max may be set lower, to reflect the fact that CBR cells are treated with top priority and are sensitive to transit delay, and hence buffer size.
• the K parameter would be set large to allow CBR cells to be stored even when there is a high level of lower priority traffic.
• the EFCI bit in the cell header may be set by a congested ATM switch as part of an end-to-end flow control mechanism, to slow down the source at times of congestion.
• the EFCI Threshold parameter is configurable for each connection at a predetermined fraction of the maximum level at which discard may occur (typi ⁇ cally this would be 50%) .
• the EFCI test may be performed for each cell arriving in the buffer, and the Payload Type EFCI bit is set for all user data cells when the threshold is exceeded.
• An option to discard CLPl cells (CLP is Cell Loss Priority, and 1 denotes low priority) may also be set per connection when the EFCI level is reached. For AAL5 connections, this feature is disabled for the user data cells. Additional objects and advan ⁇ tages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures. Brief Description of the Drawings
• Figure 1 is a simple diagrammatic representation of a typi ⁇ cal ATM switch
• FIG. 2 is an enlarged diagrammatic view of a slot con ⁇ troller forming part of the switch of Figure 1;
• Figure 3 is a block diagram of the congestion control mech ⁇ anism in slot controller of Figure 2.
• Figure 4 is a flow diagram illustrating the method steps carried out in the congestion control mechanism.
• the ATM network switch illus ⁇ trated is of the type described and claimed in our earlier UK Patent Application No 9507454.8, and has two switch fabrics 14a and 14b, each connected to a plurality of slot controllers lla-f (although only six slot controllers are shown to simplify the diagram, a typical switch may have sixteen slot controllers) .
• Each slot controller has input 12 and output 13 connections to an external data link, and includes, as may be seen from Figure 2, a receiver 21 and a transmitter 22, either or both of which may include a buffer to control the flow of data into or out of the switch.
• the transmitter 22 includes a congestion control mechanism 23 controlling the storage of cells in the buffer 24.
• the congestion control mechanism 23 is described hereinafter in more detail with reference to Figures 3 and 4. Since division is more difficult to execute, the equations
• EFCIThr x (BS + K - TSC) so that the elements can be simply arrived at by additions, multiplications and subtractions, as follows.
• the number of slots left (Buffer Space or BS) in the buffer 24 is first read on arrival of a new cell at the congestion control means 23 and passed via a multiplexer 30 to an adde r/subtracter 31.
• the VC is determined from the cell header, and the offset K associated with that VC is read from a routing table which may be defined in a separate part of the RAM (Random Access Memory) in which the buffer 24 is configured, the offset K being passed via a second multiplexer 32 to the adder/subtracter 31.
• the adder then receives an add signal on line 33 and adds the values together, with the resultant BS + K value being stored in a first register 34.
• the register 34 then passes the BS+K value back to the first multiplexer 30, while the Total Stored Cells (TSC) value is calculated at 29 from the BS and the total capacity TC of the Buffer and passed to the second multiplexer 32.
• the values are passed to the adder/subtracter 31, which carries out an A-B operation to give the result BS+K-TSC, which is held in a second register 35.
• a negative flag is generated by the adder/subtracter 31 and is held in a register 36 for use as hereinafter described.
• Max for the VC is also read from the routing table RAM, and is input to a multiplier 38 in the second stage of the congestion control mechanism (shown in Fig 3b) via a third multiplexer 39, while the value of BS+K-TSC is read from the register 35 to the multiplier 38 via a fourth multiplexer 37.
• the product MAX(BS+K-TSC) is stored in a register 40.
• the EFCI Threshold value is then read from the routing table RAM, and passed via the multiplexer 39 to the multiplier 38, to be multiplied with the BS+K-TSC value, the result being stored in a register 41.
• VcCnt value is read from the routing table RAM and is then passed via multiplexer 37 to the multiplier, and the BS+K value stored in register 34 is fed to the multiplier 38 via multiplexer 39.
• the product VcCnt (BS+K) is passed to a comparator 43, while the values stored in the registers 40 and 41 are read out to the comparator in turn via multiplexer 42.
• the respective one-bit flags indicating whether or not the VcCnt product is less than the other side of the equation are stored in registers 44 and 45.
• the sequence of operation is as follows.
• various control bits are held in the routing table. These are: (1) Enable EFCI setting; (2) Enable CLPl setting; (3) Enable Early Packet Discard (EPD) ; (4) Discard Packet; and (5) First Cell of Packet.
• the discard packet bit is set to 0 and the First Cell of Packet bit is set to 1 to indicate that the next cell to arrive is the first cell of a packet.
• the 3-bit Payload Type field in each cell header have to be considered.
• Bit 2 is set to 0 to signify a user cell
• Bit 1 is the EFCI bit
• bit 0 is set to 1 to indicate end of packet.
• the sequence of opera ⁇ tions described with reference to Figures 3a and 3b is carried out to yield the set of flags as- hereinbefore described. These flags are then considered together with the control bits and payload type in the congestion mechanism. If the negative flag is set, the buffer cannot accommodate the cell, and so it is immediately discarded without further processing, and the next cell is received. Another process runs in parallel with the mechanism described. For each cell, the payload type field is checked to see if the cell is the last in a packet, and if it is, the 1st cell in packet bit is set to 1 so that the next cell arriving is set as the first of a packet.
• bit 2 of the PT field of the cell header is checked to see whether the cell is a user cell. Taking the case first where the cell is not a user cell, for example an Rm cell, the routing table control bit for CLPl Discard is first examined to see whether the cell, if of low priority, can be discarded. If this is not set, the >MAX flag is next examined. If it is set, the cell is discarded, while if the flag is not set, the cell is passed and can enter the buffer. If CLPl discard is set, the next stage is to test whether the cell is of CLPl.
• the _>MAX test as described above, while if the cell is CLPl, the _>EFCIThr test flag is examined. If the threshold is exceeded, the cell is discarded, while if it is not, the >MAX flag is examined, as described.
• the sequence of operations set out on the right-hand side of Figure 4 is then followed. Again, the CLPl discard bit in the routing table for the cell's VC is checked, and if so, the CLP bit is checked. If the VC is not CLPl, the mechanism passes on to the next test, the Early Packet Discard (EPD) Mode test. If the VC is CLPl, the >EFCIThr flag is then examined, and if the threshold is exceeded, the cell is discarded, but otherwise the EPD Mode test follows. If CLPl Discard bit is not set, the mechanism passes direct to the EPD Mode test. The EPD Mode test looks to the routing table to see whether EPD is enabled.
• EPD Early Packet Discard
• the J>MAX flag is examined, and if the value is equalled or exceeded, the cell is discarded, while otherwise the _>EFCIThr flag is next examined. If the threshold is exceeded, the Enable EFCI setting control bit is checked, and if this is set the EFCI bit in the cell header is set to signal that the rate of sending of cells is to be de ⁇ creased; otherwise the cell is passed for admittance to the buffer. If the threshold is not exceeded, the cell is passed without further test.
• the First Cell in Packet control bit in the routing table is checked. If this is not set, indicating that the cell is within a packet, the Discard Packet bit is checked; if this is set, the cell can simply be discarded, while if it is not set, the J ⁇ EFCIThr flag is examined, as de ⁇ scribed in the preceding paragraph. If the cell is the first of a packet, the >MAX flag is checked. If the value is equalled or exceeded, the Discard Packet bit is set in the routing table, so that all the cells for that packet are discarded as described; otherwise the Discard Packet bit is cleared and the >EFCIThr flag is examined as hereinbefore described.

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• 1995
  • 1995-06-05 GB GBGB9511314.8A patent/GB9511314D0/en active Pending
• 1996
  • 1996-06-05 WO PCT/US1996/008907 patent/WO1996039763A1/en not_active Ceased
  • 1996-06-05 CA CA002223680A patent/CA2223680A1/en not_active Abandoned
  • 1996-06-05 EP EP96918094A patent/EP0878073A4/de not_active Withdrawn
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