EP0875882A2 - Multi-scan video timing generator for format conversion - Google Patents
Multi-scan video timing generator for format conversion Download PDFInfo
- Publication number
- EP0875882A2 EP0875882A2 EP98302916A EP98302916A EP0875882A2 EP 0875882 A2 EP0875882 A2 EP 0875882A2 EP 98302916 A EP98302916 A EP 98302916A EP 98302916 A EP98302916 A EP 98302916A EP 0875882 A2 EP0875882 A2 EP 0875882A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- display
- signal
- input
- horizontal
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/005—Adapting incoming signals to the display format of the display terminal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
- G09G5/008—Clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0229—De-interlacing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0435—Change or adaptation of the frame rate of the video stream
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
Abstract
Description
Claims (9)
- A format converter for receiving a digital video input signal characterized by a first viewable display resolution, pixel rate and line rate, and in response generating a digital video output signal for viewing on a display characterized by a second viewable display resolution, pixel rate and line rate, said format converter comprising:programming interface means for receiving operating mode information indicative of said first and second viewable display resolutions, pixel rates and line rates;memory means for storing said digital video input signal;display processor means for retrieving said digital video input signal from said memory means, selectively de-interlacing, filtering and scaling said digital video input signal, and in response generating said digital video output signal; anddisplay timing controller means for deriving synchronization and control information from said digital video input signal based on said operating mode information received by said programming interface means, and in response controlling operation of said display processor means to generate said digital video output signal for display at said second viewable display resolution, pixel rate and line rate.
- The format converter of claim 1, wherein said display timing controller further comprises:clock generation means for generating a display main clock signal;a lock event controller for generating a lock event signal at a predetermined instant of each frame of said digital video input signal;display synchronizer means for generating a display horizontal lock event signal and a display vertical lock event signal for controlling synchronization between said digital video input signal and said digital video output signal based on said lock event signal and said operating mode information; anddisplay timing generator means for generating timing signals synchronized to said horizontal and vertical lock event signals to control said display processor means in accordance with said operating mode information.
- The format converter of claim 2, wherein said clock generation means further comprises:a free running clock for generating a free running clock signal which is not synchronized to said digital input video signal;phase lock loop means for receiving an input clock signal derived from said digital input video signal and in response generating a synthesized clock signal which is a ratio multiple of said input clock signal; anda clock selector for selecting one of said free running clock signal or said synthesized clock signal for output as a display main clock signal.
- The format converter of claim 3, wherein said lock event controller further comprises:a programmable control register for generating a predetermined horizontal lock event value and a predetermined vertical lock event value based on said operating mode information;a horizontal pixel event counter for counting successive cycles of said input clock signal relative to each of a succession of horizontal synchronization pulses of said digital input video signal and in response generating a horizontal pixel count value;a horizontal pixel event comparator for comparing said horizontal pixel count value with said predetermined horizontal lock event value, and when said horizontal pixel count value is equal to said predetermined horizontal lock event value then generating a horizontal lock event pulse;a vertical line counter for counting successive ones of said horizontal synchronization pulses relative to a succession of input vertical synchronization pulses of said digital input video signal and in response generating a vertical line count value;a vertical line event comparator for comparing said vertical line count value with said predetermined vertical lock event value, and when said vertical line count value is equal to said predetermined vertical lock event value then generating a vertical lock event pulse;a lock event generator for generating a lock event pulse when said horizontal lock event pulse and said vertical lock event pulse coincide; anda lock event selector for selecting one of either a frame synchronization signal derived from said digital input video signal, said input clock signal, or said lock event pulse for output as said lock event signal based on said operating mode information.
- The format converter of claim 4, wherein said display synchronizer further comprises circuitry for receiving said input clock signal, said display main clock signal, said lock event signal and said operating mode information, and in response generating said display horizontal and vertical lock event signals and a run enable signal wherein:(i) in the event said operating mode information indicates a free run operating mode, the display horizontal and vertical lock event signals are suppressed so that there is no synchronization between said digital input video signal and said digital output video signal, and said run enable signal is synchronized to said display main clock signal for enabling and disabling said display timing generator;(ii) in the event said operating mode indicates a clock synchronized mode of operation, the display horizontal and vertical lock event signals are synchronized to said lock event signal initially at start up, and said run enable signal is synchronized to said display main clock signal thereafter for enabling and disabling said display timing generator;(iii) in the event said operating mode indicates a frame synchronized mode of operation, the display horizontal and vertical lock event signals are synchronized to said lock event signal on a per frame basis of the digital input video signal, and said run enable signal is synchronized to said display main clock signal for enabling and disabling said display timing generator; and(iv) in the event said operating mode indicates a line synchronized mode of operation, the display horizontal and vertical lock event signals are synchronized to said lock event signal on a per line and per frame basis of the digital input video signal, and said run enable signal is synchronized to said display main clock signal for enabling and disabling said display timing generator.
- The format converter of claim 5 wherein said display timing generator further comprises:a horizontal controller for receiving said display main clock signal, said operating mode information, said horizontal lock event signal and said run enable signal and in response generating a horizontal end of frame signal for indicating transitions between successive lines of said digital output video signal, a display horizontal synchronization signal for driving said display, and an output enable signal for enabling said display; anda vertical controller for receiving said display main clock signal, said operating mode information, said vertical lock event signal, said run enable signal and said horizontal end of frame signal and in response generating a display vertical synchronization signal for driving said display, and a display vertical enable signal for application to sad horizontal controller in connection with generating said output enable signal.
- The format converter of claim 1 wherein said digital input video signal is an interlaced signal and said digital output video signal is a progressive scan signal.
- The format converter of claim 1 wherein said digital input video signal is a progressive scan signal and said digital output video signal is also a progressive scan signal.
- A display timing controller for deriving synchronization and control information from a digital video input signal based and in response controlling operation of said display processor to generate a digital video output signal for display at a viewable display resolution, pixel rate and line rate different from that of said digital video input signal, comprising:clock generation means for generating a display main clock signal;a lock event controller for generating a lock event signal at a predetermined instant of each frame of said digital video input signal;display synchronizer means for generating a display horizontal lock event signal and a display vertical lock event signal for controlling synchronization between said digital video input signal and said digital video output signal based on said lock event signal; anddisplay timing generator means for generating timing signals synchronized to said horizontal and vertical lock event signals to control said display processor to generate said digital video output signal for display at said viewable display resolution, pixel rate and line rate.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/839,745 US6177922B1 (en) | 1997-04-15 | 1997-04-15 | Multi-scan video timing generator for format conversion |
US839745 | 1997-04-15 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0875882A2 true EP0875882A2 (en) | 1998-11-04 |
EP0875882A3 EP0875882A3 (en) | 1998-12-09 |
EP0875882B1 EP0875882B1 (en) | 2007-11-21 |
Family
ID=25280530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98302916A Expired - Lifetime EP0875882B1 (en) | 1997-04-15 | 1998-04-15 | Multi-scan video timing generator for format conversion |
Country Status (6)
Country | Link |
---|---|
US (1) | US6177922B1 (en) |
EP (1) | EP0875882B1 (en) |
JP (1) | JP4286928B2 (en) |
KR (1) | KR100583445B1 (en) |
DE (1) | DE69838741T2 (en) |
TW (1) | TW369756B (en) |
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Also Published As
Publication number | Publication date |
---|---|
JP4286928B2 (en) | 2009-07-01 |
US6177922B1 (en) | 2001-01-23 |
EP0875882A3 (en) | 1998-12-09 |
TW369756B (en) | 1999-09-11 |
JPH10319928A (en) | 1998-12-04 |
KR100583445B1 (en) | 2006-11-30 |
KR19980081437A (en) | 1998-11-25 |
DE69838741T2 (en) | 2008-10-30 |
DE69838741D1 (en) | 2008-01-03 |
EP0875882B1 (en) | 2007-11-21 |
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