TWI444047B - Deblockings filter for video decoding , video decoders and graphic processing units - Google Patents

Description

Deblocking filter, video decoder and graph for video decoding Shape processing unit

The present invention relates to image compression and decompression, and more particularly to a graphics processing unit having image compression and decompression features.

Personal computers and consumer electronics are used in a variety of entertainment products. These entertainment items can be broadly classified into two categories: those that use computer-generated graphics, such as computer games, and those that use compressed video streams, such as pre-recorded programs to digital video discs ( On DVD), or from a cable or satellite industry, digital programming to a set-top box. The second type also includes a coded analog video stream, such as a digital video recorder (DVR).

Computer graphics are usually generated by a graphics processing unit (GPU). A graphics processing unit is a special type of microprocessor built on computer game consoles and some personal computers. A graphics processing unit is optimized to quickly perform three-dimensional primitive objects, such as triangles, quads, and the like. These basic objects are described by a plurality of vertices, where each vertex has an attribute (eg, a color) and texture can be applied to the base object. The result of the depiction is a two-dimensional array of pixels Pixels), displayed on a computer monitor or monitor.

The encoding and decoding of video streams involves different kinds of operations, such as discrete cosine transform, motion estimation, motion compensation, and deblocking filters. These calculations are typically handled by a general purpose central processing unit (CPU) in conjunction with special hardware logic circuits, such as an application specific integrated circuit (ASIC). Consumers therefore need multiple computing platforms to meet their entertainment needs. There is therefore a need for a single computing platform that can handle computer graphics and video encoding/decoding.

Embodiments disclosed herein provide a system and method for video compression deblocking. An exemplary deblocking filter for video decoding includes: a logic circuit configured to determine whether a pixel of a predetermined pixel group of a plurality of pixel groups reaches a standard; and when the standard is reached, first a logic circuit for pixel filtering of a predetermined pixel group; and arranged to sequentially sequence the remaining pixel groups of the plurality of pixel groups according to a corresponding group of filtering units in a set of taps when the standard is reached Filtered logic circuit.

An exemplary video decoder includes an entropy decoder, a spatial decoder, a combinational logic circuit, and an in-loop deblocking filter. The entropy decoder receives an input encoded bit stream. The spatial decoder receives the output of the entropy decoder and produces a coded picture comprising a plurality of pixels. The combination The logic circuit combines a current picture with a predicted picture to produce a combined picture. The deblocking filter in the loop receives the combined picture. The in-loop deblocking filter includes: a logic circuit configured to filter a predetermined pixel group; and configured to, when the predetermined pixel group reaches a criterion, according to a corresponding group of filtering units in the complex array filtering unit, A logic circuit for filtering each of the remaining pixel groups in a plurality of pixel groups.

An exemplary graphics processing unit includes a main processing interface and a video acceleration unit. The main processing interface receives at least one video acceleration command. The video acceleration unit is configured to use the at least one video acceleration command. The video acceleration unit includes a loop-in-square block effect filter. The in-loop deblocking filter includes: a logic circuit configured to determine whether a pixel of a predetermined pixel group of a plurality of pixel groups reaches a first standard; and is configured to first determine the predetermined pixel group when the first standard is reached a logic circuit for pixel filtering; and configured to, when the first criterion is reached, sequentially filter the remaining pixel groups of the plurality of pixel groups according to a corresponding group of filtering units in a set of taps Logic circuit.

Computing platform for video encoding/decoding

Figure 1 is a block diagram of an exemplary computing platform for graphics and video coding and/or decoding. The system 100 includes a general purpose CPU 110 (hereinafter referred to as a main processor), a graphics processing unit (GPU) 120, a memory 130, and a bus bar 140. Graphics processing unit 120 includes a video acceleration unit (VPU) 150 that can speed up video encoding and/or decoding, as will be described later. Graphics processing unit 120 The video acceleration function is an instruction that can be executed on the graphics processing unit 120.

The software decoder 160 and the video acceleration driver 170 are located in the memory 130, and at least a portion of the decoder 160 and the video acceleration driver 170 are executed on the main processor 110. The decoder 160 can also issue a video acceleration command to the graphics processing unit 120 via a host processor interface 180 provided by the video acceleration driver 170. As such, the system 100 performs video encoding and/or decoding by the host processor software of the graphics processing unit 120 by issuing a video acceleration command, and the graphics processing unit 120 responds to the commands through a portion of the acceleration decoder 160.

In some embodiments, only a small portion of the decoder 160 is executing on the host processor, while most of the decoder 160 is executed by the graphics processing unit 120 with minimal overloading of the driver. In this way, the computationally intensive blocks that are often executed are unloaded to the graphics processing unit 120, while the more complex operations are performed by the main processor 110. In some embodiments, a dense computational function implemented by graphics processing unit 120 includes inloop deblocking filter hardware acceleration logic 400, also known as in-loop square effect filter 400. Or go to the block effect filter 400, which will be described later in conjunction with FIG. Another example of intensive computing functions is to determine the boundary strength (BS) of each filter.

The above structure thus makes the following operations flexible: on the main processor 110, the decoder 160 performs some special functions (such as deblocking or calculation) by executing a shader program on a marcoblock. Boundary strength); or a majority of the decoder 160 is executed on the graphics processing unit 120, utilizing pipeline pipelining and parallelism. In some embodiments in which decoder 160 is executed on graphics processing unit 120, the deblocking process is a thread of synchronization between the various aspects of decoder 160.

Several conventional elements that are not necessary for explaining the video acceleration characteristics of the graphics processing unit 120 and are familiar to those skilled in the memory are omitted in FIG.

Video decoder

Figure 2 is a block diagram of the video decoder 160 in Figure 1. In the particular embodiment illustrated in Figure 2, decoder 160 applies the ITU H.264 video compression specification. However, those skilled in the art will appreciate that the decoder 160 of FIG. 2 is a preliminary representation of a video decoder that also illustrates the operation of other types of decoders similar to H.264, such as SMPTE VC-1. With the MPEG-2 specification. In addition, although shown as part of a graphics processing unit 120, those skilled in the art will appreciate that the portion of the decoder 160 disclosed herein can also be implemented outside of a graphics processing unit, such as a separate logic circuit, Apply a part of an integrated circuit (ASIC), etc.

The input bit stream 205 is first processed by an entropy decoder 210. Entropy coding has the advantage of statistically redundant: some patterns appear more often than others, so the more common ones are represented by shorter codes. Entropy coding includes Huffman coding and run-length encoding. After entropy coding, the capital The material is processed by a spatial decoder 215, which has the advantage that, in fact, adjacent pixels in a pattern are generally identical or related, so that the difference can be encoded. In this exemplary embodiment, spatial decoder 215 includes an inverse quantizer 220 and an inverse discrete cosine transform (IDCT) function 230. The output of the IDCT function 230 can be viewed as a graphic (235) consisting of a number of pixels.

The graphic 235 is processed into smaller sub-blocks, called large squares. The H.264 video compression specification uses a large block size of 16x16 pixels, while other compression specifications can use other sizes. The large blocks in the graphics 235 are combined with the information of the previously decoded graphics items, referred to as inter-inter prediction processing, or combined with the information of other large blocks of the graphics 235, referred to as intra-prediction processing. The input bit stream 205 is decoded by the entropy decoder 205, and inter-picture or intra-picture prediction is applied depending on the type of graphics.

Entropy decoder 210 generates a motion vector 245 output when inter-picture prediction is applied. The motion vector 245 is used for temporary encoding, which has the advantage that, in fact, many pixels will typically have the same value in a series of graphics. The change from one graphic to another is encoded as a motion vector 245. Motion compensation block 250 combines one or more previously decoded graphics 255 with motion vector 245 to produce a predicted graphics (265). When inter-picture prediction is applied, spatial compensation block 270 combines information from adjacent large squares with large squares within graphics 235 to produce a predicted pattern (275).

Combiner 280 adds graphic 235 to the output of mode selector 285. Mode selector 285 uses entropy to decode the bit stream to determine the combiner 280 uses the predicted graphics (265) generated by the motion compensation block 250 or the predicted graphics (275) generated using the spatial compensation block 270.

The encoding process causes artifacts such as discontinuities along the edges of the large squares and discontinuities along the edges of the sub-blocks within the large squares. The result is an "edge" in the decoding frame, which was not originally. The deblocking filter 290 is applied to the combined pattern output by the combiner 280 to remove these edge products. The decoded pattern 295 generated by the deblocking filter is stored for decoding the next pattern.

In conjunction with the discussion of FIG. 1, partial decoder 160 is executed on host processor 110, and decoder 160 also has the advantage of providing video acceleration instructions by graphics processing unit 120. In particular, in some embodiments, deblocking filter 290 uses one or more instructions provided by graphics processing unit 120 to implement filtering using relatively low computational cost.

Deblocking filter

The deblocking filter 290 is a multi-tap filter that adjusts the pixel values of the edges of the sub-blocks based on neighboring pixel values. Different embodiments of the deblocking filter 290 can be used in accordance with the compression specifications implemented by the decoder 160. Each specification uses different filter parameters, such as the size of the sub-block, the number of pixels updated by the filtering operation, and the frequency at which the filter is applied (eg, every N columns or every M rows). In addition, each specification uses a different filter length structure. Those skilled in the art should be aware of multi-cell filters, and the structure of a particular unit will not be discussed here. By the VC-1 specification The block effect filter embodiment will be described in conjunction with FIG. First, the sub-block pixel arrangement of the VC-1 filter will be described in conjunction with Figure 3.

Figure 3 shows two adjacent 4x4 sub-blocks (310, 320), defined as columns R1-R4 and rows C1-C8. The vertical boundary 330 between the two sub-blocks is along lines C4 and C5. The VC-1 filter operates on each 4x4 sub-block. For the leftmost sub-block, the VC-1 filter checks a predetermined group of pixels (P1, P2, P3) in a predetermined column (R3). If the predetermined group of pixels reaches a certain standard, another pixel P4 in the same predetermined column is updated. The standard is determined by the particular set of calculations and comparisons of pixels in the predetermined set. Those skilled in the art will appreciate that these calculations and comparisons can also be a set of taps, and detailed calculations and comparisons will be discussed later in conjunction with FIG. The update value is also based on the operations performed on the pixels in the predetermined group. The VC-1 filter processes the rightmost sub-block in a similar manner, determines whether the pixels P6, P7, P8 meet a criterion, and updates P5 if the criterion is reached. In other words, the VC-1 filter is a predetermined column (R3) of a group of predetermined pixels - edge pixels P4 and P5 - based on the values of other groups of predetermined pixels in the same column, the value of P4 is based on P1, P2, P3, and The value of P5 is based on P6, P7, and P8.

The VC-1 conditionally updates the same group of predetermined pixels of the remaining columns based on the values calculated for the predetermined group of pixels (edge pixels P4, P5) of the predetermined column (R3). As a result, only when P4 and P5 in R3 are updated, P4 in R1 is updated based on P1, P2, and P3 in R1. Similarly, only when P4 and P5 in R3 are updated, P5 in R1 is updated based on P6, P7, and P8 in R1. Columns 2 and 4 are also treated in a similar manner.

On the other hand, some pixels of a pixel in a predetermined third column Filtered or updated when the other pixels in the third column reach a standard. This filter involves performing comparisons and calculations on these other pixels. If the other pixels in the third column reach the standard, the corresponding pixels in the remaining columns are filtered in a similar manner, as described above. Some embodiments of the deblocking filter 290 disclosed herein use a groundbreaking technique to first filter the third column and then filter the other columns. These groundbreaking techniques will be described in more detail in conjunction with Figures 4, 5, and 6A-6D.

Although Figure 3 illustrates the processing of the vertical edges of a column, it will be appreciated by those skilled in the art that the same figure can be rotated by 90 degrees to indicate that the horizontal edges of the line are processed. Those skilled in the art will also appreciate that although VC-1 uses the third column of the four columns as a predetermined column for determining the conditional update of other columns, the principles disclosed herein can be applied to embodiments using other predetermined columns (eg, The first column, the second column, etc.) can also be applied to other embodiments that form different numbers of sub-blocks. Similarly, those skilled in the art will appreciate that although VC-1 checks the value of a group of neighboring pixels to set the value of the pixel to be updated, the principles disclosed herein can be applied to other pixels that have been verified and other pixels have been set. An embodiment. For an example, P2 and P3 can be tested to determine the updated value of P4. As another example, P3 can be set according to the values of P2 and P4.

The video acceleration unit 150 in the graphics processing unit 120 is an in-loop deblocking filter (IDF), for example, a block-effect filter in the loop of the VC-1 specification to implement a hardware acceleration logic circuit. A graphics processing unit instruction implements the hardware acceleration logic circuit, which will be described later. A conventional method of implementing a VC-1 loop deblocking filter is to process each column/row in parallel because the same pixel calculation is performed in each column/row of a sub-block. This conventional method is for two adjacent cycles per cycle. 4x4 sub-block filtering, but requires an enhanced gate count execution. In contrast, the groundbreaking method used by the VC-1 loop-in-blocking filter hardware acceleration logic circuit 400 processes the third column/row of pixels first, and if the pixels meet the required standard, then sequentially process The remaining three columns/rows. This groundbreaking method uses fewer logic gates than the conventional method, which replicates the function of each column/row. The VC-1 loop deblocking filter acceleration logic circuit 400 sequentially samples two adjacent 4x4 sub-blocks per cycle. This longer filtering time coincides with the instruction cycle of the graphics processing unit 120, wherein the faster filtering of the conventional method is in fact faster than the required speed, resulting in wasted logic gates.

Figure 4 is a block diagram of the hard description virtual code of the block-effect filter hardware acceleration logic circuit 400 in the VC-1 loop. Although not using a virtual hardware description language (HDL), such as Verilog and VHDL, a virtual code is used, and those skilled in the art should be familiar with these virtual codes. These individuals should be aware that when described in actual HDL, these codes should be compiled and then synthesized into a number of logical gate configurations that form part of the video acceleration unit 150. These people should be aware that these logic gates can be implemented in a variety of techniques, such as an application-specific integrated circuit (ASIC), programmable logic gate array (PGA), or field-programmed logic gate array (FPGA).

The 410 segment of this code is a module definition. The VC-1 loop deblocking filter hardware acceleration logic circuit 400 has a number of input parameters. The sub-block to be filtered is specified by the block parameter. If the vertical parameter is True, the acceleration logic circuit 400 will block The parameters are treated as 4x8 squares (see Figure 3) and vertical edge filtering is performed. If the vertical parameter is False, the acceleration logic circuit 400 treats the block parameter as an 8x4 block (see Figure 3) and performs horizontal edge filtering.

The section 420 of the code begins an iteration loop, setting the value of the loop parameter variable. When the loop is passed for the first time, the loop parameter is set to 3, so the third line is processed first. Subsequent loop iterations set the loop parameters to 1, 2, and 4. Using these parameters, the VC-1 in-loop deblocking filter hardware acceleration logic circuit 400 repeats 4 times, processing 8 pixels at a time, one of which can be a horizontal column or a vertical line, and each column is line accelerated logic. Circuit 500 processes (see Figure 5). In some embodiments, the row acceleration logic circuit 500 is implemented as an HDL sub-module and will be described in conjunction with FIG.

Section 430 tests the vertical parameters to determine whether to perform vertical or horizontal edge filtering. Based on the result, the eight elements of the row array variable are initialized from the row of the 4x8 input block or the row of the 8x4 input block.

Section 440 determines if the third line has been processed by comparing the loop parameter to 3. If the loop parameter is 3 and the other two control variables, ProcessingPixel3 and FILTER_OTHER_3 are set to true. If the loop parameter is not 3, the ProcessingPixel3 is set to false.

Section 450 illustrates another HDL module, VC1_IDC_Filter_Line, which applies the current line. (As described in connection with Figure 3, the row filter updates the edge pixel values based on neighboring pixel values.) The parameters supplied to the sub-module include the control variables ProcessingPixel3, FILTER_OTHER_3, and loop parameters. In an embodiment, the VC-1 loop deblocking filter hardware acceleration logic circuit The 400 has an additional input parameter, a quantized value, and the quantized parameter is also provided to the sub-module.

After the sub-module processes the column, the VC-1 loop de-blocking filter hardware acceleration logic circuit 400 continues the iteration loop with a loop parameter update value in section 420. In this way, the filter is applied to the third row of the input block, followed by the first row, the second row, and the fourth row.

Figure 5 is a listing of the hardware description language code of the acceleration logic circuit 500, which implements the sub-modules described above. The section 510 of the code is a module definition. The row acceleration logic circuit 500 has a number of input parameters. The line system to be filtered is defined as a line input parameter. ProcessingPixel3 is an input parameter. If the behavior is in the third or third column, it is set to true by the higher layer logic. The parameter FILTER_OTHER_3 is initially set to true by the higher layer logic circuit and is adjusted by the line acceleration logic circuit 500 according to the pixel value.

Section 520 performs various pixel value operations as determined by VC-1. (Because the calculation can be understood with reference to the specification of VC-1, these operations will not be described in detail.) Section 530 tests the ProcessingPixel3 parameters provided by the block-effect filter hardware acceleration logic circuit 400 in the higher layer VC-1 loop. . If ProcessingPixel3 is true, then section 530 initializes a control variable DO_FILTER to a predetermined value, true. The various results of the operations in the middle of the segment 520 are used to determine if the other three rows are also to be processed. If the pixel operation result indicates that the other three lines are not processed, DO_FILTER is set to false.

If ProcessingPixel3 is false, segment 540 uses the input parameter FILTER_OTHER_3 (set by the higher layer VC-1 loop to the block effect filter hardware acceleration logic circuit 400) to set the value of DO_FILTER. If DO_FILTER is true, segment 540 tests the DO_FILTER variable and updates the edge pixels P4, P5 of the row variable (see Figure 3).

Section 550 tests the ProcessingPixel3 parameter and updates FILTER_OTHER_3 as appropriate. The FILTER_OTHER_3 variable is used to convey status information for different examples in this module. If ProcessingPixel3 is true, then section 550 updates the FILTER_OTHER_3 parameter with the value of DO_FILTER. This technique allows the higher layer module (ie VC1_InloopFilter) used to describe this module to provide the FILTER_OTHER_3 value updated by the VC_1_INLOOPFILTER_LINE low-level module of this example to VC_1_INLOOPFILTER_LINE of another example.

Those skilled in the art will appreciate that the virtual code of FIG. 5 can be synthesized in various ways to produce a logic gate arrangement that implements line acceleration logic circuit 500. One of the arrangements is illustrated in Figures 6A-D, which together form a block diagram of row acceleration logic circuit 500. Those skilled in the art should be familiar with the block-effect filter algorithm and logic circuit structure in the VC-1 loop. Therefore, the elements of Figures 6A-D will not be described in detail. The features of the row acceleration logic circuit 500 will be selected in detail.

Those skilled in the art will appreciate that the operations involved in the deblocking filter in the VC-1 loop include the following, where P1-P8 refers to the position of the pixel in the column/row being processed.

A0=(2*(P3-P6)-5*(P4-P5)+4)>>3

A1=(2*(P1-P4)-5*(P2-P3)+4)>>3

A2=(2*(P5-P8)-5*(P6-P7)+4)>>3

Clip=(P4-P5)/2

Each of the first three operations involves three subtractions, two multiplications, one addition, and one right shift. One portion of the row acceleration logic circuit 500 in FIG. 6A uses the shared logic circuit to sequentially calculate A0, A1, A2 instead of using specific independent logic circuit blocks for A0, A1, A2. By avoiding the repetition of the logic circuit blocks, the multiplexer is used to sequentially process the inputs, reducing logic gates and/or power consumption.

Multiplexers 605, 610, and 620 are used to select different inputs from pixel register P-8 for different timing periods, and these inputs are provided to the respective shared logic blocks. Logic circuit blocks 625 and 630 each perform a subtraction. Logic circuit block 635 is multiplied by 2 by performing a left shift of 1 bit. The multiplication is performed by shifting one bit to the left, followed by an adder 645. Adder 650 adds the output of left shifter 635, a constant 4 and the negative of the 645 output. Finally, logic circuit block 655 performs a right shift of 3 bits.

In the first timing cycle, an input T = 1 is supplied to each of the multiplexers 605, 610, and 615, and the value of A1 is calculated and stored in the register 660. In the second timing cycle, an input T=2 is provided to each of the multiplexers 605, 610, and 615, and the value of A2 is calculated and stored in the register 665. In the third timing cycle, an input T=3 is provided to each of the multiplexers 605, 610, and 615, and the value of A0 is calculated and stored in the register 670. The values A1, A2, A3 in which the registers 660, 665, 670 are present will be used by the partial row acceleration logic circuit 500 of Figure 6B, as will be described later. The output of the P4 register (671) and the output of the P5 register (673) will be used by the partial line acceleration logic circuit 500 of Figure 6C, as will be described later.

Those skilled in the art should also understand that the de-blocking filter in the VC-1 loop involves additional operations that are described later:

The partial row acceleration logic circuit 500 of FIG. 6B receives input from the partial row acceleration logic circuit 500 of FIG. 6A and calculates D (675). Referring again to FIG. 6A, CLIP (677) is generated as follows: Pixels P4 and P5 are subtracted from logic circuit block 679, and the result is shifted right by logic block 680 (integer divided by 2) to produce CLIP 677. Going back to Figure 6B, A1 can be in the first The cycle is taken from the register 660, A2 is available from the register 665 in the second cycle, and A0 is available from the register 670 in the third cycle. Thus, in the fourth cycle, the partial line acceleration logic circuit 500 of FIG. 6 calculates D (675) according to the above equation.

Line acceleration logic circuit 500 utilizes (675) to update the pixel locations of P4, P5. In particular, P4 = P4-D and P5 = P5 + D. Although the 6A, 6B diagrams have previously been described in connection with a single column/row (e.g., a single set of pixel locations P0-P8), the operation of the third column/row of a sub-block affects the behavior of the other three columns/rows of the sub-block. Row acceleration logic circuit 500 implements this behavior using a groundbreaking approach. When the independent filtering operation is started from the front - parallel - completion, in conjunction with the description of Figs. 6A, 6B, the partial line acceleration logic circuit 500 shown in the 6C, 6D diagram conditionally selects the position to be updated. In other words, the VC-1 in-loop deblocking filter hardware acceleration logic circuit 400 determines that the original value was written back or the new value was written back. In contrast, a conventional method, a VC-1 loop de-blocking filter uses a loop, so independent filtering operations are performed conditionally.

As previously explained, FIG. 4 illustrates that the virtual code of row acceleration logic circuit 500 operates in a loop: an instantiation section 450 appears in a repeating section 420. In addition, the example of row acceleration logic circuit 500 uses two parameters, ProcessingPixel3 and FILTER_OTHER_3. These parameters of the row acceleration logic circuit 500 are used to conditionally update the pixels P4, P5 as follows. Referring to Figure 6C, the register P4 is written to the result of the subtractor 681, wherein the subtractor 681 has an input of P4 (671), which is 0 or D (675), depending on the value of DO_FILTER (683). Similarly, the register P5 writes the result of the adder 685, wherein the adder 685 has an input of P5 (673), which is 0 or D (675), depending on the value of DO_FILTER (683). Thus, the updated value of P4 is the original P4 value (if DO_FILTER is false), or P4-D. Similarly, the updated value of P5 is the original P5 value (if DO_FILTER is false), or P5+D.

Those skilled in the art should understand that when processing the third column of a sub-block, the standard for updating P4 with P4-D is: ((ABS(A0)<PQUANT)OR(A3<ABS(A0))OR(CLIP) !=0)

The DO_FILTER 683 is calculated by the partial line acceleration logic circuit 500 that tests these conditions in Figure 6D. Multiplexer 687 provides an input to OR gate 697. If ABS(A0)<PQUANT selects a true output, the others are false. Multiplexer 689 provides another input to OR gate 697, if A3 < ABS (A0) then selects a true output, others are false. Multiplexer 691 provides another input to OR gate 697, if CLIP! =0 selects a true output, others are false.

DO_FILTER 683 is provided by multiplexer 693, which utilizes control input Processing_Pixel_3 (695) to select the output of output OR gate 697 or input signal FILTER_OTHER_3 (699). The input of Processing_Pixel_3 (695) and FILTER_OTHER_3 (699) previously described in conjunction with FIG. 4 and the virtual code of the higher layer VC-1 in-loop deblocking filter hardware acceleration logic circuit 400 illustrating the row acceleration logic circuit 500 has been described. Returning to Figure 4, when the third row/column is processed (the first lap), Processing_Pixel_3 (695) is set to true, and the others are false. Based on the conditions regarding PQUANT, ABS(A0), and CLIP, an intermediate variable DO_FILTER is recorded, regardless of whether P4/P5 is updated. Last FILTER_OTHER_3 The value of (699) is set from the intermediate variable DO_FILTER. The result of the row acceleration logic circuit 500 of the logic circuit portion of FIGS. 6C and 6 is that the pixel position of P4 and P5 in 4 adjacent columns/rows is set as a filtered value every 4 cycles (according to A0-A3, PQUANT, CLIP, etc. variables) or write their original values again.

The VC-1 deblocking acceleration unit 400 pioneered the combination of parallel and sequential, as previously described. Parallel processing provides faster execution and reduces latency. Although the parallelization increases the number of logic gates, the amount of increase is offset by the aforementioned sequential processing. The conventional method of using the aforementioned sequential processing does not increase the number of logic gates.

Some embodiments of graphics processing unit 120 include a hardware acceleration unit for H.264 deblocking, and the deblocking function is used by the graphics processing unit for use. The graphics processing unit 120 will be described in detail in conjunction with FIG. 8 and enhances the specification of the graphics processing unit instructions that provide the H.264 deblocking acceleration function.

Graphics processor Principle of multiple deblocking instructions

The set of instructions of graphics processing unit 120, including partial decoder 160, implemented in software, can be used to speed up a deblocking filter. It is described herein that a groundbreaking technique provides more than one multiple graphics processing unit instructions to speed up a particular deblocking filter. The in-loop deblocking filter 290 is originally sequential, so a particular filter must filter the pixels in a certain order (eg, H.264 specifies left to right and then top to bottom). Thus, previously filtered or updated pixels are used as input when filtering back pixels. In. The main processor processes the pixel values stored in the conventional memory, which causes the pixels to be read and written one by one. However, the nature of this sequence cannot be properly coordinated when the in-loop deblocking filter 290 uses a graphics processing unit to speed up the partial filtering process. Conventional graphics processing units store pixels in a texture cache, and the graphics processing unit pipeline design does not follow back-to-back read and write texture caches.

It is disclosed herein that some embodiments of graphics processing unit 120 provide multiple graphics processing unit instructions that can be used together to speed up a particular deblocking filter. Some of these instructions use texture cache as a pixel data source, while some instructions use a graphics processing unit execution unit as a data source. The in-loop deblocking filter 290 suitably combines these different graphics processing unit instructions to achieve read and write pixels one after the other. Next, the data flowing through the graphics processing unit 120 will be outlined, followed by the deblocking acceleration commands provided by the graphics processing unit 120, and the in-loop deblocking filter 290.

Graphics processing unit flow

Figure 7 is a diagram of the data flow of graphics processing unit 120, wherein the instruction stream is represented by the arrow to the left of Figure 7, and the image or graphics stream is represented by the arrow to the right. Figure 7 omits several elements familiar to those skilled in the art which are not necessary to interpret the deblocking features within the loop of graphics processing unit 120. An instruction stream processor 710 receives an instruction 720 from a system bus (not shown) and decodes the instruction to generate instruction material 730, such as vertex data. Graphics processing unit 120 supports a conventional graphics processing instruction and instructions for speeding up video encoding and/or decoding.

Conventional graphics processing instructions involve problems such as vertex shading, geometry shading, and pixel shading. Thus, the instruction material 730 is applied to a pool 740 of shader execution units. The shading execution unit necessarily uses a texture filter unit (TFU) 750 to apply a texture to a pixel. The texture data is cached from texture cache 760, which is appended to the main memory (not shown).

Some instructions are sent to the video accelerator 150, the operation of which will be described later. The resulting data is then processed by a post-packer (post-packer 770) which compresses the data. After post-processing, the data generated by the video acceleration unit is provided to an execution unit pool 740.

The execution of the video encoding/decoding acceleration instructions, such as the aforementioned deblocking filtering instructions, differs in many respects from the conventional graphics instructions described above. First, the video acceleration command is executed by the video acceleration unit 150 instead of the shader execution unit. Second, the video acceleration instructions do not use their texture data.

However, the image data used by the video acceleration command and the texture data used by the graphics command are both 2-dimensional arrays. The graphics processing unit 120 also utilizes this advantage to use the texture filtering unit 750 to download image data to the video acceleration unit 150, thereby causing the texture cache 760 to cache some of the image data operated by the video acceleration unit 150. Therefore, as shown in FIG. 7, the video acceleration unit 150 is located between the texture filtering unit 750 and the post-packer 770.

Texture filtering unit 750 examines instruction material 730 retrieved from instruction 720. Instruction material 730 also provides the TFU 750 texture cache 760 desired The coordinates of the image data. In one embodiment, these coordinates are designated U, V pairs, and those skilled in the art should be familiar with this. When the instruction 720 is a video acceleration instruction, the captured instruction material further instructs the texture filtering unit 750 to skip the texture filter (not shown) in the texture filtering unit 750.

According to this method, the texture filtering unit 750 is manipulated as a video acceleration command to download image data to the video acceleration unit 150. The video acceleration unit 150 receives the image data from the texture filtering unit 750 on the data path, and the command material 730 on the command path, and performs an operation on the image data according to the command data 730. The image data output by the video acceleration unit 150 is fed back to the execution unit pool 740 after being processed by the post wrapper 770.

Go block effect instruction

In the embodiment of the graphics processing unit 120 described herein, a VC-1 deblocking filter and a H.264 deblocking filter hardware acceleration are provided. The VC-1 deblocking filter is accelerated by a graphics processing unit instruction ("IDF_VC-1"), while the H.264 deblocking filter is commanded by three graphics processing units ("IDF_H264_0", "IDF_H264_1"," IDF_H264_2") acceleration.

As previously explained, each graphics processing unit instruction is decoded and parsed into instruction material 730, which can be viewed as a particular set of parameters for each instruction, as shown in the first table. The IDF_H264_x instruction shares some common parameters, while the others are unique to each instruction. Those skilled in the art should understand that these parameters can be encoded using various opcodes and instruction formats, so these topics will not be discussed here.

A number of input parameters are used in combination to determine the 4x4 block address captured by texture filtering unit 750. The BaseAddress parameter indicates the starting point of the texture data in the texture cache. Mark the upper left square of this area BaseAddress parameter. The PictureHeight and PictureWidth input parameters are used to determine the range of the square, the lower left coordinate. Finally, the video graphics can be progressive (progessive) or interlaced (interlace). For interlaced scanning, it consists of two directions (upper and lower). The texture filtering unit 750 uses FieldFlag and TopFieldFlag to properly process the interlaced scanned image.

The deblocking 8x4x8 bit output is provided to a target register and also written back to the execution unit pool 740. Writing the deblocking output back to the execution unit pool 740 is a "modify in place" operation that is necessary in some decoder implementations, such as the pixel values in the H.264 block, right and below. , calculated according to the previous results. However, the VC-1 decoder does not have this limitation relationship like H.264. In VC-1, each 8x8 boundary (first vertical and then horizontal) is filtered. All vertical edges can thus be executed substantially in parallel, with the 4x4 edges being filtered later. Parallelization can be utilized because only two pixels (one edge at a time) are updated, and these pixels are not used to calculate other edges. Since the deblocking data is written back to the execution unit pool 740 instead of the texture cache 760, a different IDF_H264_x instruction is provided, which is retrieved from a different location. This can be seen in the first table, in the description of BlockAddress, the Data Block 1 and Data Block 2 parameters. The IDF_H264_0 instruction fetches the entire 8x4x8 bit sub-block from texture cache 760. The IDF_H264_1 instruction fetches half of the sub-blocks from texture cache 760 and fetches half from execution unit pool 740.

The function of the IDF_H264_x instruction as a function of decoder 160 will be described in more detail in connection with FIG. Next, before the pixel data is supplied to the video acceleration unit 150, the texture filtering unit 750 and the execution unit pool 740 convert the captured image. Processing of prime data.

Conversion of image data

The instruction parameters described above provide coordinates to the texture filtering unit 750 for the sub-block address to be extracted from the texture cache 760 or from the execution unit pool 740. The image data contains the brightness (Y) and chroma (Cb, Cr) planes. A YC flag input parameter defines whether the Y plane or the CbCr plane is to be processed.

When processing the luminance (Y) data, as indicated by the YC flag parameter, the texture filtering unit 750 extracts the sub-block and provides the 128-bit as a VC-1 loop deblocking filter hardware acceleration logic circuit 400. Input (such as the block input parameter of the VC-1 accelerator example in Figure 4). The generated data is written to the target register as a group of four registers (registered quads, ie, DST, DST+1, DST+2, DST+3).

When processing the chroma data, as indicated by the YC flag parameters, the Cb and Cr blocks will be continuously processed by the block-1 filter hardware acceleration logic circuit 400 within the VC-1 loop. The resulting data is written to texture cache 760. In some embodiments, this write action occurs in each cycle, with 256 bits written per cycle.

Some video acceleration unit embodiments use interlaced scanning CbCr planes, each of which is half the width and half the length. In these embodiments, the texture filtering unit 750 scans the CbCr sub-block data for the video acceleration unit 150 to communicate with one of the texture filtering unit 750 and the video acceleration unit 150. In particular, texture filtering unit 750 writes two 4x4 Cb squares to the buffer, and then writes two 4x4 Cr squares to the buffer. The 8x4 Cb block is first accelerated by the blocker filter hardware in the VC-1 loop. The circuit 400 processes and the generated data is written to the texture cache 760. Next, the 8x4 Cr block is processed by the VC-1 loop deblocking filter hardware acceleration logic circuit 400, and the resulting data is written to texture cache 760. The video acceleration unit 150 uses the CbCr flag parameters to manage this sequential processing.

Software decoder uses deblocking instructions

In conjunction with the previous description of FIG. 1, decoder 160 executes on main processor 110 but also utilizes video acceleration instructions provided by graphics processing unit 120. In particular, the embodiment of the H.264 loop deblocking filter 290 uses a specific IDF_H264_x combination to process the edges, extracting some sub-blocks from the texture cache 760 and executing from the execution unit pool 740 in the order specified by H.264. Take some more. With proper combination, these IDF_H264_x instructions achieve one pixel read and write.

Figure 8 is a block diagram of a 16x16 large block for H.264. This large square is cut into 16 4x4 sub-blocks, each of which will perform a deblocking effect. The four sub-blocks in Figure 8 can be defined by columns and rows (for example, R1, C2). The H.264 definition first processes the vertical edges at the processing horizontal edges, as shown in Figure 8 (a-h).

Therefore, the deblocking filter is applied to the edge between a pair of sub-blocks, and the sub-blocks are filtered in this order: edge a=[block to left of R1,C1]| [R1,C1];[block to left Of R2,C1]|[R2,C1];[block to left of R3,C1]| [R3,C1];[block to left of R4,C1]| [R4,C1]edge b=[R1,C1 ]| [R2,C2];[R2,C1]|[R2,C2];[R3,C1]| [R3,C2];[R4,C1]|[R4,C2];edge c=[R1, C2]| [R2,C3];[R2,C2]|[R2,C3]; [R3,C2]| [R3,C3];[R4,C2]|[R4,C3];edge d=[R1,C3]| [R2,C4];[R2,C3]|[R2,C4] ;[R3,C3]| [R3,C4];[R4,C3]|[R4,C4];edge e=[block to top of R1,C1]| [R1,C1];[block to top of R1 ,C2]|[R1,C2];[block to top of R1,C3]| [R1,C3];[block to top of R1,C4]| [R1,C4]edge f=[R1,C1]| [R2,C1];[R1,C2]|[R2,C2];[R1,C3]| [R2,C3];[R1,C4]|[R2,C4]edge g=[R2,C1]| [R3,C1];[R2,C2]|[R3,C2];[R2,C3]| [R3,C3];[R2,C4]|[R3,C4]edge h=[R3,C1]| [R4,C1];[R3,C2]|[R4,C2];[R3,C3]| [R4,C3];[R3,C4]|[R4,C4]

For the first pair of sub-blocks, the texture cache 760 is downloaded since no pixels have been changed due to the application of the filter. Although the filter of the first vertical edge (a) can change the pixel value of (R1, C1), the vertical edge of the second column actually shares all the pixels with the vertical edge of the first column. Therefore, the second pair of sub-blocks (edge b) are also downloaded from texture cache 760. Since the vertical edges between two adjacent columns do not share pixels, the third pair (edge c) is the same as the fourth pair (edge d) sub-block.

The specific IDF_H264_x command issued by the in-loop deblocking filter 290 determines that pixel data is to be downloaded from that location. The order of processing the first set of vertical edges (ad) by the IDF_H264_x instruction used by the in-loop deblocking filter 290 is: IDF_H264_0 SRC1 = address of (R1, C1); IDF_H264_0 SRC1 = address of (R2, C1); IDF_H264_0 SRC1=address of(R3,C1); IDF_H264_0 SRC1=address of(R4,C1);

Next, the in-loop deblocking filter 290 processes the second vertical edge (b) starting from (R1, C2). The leftmost 4 pixels in the 8x4 sub-block defined as (R1, C2) overlap with the rightmost pixel of the (R1, C1) sub-block. These are processed by the vertical edge filters of (R1, C1) and may also be updated, and the overlapping pixel systems are thus read from the execution unit pool 740 instead of the texture cache 760. However, the 4 pixels to the far right of the (R1, C2) sub-block are not yet filtered and are therefore read from texture cache 760. Sub-blocks (R2, C2) to (R4, C2) are also the same. The in-loop deblocking filter 290 processes the second set of vertical edges by commanding the order of IDF_H264_x below to complete the result: IDF_H264_1 SRC1=address of(R1, C2); IDF_H264_1 SRC1=address of(R2, C2); IDF_H264_1 SRC1=address of(R3,C2);IDF_H264_1 SRC1=address of(R4,C2);

When processing the third set of vertical edges, start with (R1, C3). The leftmost 4 pixels in the (R1, C3) 8x4 sub-block overlap with the rightmost pixel of the (R1, C2) sub-block, and thus are read from the execution unit pool 740 instead of the texture cache 760. However, the 4 pixels to the far right of the (R1, C2) sub-block are not yet filtered and are therefore read from texture cache 760. The sub-blocks (R1, C2) to (R4, C2) are also the same. A similar situation occurs with the last set of vertical edges. Therefore, the in-loop deblocking filter 290 processes the remaining two sets of vertical edges by ordering the following IDF_H264_x: IDF_H264_1 SRC1=address of(R1, C3); IDF_H264_1 SRC1=address of(R2, C3); IDF_H264_1 SRC1 =address of(R3,C3); IDF_H264_1 SRC1=address of(R4,C3);IDF_H264_1 SRC1=address of(R1,C4);IDF_H264_1 SRC1=address of(R2,C4);IDF_H264_1 SRC1=address of(R3,C4);IDF_H264_1 SRC1=address of( R4, C4);

The horizontal edge (e-h) is then processed. At this point, the deblocking filter has been applied to each sub-block in the large square, so each pixel may have been updated. Therefore, each sub-block sent to perform horizontal edge filtering is read from execution unit pool 740 instead of texture cache 760. Therefore, the in-loop deblocking filter 290 processes the horizontal edge by ordering the following IDF_H264_x: IDF_H264_2 SRC1=address of(R1, C1); IDF_H264_2 SRC1=address of(R2, C1); IDF_H264_2 SRC1=address of( R3,C1);IDF_H264_2 SRC1=address of(R4,C1);IDF_H264_2 SRC1=address of(R1,C2);IDF_H264_2 SRC1=address of(R2,C2);IDF_H264_2‧‧‧SRC1=address of(R3,C2 );IDF_H264_2 SRC1=address of(R4,C2);IDF_H264_2 SRC1=address of(R1,C3);

A block of any program description or flow diagram should be understood to represent a module, segment or portion of code, which comprises one or more executable instructions for implementing a particular logic circuit function or a step in a program. Those skilled in the software sector should be aware that other implementation methods are also included in the scope of the disclosure. In other implementations, the functions may be performed in the order shown or disclosed, including substantially concurrent or reverse, Depending on the function involved.

The systems and methods disclosed herein can be implemented in software, hardware, or a combination thereof. In some embodiments, the system and/or method is implemented in software stored in memory and executed by a suitable processor located in a computing device (including but not limited to a microprocessor, microcontroller, network Road processor, reassemblable processor, expandable processor). In other embodiments, the system and/or method is implemented by a logic circuit, including but not limited to a programmable logic device (PLD), a programmable gate array (PGA), and a field programmable circuit array (PGA). A programmable gate array (FPGA) or an application specific circuit (ASIC). In other embodiments, these logical narratives are performed in a graphics processor or graphics processing unit (GPU).

The systems and methods disclosed herein can be embedded in any computer readable medium or linked to an instruction execution system, apparatus, or device. The instruction execution system includes any computer-based system, a system containing the processor, or other system from which the instructions can be retrieved and executed. The disclosed text "computer-readable medium" can be any means by which the program can be stored, stored, communicated, communicated or transmitted for use or in connection with the execution system of the instruction. The computer readable medium can be, for example, a non-limiting, electronic or magnetic, optical, electromagnetic, infrared, or semiconductor technology system or delivery medium.

A specific example (not limiting) of a computer readable medium using electronic technology may include: a line having one or more electrical (electronic) connections; a random access memory (RAM); a read only memory body (ROM, read-only memory); can erase the programmable read-only memory (EPROM or flash memory). Specific examples of computer readable media that use magnetic technology (without limitation) may include: a portable computer diskette. A specific example (not limiting) of a computer readable medium using optical technology can include: an optical fiber and a portable CD-ROM.

The invention is illustrated and described herein by way of example only, and is not intended to Many different modifications and structural changes are made within the scope and scope of equalization. Therefore, it is preferable to interpret the scope of the appended patent application broadly and in a manner consistent with the field of the invention, and to make this statement before the scope of the subsequent patent application.

100‧‧‧ system

110‧‧‧General Purpose CPU

120‧‧‧Graphics Processor (GPU)

130‧‧‧ memory

140‧‧‧ Busbar

150‧‧‧Video Acceleration Unit (VPU)

160‧‧‧Software decoder

170‧‧‧Video Acceleration Driver

205‧‧‧Input bit stream

210‧‧‧ Entropy decoder

215‧‧‧ Space Decoder

220‧‧‧Inverse Quantizer

230‧‧‧Inverse Discrete Cosine Transform

235‧‧‧ graphics

245‧‧‧Mobile vector

250‧‧‧Mobile compensation

255‧‧‧ previously decoded graphics

265‧‧‧ forecast graphics

270‧‧‧ Space compensation

280‧‧‧Adder

290‧‧‧Deblocking filter

295‧‧‧Decoding graphics

310-320‧‧‧Two adjacent 4x4 sub-blocks

330‧‧‧ vertical boundary

400‧‧‧In-loop deblocking filter hardware acceleration logic circuit

410‧‧‧Module Definition Section

420‧‧ ‧Replicated loop section

430‧‧‧Test vertical parameter section

440‧‧‧Compare loop parameters with 3 segments

450‧‧‧Example section

500‧‧‧ lines of acceleration logic

510‧‧‧Module Definition Section

520‧‧‧Pixel Value Operation Section

530‧‧‧Compare loop parameters with 3 segments

540‧‧‧Test DO_FILTER section

550‧‧‧Update status section

605-610-615-620‧‧‧Multiplexer

625-630-679‧‧‧Subtractor

635-640-655-680‧‧‧Logical Circuit Blocks

645-650‧‧‧Adder

660-665-670‧‧‧ 存存器

671‧‧‧P4 register output

673‧‧‧P5 register output

681‧‧‧Subtractor

685‧‧‧Adder

687-689-691-693‧‧‧Multiplexer

697‧‧‧OR gate

710‧‧‧Instruction Stream Processor

720‧‧‧ directive

730‧‧‧Instruction Information

740‧‧‧Executive unit pool

750‧‧‧Texture Filter Unit

760‧‧‧Texture cache

770‧‧‧post wrapper

Figure 1 is a block diagram of an exemplary computing platform for graphics and video coding and/or decoding.

Figure 2 is a block diagram of the video decoder 160 in Figure 1.

Figure 3 illustrates the sub-block pixel settings of a VC-1 filter.

Figure 4 is a block diagram of the hard description virtual code of the block-effect filter hardware acceleration logic circuit 400 in the VC-1 loop.

Figure 5 is a list of hardware description language code for the acceleration logic circuit 500 of Figure 4.

Fig. 6A-D is a block diagram showing the acceleration logic circuit of the fourth and fifth rows.

Figure 7 is a data flow diagram of the graphics processing unit 120 of Figure 1.

Figure 8 is a block diagram of a 16x16 large block used by H.264.

205‧‧‧Input bit stream

210‧‧‧ Entropy decoder

215‧‧‧ Space Decoder

220‧‧‧Inverse Quantizer

230‧‧‧Inverse Discrete Cosine Transform

235‧‧‧ graphics

245‧‧‧Mobile vector

250‧‧‧Mobile compensation

255‧‧‧ previously decoded graphics

265‧‧‧ forecast graphics

270‧‧‧ Space compensation

280‧‧‧Adder

285‧‧‧Mode selector

290‧‧‧Deblocking filter

295‧‧‧Decoding graphics

Claims (20)

A deblocking filter for video decoding, comprising: a first logic circuit for performing correlation of each pixel group in a plurality of pixel groups according to a corresponding group of filtering units in the complex array filtering unit a second logic circuit for determining whether a pixel of a predetermined pixel group of the plurality of pixel groups reaches a standard; a third logic circuit configured to: when the standard is reached, according to the predetermined pixel group Correlating filtering operation, first filtering the pixels of the predetermined pixel group; and a fourth logic circuit, configured to, when the standard is reached, sequentially sequence the remaining pixel groups in the plurality of pixel groups according to the corresponding correlation filtering operation Filtering, wherein when the criterion is not met, the fourth logic circuit maintains pixels in the pixel groups unfiltered according to the correlation filtering operation corresponding to maintaining the plurality of pixel groups. The deblocking filter for video decoding according to claim 1, wherein the plurality of pixel groups form a square pixel block, and each pixel group of the plurality of pixel groups comprises a column of pixel blocks. The deblocking filter for video decoding according to claim 1, wherein the plurality of pixel groups form a square pixel block, and each pixel group of the plurality of pixel groups comprises a row of pixel blocks. The deblocking filter for video decoding according to claim 1, wherein the third logic circuit further comprises: a fifth logic circuit, configured to be based on one of the remaining pixel groups. The predetermined pixel group is updated to update one of the remaining predetermined pixel groups. The third logic circuit further includes: a sixth logic circuit configured to, when the standard is reached, first parallel to the pixels of the predetermined pixel group, as in the deblocking filter for video decoding in claim 1 Filtering. A deblocking filter for video decoding according to claim 1, wherein the deblocking filter for video decoding is applied to an edge between sub-block pairs to remove edge products. A deblocking filter for video decoding according to claim 1, wherein the deblocking filter for video decoding uses a plurality of graphics processing instructions combined to achieve one pixel read and write. In. A deblocking filter for video decoding according to claim 1 of the patent application, wherein the deblocking filter for video decoding is defined in accordance with the VC-1 standard. A video decoder comprising: an entropy decoder for receiving an input encoded bit stream; a spatial decoder receiving the output of the entropy decoder and generating a coded picture comprising a plurality of pixels; a first logic circuit, setting Combining a current picture with a predicted picture to generate a combined picture; and a loopback internal block effect filter to receive the combined picture, the in-loop deblocking filter includes: a second logic circuit for a corresponding group of filtering units in the complex array filtering unit to perform a correlation of each pixel group in the plurality of pixel groups Filtering operation; a third logic circuit configured to: when a predetermined pixel group of the plurality of pixel groups reaches a standard, filter the predetermined pixel group according to the correlation filtering operation of the predetermined pixel group; and a fourth logic a circuit configured to: when the predetermined pixel group reaches the standard, filter the remaining pixel groups in the plurality of pixel groups according to the correlation filtering operation of the predetermined pixel group, wherein when the predetermined pixel group does not meet the criterion, The fourth logic circuit maintains pixels in the pixel groups unfiltered according to the correlation filtering operation corresponding to the plurality of pixel groups. The video decoder of claim 9, wherein the plurality of pixel groups form a square pixel block, and each pixel group of the plurality of pixel groups comprises a column of pixel squares. The video decoder of claim 9, wherein the plurality of pixel groups form a square pixel block, and each pixel group of the plurality of pixel groups comprises a row of pixel blocks. The video decoder of claim 9, wherein the third logic circuit further comprises: a fifth logic circuit configured to filter the pixels of the predetermined pixel group in parallel when the standard is reached. The video decoder of claim 9, wherein the fourth logic circuit further comprises: a sixth logic circuit, configured to update each of the remaining pixels according to one of the remaining predetermined pixel groups One of the first predetermined pixel groups in the group of pixels. For example, the video decoder of claim 9 of the patent scope, wherein the loop is The block effect filter is defined in accordance with the VC-1 standard. A graphics processing unit includes: a main processing interface, receiving at least one video acceleration command; and a video acceleration unit for responding to at least one video acceleration command, the video acceleration unit including a loop-in-square block effect filter, The in-loop deblocking filter comprises: a first logic circuit for performing a correlation filtering operation on each pixel group in the plurality of pixel groups according to a corresponding group of filtering units in the complex array filtering unit; The second logic circuit is configured to determine whether the pixel of the predetermined pixel group of the plurality of pixel groups reaches a first standard; a third logic circuit is configured to: when the first standard is reached, the correlation filtering according to the predetermined pixel group Computing, first filtering the pixels of the predetermined pixel group; and a fourth logic circuit configured to, when the first criterion is reached, sequentially perform the correlation filtering operation on the remaining pixel groups in the plurality of pixel groups, sequentially ordering the complex number The remaining pixel group filtering in the pixel group, wherein the predetermined pixel group does not reach the standard according to the plurality of pixels The respective correlation filtering operation, maintaining the unfiltered pixels of those pixel groups. The graphics processing unit of claim 15, wherein the plurality of pixel groups form a square pixel block, and each pixel group of the plurality of pixel groups comprises a column of pixel squares. The graphics processing unit of claim 15, wherein the plurality of pixel groups form a square pixel block, and each pixel of the plurality of pixel groups A group contains a row of pixel squares. The video decoder of claim 15, wherein the fourth logic circuit further comprises: a fifth logic circuit, configured to update each of the remaining pixels according to a second predetermined pixel group in each of the remaining pixel groups One of the first predetermined pixel groups in the group of pixels. A video decoder as claimed in claim 15 wherein the in-loop block effect filter is defined in accordance with the VC-1 standard. The graphics processing unit of claim 15, wherein the first logic circuit is further configured to perform the correlation filtering operation on each of the plurality of pixel groups in parallel.