Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

• Another object of the invention is to provide a novel integrated circuit which generates an output pulse in response to an input signal with a substantially smaller tolerance in the pulse width than the prior art.
• Another object of the invention is to provide an integrated circuit memory which incorporates a novel delay/pulse generating circuit to achieve a smaller power dissipation than the prior art.
• a memory is constructed in an integrated circuit chip as follows. Firstly, an array of memory cells and a read/ rite circuit is provided such that the read/write circuit performs a predetermined operation on the array for a time interval that is set by the width of a pulse signal. Also, a pulse generator is provided which is coupled to the read/write circuit and which contains transistors that switch on and off at an unpredictable speed to generate the pulse signal such that the width of the pulse signal has a large tolerance. Further, a compensation circuit is provided which includes a plurality of compensation components for the pulse generator circuit. This compensation circuit selectively couples the compensation components to the pulse generator such that the selectively coupled components in combination with the pulse generator's transistors produce the pulse signal with a precise width that has an insignificant tolerance.
• Fig. 13 is a circuit which generates the precharge signals, wordline signals, and sense signals as shown in Fig. 12 in accordance with the present invention.
• Fig. 14 is a circuit diagram of a dynamic memory in which the precharge signals, wordline signals, and sense signals are precisely generated with the present invention.
• Fig. 16a shows a circuit which is used to generate control signals for the circuit of Fig. 15.
• Fig. 16b shows a circuit which is an alternative to the circuit of Fig. 16a.
• Signal OSC from the ring oscillator 31 is sent to the divide by N circuit 32; and in response, that circuit generates an output signal OSCN.
• Signal OSCN is the same as the signal OSC except that it is reduced in frequency by a factor of N.
• Signal OSCN is sent to a clock input CK on the up-counter 33; and, that counter also receives a reset signal RES on a reset input R.
• signal RES When signal RES is high, the counter 33 is reset: to a count of zero; whereas when signal RES is low, the counter 33 counts up by one for each low-to-high transition which occurs in the signal OSCN.
• FIG. 5 A timing diagram which illustrates the operation of the control module 30 and the compensation module 40 is shown in Fig. 5.
• the up-counter 33 is reset to a count of zero by the reset signal RES being high during a time interval ⁇ TR.
• the enable signal EN goes high; and in response, signal OSC from the ring oscillator 31 starts to oscillate.
• Each low-to-high transition in the ring oscillator signal OSC causes the up-counter 33 to increment the count signal CNT by one.
• the control signal SL from the decoder 34 will be high; and in Fig. 5, this occurs up to a time instant t2. At that time, the count
• Capacitance C IS selected such that when the switching speed of the transistors 20a and 20b is at the middle of medium sub-range, then the output signal v 0 from module 20 w ll again have the ideal predetermined delay 51a.
• capacitance CL IS selected such that when the switching speed of the transistors 20a and 20b is at the middle of the fast speed sub-range, then the output signal v 0 from module 20 will have the ideal predetermined delay 51a.
• the speed of the transistors 20a and 20b have the tolerance ⁇ 2 as shown in Fig. 6.
• the output signal v 0 from module 20 will have a
• each bit in that counter which is high will couple a capacitor in the compensation module 40' to the inverters 20-1 through 20-3.
• each bit in that counter which is high will couple a capacitor in the compensation module 40' to the inverters 20-1 through 20-3.
• capacitor Ci will be coupled by the pass gates 41 to the inverters 20-1 through 20-3; and simultaneously, capacitors 2C ⁇ will be coupled by the pass gates 42 to the inverters 20-1 through 20-3.
• capacitors 2C ⁇ will be coupled by the pass gates 42 to the inverters 20-1 through 20-3.
• the width W2 of the SENSE pulse must be precisely controlled. And, in accordance with the present invention, this is achieved by generating the SENSE pulse with the circuits of Figs. 4 through 10.
• Fig. 13 shows the structural details of a circuit which generates the precharge signal
• Fig. 8 is used in circuit 81, then respective capacitors
• the number of inverters after inverter 8O-N2 up to and including inverter 80-N is selected such that the delay through those inverters, plus the delay which is added by the control/compensation circuit 81, equals the desired width 2 of the SENSE signal.
• Precharge circuit 102 consists of a single transistor 102a.
• Sense amplifier 103 consists of five transistors 103a through 103e. All of the components within the precharge circuit and the sense amplifier and the memory cells are interconnected as shown in Fig. 14.
• control signal CTL X will be a high voltage.
• a respective one of the control circuits 110 or 120 is used.
• the control circuit 110 is used to generate the control signals for the compensation circuit 40 of Fig. 4, then three of the control circuits 110 are used.
• One control circuit 110 will generate the SL control signal; a second control circuit 110 will generate the MED control signal; and a third control circuit 110 will generate the FA control signal .
• control circuit 120 is used to generate the control signals for the compensation circuit 40' of Fig. 8, then three of the control circuits 120 will be used. One control circuit 120 will generate the BIT2 0 control signal; a second control circuit 120 will generate the BIT2 1 control signal; and a third control circuit 120 will generate the BIT2 2 control signal .

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• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Dram (AREA)

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• 1996
  • 1996-12-13 EP EP96942950A patent/EP0867068A1/de not_active Withdrawn
  • 1996-12-13 JP JP09522890A patent/JP2000502204A/ja active Pending
  • 1996-12-13 WO PCT/US1996/019672 patent/WO1997023042A1/en not_active Application Discontinuation

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