EP0828988B1 - Programmable electronic timer circuit - Google Patents

Programmable electronic timer circuit Download PDF

Info

Publication number
EP0828988B1
EP0828988B1 EP96911525A EP96911525A EP0828988B1 EP 0828988 B1 EP0828988 B1 EP 0828988B1 EP 96911525 A EP96911525 A EP 96911525A EP 96911525 A EP96911525 A EP 96911525A EP 0828988 B1 EP0828988 B1 EP 0828988B1
Authority
EP
European Patent Office
Prior art keywords
signal
stage
counter
program
logic state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96911525A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0828988A1 (en
EP0828988A4 (en
Inventor
James C. Gwynn, Iii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ensign Bickford Co
Original Assignee
Ensign Bickford Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ensign Bickford Co filed Critical Ensign Bickford Co
Publication of EP0828988A1 publication Critical patent/EP0828988A1/en
Publication of EP0828988A4 publication Critical patent/EP0828988A4/en
Application granted granted Critical
Publication of EP0828988B1 publication Critical patent/EP0828988B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F42—AMMUNITION; BLASTING
    • F42B—EXPLOSIVE CHARGES, e.g. FOR BLASTING, FIREWORKS, AMMUNITION
    • F42B3/00—Blasting cartridges, i.e. case and explosive
    • F42B3/10—Initiators therefor
    • F42B3/12—Bridge initiators
    • F42B3/121—Initiators with incorporated integrated circuit
    • F42B3/122—Programmable electronic delay initiators

Definitions

  • the present invention relates to an electronic timer circuit and in particular to a useful programmable electronic timer circuit.
  • the timer circuit is designed to provide stable, accurate and repeatable time delays between an input signal it receives and an output signal it produces over a wide range of operating voltages and temperatures.
  • the invention also relates to an electronic detonator circuit that includes such a timer circuit to provide an output signal to initiate an explosive charge after a predetermined time interval from receipt of an initiation signal.
  • a detonator for initiating an explosive charge it is often important to precisely control the timing with which the explosive charge is initiated after receipt of an initiation signal. It is known to provide a detonator with a pyrotechnic or an electronic timer for this purpose. For example, in controlling the timing of a sequence of explosions in blasting operations such as mining, quarrying, construction or demolishing a structure, such as a building, a series of explosive charges must be set off in a precisely timed sequence, in order to obtain the desired blasting effect, minimize shock forces acting on the surrounding area and properly demolish the structure. This requires a series of detonators, each of which can initiate an explosive charge at a predetermined precise time interval, usually measured in milliseconds, from receipt of an ignition signal.
  • Conventional pyrotechnic delay elements incorporated into detonators used to initiate explosive charges are subject to inherent manufacturing variations with respect to density and type of chemical delay composition contained therein, and so cannot be relied upon to provide highly accurate delay intervals.
  • the cap is mounted on the end of a length of shock tube which carries an impulse type initiation signal to the cap.
  • the impulse signal acts on a piezoelectric generator forming part of the circuitry, and the piezoelectric generator generates an electric input signal to the electronic timer circuit. After a predetermined delay the timer circuit emits an output signal that is used to fire the cap.
  • conventional electronically-timed detonators suffer from limitations inherent in conventional electronic timers with respect to the flexibility and reliability with which they may be programmed (to provide a desired delay interval) and tested.
  • conventional multistage digital timers may consist of a number of toggle-counter stages, each with a separate line that is brought out of the circuit for programming purposes. Each of those lines has to be mechanically connected to either the supply voltage or ground signal and another program line is required to load these program signals into the counter stages.
  • the counter stages are pre-set to the voltage levels that their individual program lines are connected to when the program line is activated.
  • Such timers do not contain built-in voltage regulators and do not contain built-in oscillator circuits.
  • a conventional fourteenstage programmable counter would require two power supply lines, fourteen programming lines, one program load line, one oscillator input line and at least one output line. Such a circuit would require at least nineteen separate lines for proper operation.
  • the programming circuit may comprise a fuse current input
  • each program stage may comprise: (a) a latch means for producing a latch signal from which the program stage signal is derived, (b) a fuse which when intact during operation of the timer grounds the latch signal whereby the program stage signal has an inactive logic state and which when blown allows the latch signal to yield a program stage signal having an active logic state, and (c) a fuse switch means responsive to the logic state of the preceding counter stage output signal, for passing the fuse current to the fuse to blow the fuse when the preceding counter stage output is active.
  • the timer circuit may further comprise a program signal input for receiving and conveying to each program stage a program signal, and each fuse switch means may be responsive to the presence of a program signal whereby the fuse switch means will pass the fuse current to the fuse when the preceding counter stage output signal has an active logic state.
  • the programming circuit may further comprise test means associated with each program stage for yielding an active program stage signal even when the fuse is intact.
  • the timer circuit of the invention may be incorporated in an electronic delay detonator circuit for use in blasting initiation systems energized by a non-electric impulse signal according to claim 5.
  • the detonator circuit may comprise part of an electronic delay detonator comprising a housing having one end dimensioned and configured to be coupled to a signal transmission line capable of transmitting a non-electric impulse input signal into the housing, an electronic delay detonator circuit as described above with the signal conversion means disposed in signal communication relationship to the signal transmission line, and a detonator output charge in initiation relation to the igniter means.
  • the timer circuit of the present invention can be permanently programmed to interpose a preselected delay between the receipt of an initiation signal and the emission of an output signal.
  • a timer circuit according to the present invention does not lose its program with power loss. Moreover, it will function properly after significant periods of non-use and can function over a wide range of operating voltages and temperatures.
  • the timer circuit of the present invention requires fewer external connection lines for its operation than conventional programmable timer circuits, has a standard unprogrammed circuit configuration and is one-time programmable to provide an output signal after a predetermined time interval from the application of the input signal. If desired, a timer circuit according to the present invention is capable of being factory-programmed to provide an electronically-controlled time delay and to obviate the need for field-programming the selected delay. Alternatively, the timer circuit can be incorporated into devices configured for programming by the end-user to permit selection of a desired delay interval in the field.
  • the timer circuit of the present invention is generally useful in any circumstances in which an electronically timed delay is required.
  • a timer circuit in accordance with the present invention can be incorporated into an electronic detonator circuit to provide an electronic firing signal after a predetermined interval following the receipt of an electronic initiation signal.
  • a series of detonator circuits constructed according to the present invention can be individually programmed with different selected time delays, to provide output signals that initiate a series of explosive charges in a precisely timed sequence.
  • detonator circuit 10 includes a power supply 12 which is capable of providing a short, high amplitude current pulse to charge a power supply capacitor (or "firing capacitor") 14.
  • a power supply capacitor or "firing capacitor"
  • One suitable type of power supply is a piezotransducer capable of converting a shock tube signal into an electrical initiation pulse, as described more fully below.
  • the power supply capacitor 14 is isolated from the power supply 12 by an ultra-fast recovery rectifier or isolation diode 16.
  • the charged power supply capacitor 14 produces an input voltage VCC which is then used to power the rest of the detonator circuit, including the timer circuit.
  • Power supply capacitor 14 is in circuit communication with an integrated circuit 18 which comprises a programmable electronic timer circuit according to one embodiment of the present invention.
  • the integrated circuit 18 includes a voltage regulator 20, a 14-stage asynchronous ripple counter 22, an oscillator 24, a 14-bit programmable array 23 and an output driver 28.
  • the integrated circuit includes a single programming input line 26 for programming the integrated circuit 18 to a predetermined logic state.
  • Counter 22 interposes a time delay between the receipt by integrated circuit 18 of an electronic initiation signal and the issuance of a timer output signal to optional output driver 28. The delay is determined by the frequency of the oscillator and the programming state of the circuit.
  • the timer output signal activates output driver 28 which then issues a firing signal.
  • the firing signal operates an electronic switch 40 such as a Darlington switch to close a branch circuit through which power supply capacitor 14 discharges through igniter 30 to fire the detonator, as discussed more fully below.
  • the voltage regulator 20 regulates the output of power supply capacitor 14 voltage down to a very stable voltage in the 2 to 5 volt range, e.g., 3 volts, which is used by the remainder of the integrated circuit 18 and which is designated VDD.
  • the voltage regulator 20 requires two external capacitors C1 and C2 to operate, i.e., capacitors that are not manufactured as part of the integrated circuit but which are connected thereto.
  • Capacitor C1 is charged to voltage VDD by voltage regulator 20 and is used as a storage device to reduce the ripple on the regulated voltage and to provide power to the remainder of the integrated circuit.
  • the second external capacitor C2 is used to bypass the current-limiting resistor 21 to allow the voltage regulator 20 to come up to operating voltage very quickly each time power is re-applied to the circuit.
  • oscillator 24 provides a stable periodic rising and falling signal to the counter 22.
  • the period of the signal is a significant factor in determining the timing range in which the circuit can be programmed to a selected time delay.
  • oscillator 24 may be an oscillator whose frequency is determined by an external timing resistor 32 and timing capacitor 34. By choosing such an oscillator, the same integrated circuit can easily be modified to vary its maximum time interval by appropriate choice of external components. However, a fixed frequency oscillator may be employed, if desired.
  • the oscillator 24 is configured to remain stable over an operational temperature range of -55°C to 65°C so that it will operate in typical outdoor applications despite variations in weather or climate. This is achieved by providing a thermally stable reference voltage.
  • the voltage regulator 20 is based on a bandgap reference which in itself is extremely temperature-stable.
  • the timer circuit comprises a standard oscillator circuit designed to operate on a current that is small enough to be insensitive to small changes in circuit performance and high enough that the oscillator maintains its bi-stable operation.
  • the oscillator circuit comprises three polysilicon resistors which act as a voltage divider to provide two threshold voltages for various branches of the oscillator circuit.
  • the resistors are chosen so that changes in these resistors over temperature offset the changes in the oscillator thresholds.
  • the careful selection of the external resistor 32 and capacitor 34 also play a major role in the oscillator performance.
  • Using a tight Temperature Coefficient Resistor and an NPO-type capacitor provides an oscillator that remains very stable over the operational temperature range of -55°C to 65°C, e.g., it may have a thermal coefficient of less than 150 ppm/°C.
  • the counter 22 comprises two or more counter stages of toggle digital flip-flops that are disposed in a cascade or ripple arrangement with intervening programming circuitry, as will be described more fully below.
  • the first counter stage is driven by the oscillator 24 and the output of the final counter stage is connected to output driver 28.
  • Output driver 28 is activated when oscillator 24 causes counter 22 to increment to a logic state determined by the configuration of programmable array 23.
  • the configuration of programmable array 23 can be determined prior to use by providing appropriate programming signals via programming line 26.
  • Figure 2 provides a conventional representation of a conventional flip-flop counter stage of the kind that may be used in counter 22 ( Figure 1).
  • the flip-flop has a VDD port for receiving power from a power supply, e.g., from capacitor C1. It also has a clock port for receiving a counter stage input signal and a reset port and associated circuitry well known in the art for setting the logic state of the flip-flop output signal to a predetermined logic state (usually to an inactive state) upon receipt of a power-on-reset signal generated by power-on-reset circuitry (not shown) well-known in the art.
  • the flip-flop also has an output port for issuing a counter stage output signal Q. There is also a second output port for issuing an inverse counter stage output signal /Q. Inverse output signal /Q is connected to an input port D to provide a conventional T-type flip-flop.
  • a conventional cascade-type counter comprises a series of flip-flop registers or "counter stages” whose output signals are all initially at the same inactive logic state (conventionally represented as "0") and which are connected so that the output Q of one counter stage is passed directly to the clock input of the next counter stage, i.e., the counter stages are arranged sequentially.
  • the output Q of a counter stage does not change until the input changes from an active state (conventionally represented as "I”) back to the original "0" inactive state.
  • the switching of the logic state of the output of each successive counter stage from inactive to active, i.e., from "0" to "1" therefore represents an exponential division by two of the number of input pulses received at the first stage of the oscillator.
  • the output of the last counter stage of a conventional four-stage (“four bit") counter toggles from “0" to "1" after 2 3 (i.e., 8) input pulses to the first counter stage, and it toggles back to "0" after 2 4 (i.e., 16) input pulses to the first counter stage.
  • the output of the last stage in any cascade counter represents the most significant bit of the counter, i.e., it represents a greater number of input pulses than any other counter stage.
  • the significance of the counter stages decreases as their logical, i.e., sequential, proximity to the first counter stage increases.
  • a timer circuit in accordance with the present invention comprises programming circuitry that comprises an electronic toggle logic gate disposed between each successive pair of counter stages, i.e., between the first and second counter stages, between the second and third counter stages, etc., as toggle logic gate 25 is shown in Figure 3A between counter stages 22a and 22b.
  • the T input ports of counter stages 22a and 22b correspond to the clock port of the flip-flop of Figure 2.
  • Counter stages 22a and 22b also have reset, ground and VDD input ports like the flip-flop of Figure 2, but to simplify the Figure, these are not shown.
  • the counter stage output signal /Q of counter stage 22a is passed to signal input B of toggle logic gate 25 which comprises gates 25a and 25b and which, during operation, also receives a program stage signal A from an associated program stage (not shown).
  • Toggle logic gate 25 produces an input signal T for the succeeding counter stage 22b.
  • the counter stage whose output is connected to a given program stage or toggle logic gate is referred to herein as the preceding counter stage with respect to that program stage and toggle logic gate; a counter stage that receives the output of the toggle logic gate as its input is referred to herein as the succeeding counter stage.
  • counter stage 22a is the preceding counter stage
  • counter stage 22b is the succeeding counter stage.
  • the counter stages are described as being sequentially arranged despite the intervening toggle logic gates.
  • toggle logic gate 25 issues to succeeding counter stage 22b an input signal having the opposite logic state from that of output signal /Q of the preceding counter stage, i.e., the toggle logic gate "inverts" signal/Q.
  • toggle logic gate 25 issues to counter stage 22b a signal having the same logic state as signal /Q, i.e., logic gate 25 passes the stage output signal /Q directly to the succeeding counter stage. Whether or not signal A has an active logic state during operation is determined by programming the timer circuit, as described below.
  • the power-on-reset circuitry At start-up, the power-on-reset circuitry generates a reset signal pulse and a latch enable signal, which are received at inputs R and LE, respectively, by the latch comprising logic gates U1 and U2. The latch then produces a signal A.
  • the state of the signal A will be determined by the state of fuse F, i.e., whether fuse F is intact or blown. If fuse F is blown, signal A will have an active logic state. If fuse F is intact, signal A will be pulled low to an inactive logic state.
  • the power-on-reset condition of the input signal for each counter stage i.e., the output of each toggle logic gate, has an inactive or "0" logic state which toggles to the active state represented as "1" only after the input to the preceding counter stage has toggled to "1" and then back to "0". Accordingly, in a sequence of n stages, the last counter stage will not toggle to "1" to activate output driver 28 until 2 (n-1) oscillator pulses have been received by the first counter stage. To reduce the number of oscillator pulses required to activate the output driver 28, appropriate fuses in the programming array must be blown by programming the timer circuit.
  • each programming stage contains a fuse switch M1 (which in the illustrated embodiment comprises a MOSFET n-channel, depletion-mode device) a fuse F connected to the source lead of fuse switch M1, and a program enable signal input PE and a counter stage input D connected to the inputs of a logic gate U8.
  • the output of gate U8 is connected to the gate of fuse switch M1, and a program signal input PVDD is connected to the drain lead of fuse switch M1.
  • One way to program the circuit is to run the counter for the desired time interval and then stop it.
  • the logic state of each counter stage output Q is sensed by the associated program stage as the input D.
  • a fuse current signal PVDD of sufficient power to blow the fuses of all the program stages is supplied to programming input line 26 from an external test device.
  • a logic level program enable command signal PE derived from PVDD, is also provided to the program stage. If the logic state of the counter stage output is inactive, logic gate U8 will not activate switch M1 and the fuse current PVDD will not blow fuse F. However, if the input D senses an output signal Q having an active logic state, logic gate U8 will activate switch M1 and fuse current PVDD will blow fuse F.
  • a disabling program signal is provided to toggle logic gate 25 ( Figure 3A) during programming to prevent any change in the logic state of the input signal to the succeeding counter stage.
  • An alternative method which requires a less powerful PVDD program signal is to run the counter up to a count at which only the most significant counter stage bit has an active logic state.
  • the program signal is applied to the programming line to blow the fuse of the program stage associated with the active counter stage.
  • the circuit is then reset and run up to the next most significant bit and the program signal PVDD is re-applied. This cycle is repeated until all the fuses of program stages that receive active signals when the counter reaches the desired logic state have been blown.
  • the power-on-reset circuit When the circuit is powered down and later re-powered for use, the power-on-reset circuit provides a signal (R) and a signal (LE) to the latch of each program stage, which comprises logic gates Ul or U2 to produce an appropriate output signal A. If the fuse of the stage is blown, the A signal will have an active logic state. If the fuse is not blown, the A signal will have an inactive logic state. The A signal is passed to the associated toggle logic gate. Thus, at start-up, some of the toggle logic gates will have an active input signal A, others will not, and they will issue input signals to their respective succeeding counter stages accordingly. As described above, a reset signal is also sent to each counter stage at power-up to set the output signals to their inactive states. In this way the timing circuit is initialized at power-up, i.e., it is disposed in a predetermined logic state that will determine the number of oscillator pulses required to activate the output driver 28.
  • the timer circuit comprises test logic gates (U3, U4 and U5) that can simulate the blown fuses prior to programming the circuit, i.e., prior to actually blowing the fuses.
  • the counter stages are set to the appropriate logic configuration, e.g., by running the counter to the desired count as described above for programming. Then, instead of providing program signal PVDD, test signals are provided to the input lines for gates U3 and U7. Gate U7 also senses the logic state of the associated counter stage output Q, which is designated input signal D.
  • test signals are maintained and the circuit is initialized so that the program stages issue output signals A in accordance with the test configuration.
  • the timer circuit may then be initiated, and the interval between initiation signal and the issuance of an output signal can be measured.
  • Power supply 12 ( Figure 1) may then be stimulated to charge the power supply capacitor 14 to its operating voltage.
  • the isolation diode 16 prevents the stored charge from dissipating back through the power supply 12.
  • the by-pass capacitor C2 forces the storage capacitor C1 to come up to desired regulator voltage very quickly.
  • the voltage regulator 20 takes over and begins to stabilize this voltage.
  • the power-on-reset circuit activates the programming section latches to their programmed logic states and causes the counter stage output signals to issue inactive output signals, thus placing the timing circuit in the desired starting logic configuration.
  • the voltage regulator has stabilized and the oscillator 24 begins to cycle.
  • the counter 22 increments in accordance with the logic configuration established by the programming circuit. After the oscillator has cycled to the appropriate count, the timer issues an output signal to output driver 28.
  • the timer output signal triggers an output driver 28 which activates a switch 40 to close a branch circuit through which firing capacitor 14 can fire igniter 30 to set off a detonator charge.
  • a typical trigger device, or igniter means may comprise a hotwire or a semiconductor bridge.
  • An output driver suitable for this purpose is diagrammed in Figure 5. It comprises two switches, one of which is activated by the timer output signal. When the output signal activates switch M2, switch M2 activates switch M3, which then applies voltage VDD from capacitor C1 to the trigger device which, in this case, is switch 40.
  • the trigger device allows capacitor 14 to discharge through igniter 30, which energizes the output charge of the detonator.
  • an electronic digital delay detonator 100 comprising a timer circuit according to the present invention.
  • the delay detonator is coupled to a suitable input transmission line which comprises, in the illustrated case, a shock tube 110.
  • a suitable input transmission line which comprises, in the illustrated case, a shock tube 110.
  • shock tube comprises hollow plastic tubing, the inside wall of which is coated with an explosive material so that upon ignition, a low energy shock wave is propagated through the tube.
  • Shock tube 110 is fitted to a suitable housing 112 by means of an adapter bushing 114 about which housing 112 is crimped at crimps 116, 116a to secure shock tube 110 and form an environmentally protective seal between adapter bushing 114 and the outer surface of shock tube 110.
  • Housing 112 has an open end 112a which receives bushing 114 and shock tube 110, and an opposite, closed end 112b.
  • Housing 112 is made of an electrically conductive material, usually aluminum, and is preferably the size and shape of conventional blasting caps, i.e., detonators.
  • a segment 110a of shock tube 110 extends within housing 112 and terminates at end 110b in close proximity to, or in abutting contact with, an anti-static isolation cup 118.
  • Isolation cup 118 is of a type well-known in the art and is made of a semiconductive material, e.g., a carbon-filled polymeric material, so that it forms a path to ground, to dissipate any static electricity which may travel along the interior of shock tube 110.
  • a low energy booster charge 120 is positioned adjacent to anti-static isolation cup 118.
  • anti-static isolation cup 118 comprises, as is well-known in the art, a generally cylindrical body (which is usually in the form of a truncated cone, with the larger diameter positioned closer to the open end 112a of housing 112) which is divided by a thin, rupturable membrane 118b into an entry chamber 118a and an exit chamber 118c.
  • the end 110b of shock tube 110 (Figure 6A) is received within entry chamber 118a (shock tube 110 is not shown in Figure 6B for clarity of illustration).
  • Exit chamber 118c provides an air space or stand-off between the end 110b of shock tube 110 and booster charge 120. In operation, the shock wave traveling through shock tube 110 will rupture membrane 118b and traverse the stand-off provided by exit chamber 118c and impinge upon and detonate booster charge 120.
  • Booster charge 120 itself comprises a booster charge shell 122 of cup-like configuration within which is pressed a small quantity of primary explosive 124, such as lead azide, which is closed by a first cushion element 126.
  • Primary cushion element 126 which is located between isolation cup 118 and primary explosive 124, protects primary explosive 124 from pressure imposed upon it during manufacture.
  • Adapter bushing 114, isolation cup 118, first cushion element 126, and booster charge 120 may conveniently be fitted into a booster shell 132 as shown in Figure 6B.
  • the outer surface of isolation cup 118 is in conductive contact with the inner surface of booster shell 132 which in turn is in conductive contact with housing 112 to provide an electrical current path for any static electricity discharged from shock tube 110.
  • booster shell 132 is inserted into housing 112 and housing 112 is crimped to retain booster shell 132 therein as well as to protect the contents of housing 112 from the environment.
  • a capacitor 134 is connected to piezoelectric generator 130 to receive electrical output from generator 130 for storage.
  • Capacitor 134 may be a 10 micro-farad unit rated at 35 volts. Its series resistance is preferably low to accommodate the fast rise time of the 1 to 2 microsecond-long pulses it will receive from piezoelectric generator 130.
  • a battery means 136 is positioned next to capacitor 134 and adjacent to battery means 136 is a timing module 138 next to which is located an electrically activated igniter means 140.
  • a second cushion element 142 which is similar to first cushion element 126, is interposed between output charge 144 and an electrically activated igniter means 140 for the same purpose as first cushion element 126.
  • Output charge 144 comprises a primary explosive 144a and a secondary explosive 144b, which has sufficient shock power to detonate cast booster explosives, dynamite, etc., the detonation of which is the usual purpose to which detonators are put.
  • Igniter means 140 which is connected to the output of timing module 138, when energized detonates primary explosive 144a, which in turn detonates secondary explosive 144b, i.e., igniter means 140 serves to detonate output charge 144.
  • Igniter means 140 is positioned within a preferably non-conductive bushing (not shown) which serves to prevent inadvertent detonation of output charge 144 by igniter means 140 by virtue of the relatively low resistivity of the bushing and its contact with housing 112.
  • housing 112 The components contained within housing 112 are suitably encased within potting compounds to protect the components and to minimize the chances of detonation or damage by mechanical impact or electrical signals.
  • housing 112 is made of aluminum or other electrically conductive material also helps to shield the internal components against both electrical signals and mechanical shocks that could inadvertently activate booster charge 120 or output charge 144.
  • the electrically conductive housing 112 provides a high degree of attenuation of potentially damaging electrical fields by forming a Faraday cage around the electrically sensitive components.
  • the size and configuration of the housing 112 is, as noted above, preferably selected to duplicate industry standard detonator sizes currently in use.
  • the digital delay detonator 100 of Figure 6A receives a pressure input pulse via shock tube 110 which detonates booster charge 120, the explosive output of which is thus an amplification of the pressure input pulse delivered by shock tube 110.
  • Piezoelectric generator 130 is subjected to the energy delivered by the explosion of booster charge 120 and converts the energy into electrical energy.
  • This electrical energy is stored in storage capacitor 134 and a part of it is used to activate the timing circuit of timing module 138 and, after lapse of a preselected interval, to energize igniter means 140 to detonate output charge 144.
  • Battery means 136 is used to supply the necessary power to operate the delay timing circuitry of timing module 138.
  • the stored energy from capacitor 134 is applied to electrically activated igniter means 140, thereby detonating primary explosive 144a and secondary explosive 144b.
  • the delay detonator 100 may thus be employed to provide a very accurately controlled delay in the initiation of an explosive charge as may be required in blasting patterns in which a large number of charges are to be detonated in a predetermined timing pattern.
  • the electronic circuit control of the delay permits much more accurate delays than those which are attainable by conventional pyrotechnic delays, and the battery-powered timing means permits the selection of much longer delays than would be attainable if the piezoelectric generator 130 had to supply the power for both powering the timing circuits and energizing the igniter means 140.
  • shock tube 110 of the Figure 6A embodiment may be replaced by a transmission line comprising a low energy detonating cord.
  • the energy output of the detonating cord is selected to be low enough so as not to destroy the components of the delay detonator to prevent it from functioning, but high enough to cause the input impulse signal provided by the explosive output of low energy detonating cord to act, without need for amplification, directly on the piezoelectric generator. Consequently, booster charge 120 of the Figure 6A embodiment may be omitted from a detonating cord embodiment, as may isolation cup 118, for which there would be no need. Otherwise, the other parts of a detonating cord embodiment, their arrangement and operation, are the same as those discussed in conjunction with the embodiment of Figure 6A and it is therefore not necessary to repeat the illustration and description thereof.
  • the piezoelectric generator 130 comprises a piezoceramic material stack 150 comprised of a stack of multiple layers 151 of thin piezoceramic material.
  • the stack 150 is supported on a suitable plastic (synthetic organic polymeric material) housing 153, through which terminals 168A and 168b ( Figure 8) extend.
  • the output energy from the booster charge 120 impinges substantially directly upon a load distributing disc 170 (not shown in Figures 6A or 6B), which in turn evenly transmits the energy from the booster charge 120 to the multiple layers 151 of suitable thin piezoceramic material which comprise one embodiment of the stack 150 of piezoelectric generator 130.
  • the piezoceramic material layers 151 are stacked in vertical layers with opposite faces of each layer connected in parallel through the use of electrode layers 172a and 172b interposed between each layer or element 151.
  • the piezoelectric generator of the present invention uses 184 active layers, each approximately 20 microns thick, with discrete positive and negative electrodes as marked on Figure 9 formed from the inner connections. This construction provides output energy levels much greater than those which can be obtained from an otherwise comparable monolithic piezoceramic structure.
  • the plastic housing 153 and load distributing disc 170 contribute, in a preferred structure of the present invention, to obtaining the maximum benefit from the output shock wave of the booster charge 120 and the physical pressure attendant thereto.
  • the stack 150 of piezoelectric generator 130 is mounted to a smooth, flat and hard surface 153a of plastic housing 153 ( Figure 8).
  • Surface 153a is substantially parallel to the shock wave front generated by detonation of booster charge 120 and perpendicular to the direction of shock wave travel.
  • the load distributing disc 170 is disposed substantially parallel to and between the output end of the booster charge 120 and the input face of the piezoelectric generator 130 to evenly transmit and distribute the output shock wave energy of the booster charge 120 to the piezoelectric generator 130. This arrangement also helps to prevent premature shattering of the piezoelectric generator 130 which would render it inoperable. Terminals 168a and 168b are electrically connected to electrode layers 172a and 172b to establish the desired electrical connection to the timing module 138 ( Figure 6A). Plastic housing 153 and load distributing disc 170 also serve to insulate piezoelectric generator 130 against unintended and random mechanical forces, any electrical charges, etc., and serves to help maintain the piezoelectric generator in the desired position.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Programmable Controllers (AREA)
  • Measurement Of Predetermined Time Intervals (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Pulse Circuits (AREA)
EP96911525A 1995-04-10 1996-04-01 Programmable electronic timer circuit Expired - Lifetime EP0828988B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US420991 1982-09-21
US08/420,991 US5621184A (en) 1995-04-10 1995-04-10 Programmable electronic timer circuit
PCT/US1996/004471 WO1996033384A1 (en) 1995-04-10 1996-04-01 Programmable electronic timer circuit

Publications (3)

Publication Number Publication Date
EP0828988A1 EP0828988A1 (en) 1998-03-18
EP0828988A4 EP0828988A4 (en) 1998-07-08
EP0828988B1 true EP0828988B1 (en) 2000-11-22

Family

ID=23668726

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96911525A Expired - Lifetime EP0828988B1 (en) 1995-04-10 1996-04-01 Programmable electronic timer circuit

Country Status (16)

Country Link
US (1) US5621184A (hu)
EP (1) EP0828988B1 (hu)
JP (1) JP3027611B2 (hu)
AR (1) AR001591A1 (hu)
BR (1) BR9609672A (hu)
CA (1) CA2215326C (hu)
DE (1) DE69611038T2 (hu)
ES (1) ES2155935T3 (hu)
IN (1) IN188382B (hu)
MX (1) MX9707789A (hu)
MY (1) MY113591A (hu)
NO (1) NO974663L (hu)
PE (1) PE46397A1 (hu)
RU (1) RU2129295C1 (hu)
WO (1) WO1996033384A1 (hu)
ZA (1) ZA962523B (hu)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6079332A (en) * 1996-11-01 2000-06-27 The Ensign-Bickford Company Shock-resistant electronic circuit assembly
US6199484B1 (en) 1997-01-06 2001-03-13 The Ensign-Bickford Company Voltage-protected semiconductor bridge igniter elements
US5899570A (en) * 1997-03-28 1999-05-04 Microchip Technology Incorporated Time-based temperature sensor system and method therefor
AU732234B2 (en) * 1997-06-19 2001-04-12 Detnet International Limited Electronic circuitry for timing and delay circuits
AU758460B2 (en) * 1997-06-19 2003-03-20 Detnet International Limited Electronic circuitry for timing and delay circiuts
US5912428A (en) * 1997-06-19 1999-06-15 The Ensign-Bickford Company Electronic circuitry for timing and delay circuits
US20060086277A1 (en) 1998-03-30 2006-04-27 George Bossarte Precision pyrotechnic display system and method having increased safety and timing accuracy
AU5202099A (en) * 1998-03-30 1999-11-08 Magicfire, Inc. Precision pyrotechnic display system and method having increased safety and timing accuracy
KR20010072266A (ko) * 1998-08-13 2001-07-31 추후보정 폭파설비
JP3061043B2 (ja) * 1998-12-11 2000-07-10 日本電気株式会社 電源回路
DE19949842B4 (de) * 1999-10-15 2005-11-03 Siemens Ag Zündeinrichtung für eine pyrotechnische Insassenschutzeinrichtung
ES2176060B1 (es) * 1999-10-27 2004-02-01 Instalaza Sa Mejoras en espoletas mecano-electronicas para granadas de mano.
US6324979B1 (en) * 1999-12-20 2001-12-04 Vishay Intertechnology, Inc. Electro-pyrotechnic initiator
US6584907B2 (en) 2000-03-17 2003-07-01 Ensign-Bickford Aerospace & Defense Company Ordnance firing system
CA2427147C (en) * 2000-11-09 2008-12-30 Orica Explosives Technology Pty Ltd Sensor for monitoring electronic detonation circuits
WO2002079717A2 (en) * 2001-02-14 2002-10-10 The Ensign-Bickford Company Delay detonator timing circuit
AU2003243539A1 (en) * 2002-06-12 2003-12-31 Ensign-Bickford Aerospace And Defense Company Signal transfer device
US7213518B2 (en) 2003-02-21 2007-05-08 Engel Ballistic Research, Inc. Modular electronic fuze
US7874250B2 (en) * 2005-02-09 2011-01-25 Schlumberger Technology Corporation Nano-based devices for use in a wellbore
US8079307B2 (en) 2005-10-05 2011-12-20 Mckinley Paul Electric match assembly with isolated lift and burst function for a pyrotechnic device
US8701559B2 (en) * 2006-01-17 2014-04-22 Omnitek Partners Llc Energy harvesting power sources for detecting target impact of a munition
US20080282925A1 (en) * 2007-05-15 2008-11-20 Orica Explosives Technology Pty Ltd Electronic blasting with high accuracy
US8477049B2 (en) * 2009-06-05 2013-07-02 Apple Inc. Efficiently embedding information onto a keyboard membrane
US8448573B1 (en) * 2010-04-22 2013-05-28 The United States Of America As Represented By The Secretary Of The Navy Method of fuzing multiple warheads
RU2451896C1 (ru) * 2010-11-10 2012-05-27 Открытое акционерное общество "Новосибирский институт программных систем" Капсюль-детонатор
EP2818823A4 (en) * 2012-02-22 2015-09-30 Obshchestvo S Ogranichennoy Otvetstvennostyu Pulse Electric detonator
CN105652703B (zh) * 2014-11-24 2018-06-19 中国科学院沈阳自动化研究所 一种可以自动计算延时的定时器电路及方法
WO2016171581A1 (ru) * 2015-04-24 2016-10-27 САЯПИН, Виталий Викторович Капсюль - детонатор
RU2636831C1 (ru) * 2016-10-10 2017-11-28 Виталий Борисович Шепеленко Электродетонатор с электромеханической блокировкой
RU2634951C1 (ru) * 2016-10-10 2017-11-08 Владимир Викторович Черниченко Устройство инициирования
RU2634947C1 (ru) * 2016-10-10 2017-11-08 Владимир Викторович Черниченко Электродетонатор
RU2634949C1 (ru) * 2016-10-10 2017-11-08 Виталий Борисович Шепеленко Электродетонатор безопасного обращения
RU2642696C1 (ru) * 2016-10-10 2018-01-25 Владимир Викторович Черниченко Контактный датчик цели
RU2634941C1 (ru) * 2016-10-10 2017-11-08 Виталий Борисович Шепеленко Контактный датчик цели
CN109341446B (zh) * 2018-11-26 2020-11-06 无锡矽微智能科技有限公司 一种用于电子雷管的命令识别装置和方法以及延时装置和方法
CN113006757B (zh) * 2021-02-25 2022-12-20 三一石油智能装备有限公司 电驱压裂橇系统中辅助电机设备控制方法、装置及压裂橇

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3533088A (en) * 1967-10-31 1970-10-06 Rca Corp Control circuit for memory
US3955069A (en) * 1972-09-28 1976-05-04 General Electric Company Presettable counter
US3851589A (en) * 1973-04-25 1974-12-03 Texaco Inc Electronic delay blaster
US5042386A (en) * 1974-09-27 1991-08-27 The United States Of America As Represented By The Secretary Of The Navy Destructive device for metal oxide-semiconductors
US4222226A (en) * 1978-02-14 1980-09-16 Fuji Electric Co., Ltd. Multi-range timer
US4445435A (en) * 1980-05-05 1984-05-01 Atlas Powder Company Electronic delay blasting circuit
DE3332530C2 (de) * 1982-12-21 1985-11-28 Kriegeskorte & Co Gmbh, 7000 Stuttgart Zündeinrichtung für Patronen, insbesondere Handfeuerwaffen-Patronen
US4712477A (en) * 1985-06-10 1987-12-15 Asahi Kasei Kogyo Kabushiki Kaisha Electronic delay detonator
US4869171A (en) * 1985-06-28 1989-09-26 D J Moorhouse And S T Deeley Detonator
US4825765A (en) * 1986-09-25 1989-05-02 Nippon Oil And Fats Co., Ltd. Delay circuit for electric blasting, detonating primer having delay circuit and system for electrically blasting detonating primers
US4897860A (en) * 1988-03-02 1990-01-30 Dallas Semiconductor Corporation Programmable time base circuit with protected internal calibration
US4960033A (en) * 1988-12-27 1990-10-02 Electro-Tech, Inc. Gun firing relay circuit
JPH0468562A (ja) * 1990-07-10 1992-03-04 Nec Corp コード設定回路
US5151611A (en) * 1990-12-10 1992-09-29 Westinghouse Electric Corp. Programmable device for integrated circuits
US5173569A (en) * 1991-07-09 1992-12-22 The Ensign-Bickford Company Digital delay detonator
US5363765A (en) * 1993-03-12 1994-11-15 Asahi Kasei Kogyo Kabushiki Kaisha Electronic delay circuit for firing ignition element
US5460093A (en) * 1993-08-02 1995-10-24 Thiokol Corporation Programmable electronic time delay initiator

Also Published As

Publication number Publication date
AU690451B2 (en) 1998-04-23
MX9707789A (es) 1997-12-31
US5621184A (en) 1997-04-15
EP0828988A1 (en) 1998-03-18
DE69611038T2 (de) 2001-03-22
IN188382B (hu) 2002-09-14
BR9609672A (pt) 1999-07-06
ES2155935T3 (es) 2001-06-01
JPH10510915A (ja) 1998-10-20
ZA962523B (en) 1996-10-07
PE46397A1 (es) 1997-11-23
NO974663D0 (no) 1997-10-09
MY113591A (en) 2002-04-30
EP0828988A4 (en) 1998-07-08
NO974663L (no) 1997-12-08
DE69611038D1 (de) 2000-12-28
AR001591A1 (es) 1997-11-26
RU2129295C1 (ru) 1999-04-20
JP3027611B2 (ja) 2000-04-04
CA2215326A1 (en) 1996-10-24
CA2215326C (en) 2000-11-14
WO1996033384A1 (en) 1996-10-24
AU5438996A (en) 1996-11-07

Similar Documents

Publication Publication Date Title
EP0828988B1 (en) Programmable electronic timer circuit
US5435248A (en) Extended range digital delay detonator
US6268775B1 (en) Dual capacitor oscillator circuit
US4843964A (en) Smart explosive igniter
AU645731B2 (en) Digital delay detonator
US6082265A (en) Electronic delay detonator
JPH0324094B2 (hu)
US4136617A (en) Electronic delay detonator
US6401621B1 (en) Electronic safe and arm apparatus for initiating a pyrotechnic
AU690451C (en) Programmable electronic timer circuit
WO2002079717A2 (en) Delay detonator timing circuit
AU758460B2 (en) Electronic circuitry for timing and delay circiuts
AU732234B2 (en) Electronic circuitry for timing and delay circuits
Bickes Jr et al. Smart explosive igniter
Patil et al. Intelligent Ordnance Initiation System
MXPA99011418A (en) Electronic circuitry for timing and delay circuits

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19970911

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE ES FR GB SE

A4 Supplementary search report drawn up and despatched

Effective date: 19980525

AK Designated contracting states

Kind code of ref document: A4

Designated state(s): DE ES FR GB SE

RA4 Supplementary search report drawn up and despatched (corrected)

Effective date: 19980604

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 20000125

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE ES FR GB SE

REF Corresponds to:

Ref document number: 69611038

Country of ref document: DE

Date of ref document: 20001228

ET Fr: translation filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20010401

REG Reference to a national code

Ref country code: ES

Ref legal event code: FG2A

Ref document number: 2155935

Country of ref document: ES

Kind code of ref document: T3

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20010401

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: ES

Payment date: 20050527

Year of fee payment: 10

REG Reference to a national code

Ref country code: FR

Ref legal event code: TP

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060403

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 20070427

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20070531

Year of fee payment: 12

REG Reference to a national code

Ref country code: ES

Ref legal event code: FD2A

Effective date: 20060403

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20070417

Year of fee payment: 12

EUG Se: european patent has lapsed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20081101

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20081231

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080402