MXPA99011418A - Electronic circuitry for timing and delay circuits - Google Patents

Abstract

An electronic delay circuit (10) useful for the delayed initiation of detonators illustrates several novel features that may be combined, including a novel oscillator (34), a programmable timer circuit (32) and a run control circuit (46). The oscillator (34) generates a clock signal determined by the rate of discharge of a capacitor (34a) relative to a reference voltage REF. A second capacitor (34b) is charged to a voltage that exceeds REF, and when the first capacitor (34a) falls below REF, an internal signal is generated and the capacitors are switched, so that the first capacitor gets charged while the second is discharged. A latch (34f) produces clock pulses in response to the internal signals. The programmable timer circuit (32) includes a ripple counter (38) and a program bank (40) that loads a count in the counter upon initialization. Each stage of the counter (38) has separate inputs for set and clear signals, and the program bank (40) has a setting circuit and a clearing circuit for each counter stage. Each clearing circuit generates a signal of fixed duration and each setting circuit can generate a signal of two different durations, one of which exceeds the clear signal. During programming, the set signal of short or long duration is chosen and, in loading the counter, the longer of the set signal or the clear signal determines the state of the counter stage. The run control circuit (46) controls a gate (34h) that permits oscillator pulses to increment the counter (38), but closes gate (34h) should a temporary loss in power occur thus preventing the timer (32) from being re-initialized.

Description

ELECTRONIC CIRCUITERIA FOR REGULATION AND DELAY CIRCUITS DESCRIPTION OF THE INVENTION The present invention pertains to electronic delay detonators and in particular, to programmable electronic initiation delay detonators. Electronic detonators are known for use in initiating explosive charges, for example for initiating impulse loads used in mining and excavation applications. Such detonators are known for their precise delay characteristics in relation to the delay units based on more traditional chemical products. U.S. Patent No. 5,377,592 to Rodé et al, dated January 3, 1995, discloses an electronic digital delay unit powered by an energy pulse generated by a piezoelectric transducer in response to an impulse type initiation signal. The initiation signal stimulates the piezoelectric transducer to create a charge of electrical energy that is stored in a storage capacitor. The energy is extracted from the storage capacitor to operate a timer circuit comprising an oscillator and a counter that counts the oscillation pulses from the oscillator to a predetermined count. When the predetermined count is reached, a signal is generated to discharge the remaining energy of the storage capacitor to the electric ignition element, for example, an explosion cursor wire. The detonator may be equipped with an externally accessible programming interface such that the timer circuit may be programmed with a delay after the detonator is constructed. U.S. Patent 5,435,248 to Rodé et. al., dated July 25, 1995, discloses an electronic range digital delay detonator comprising fuse links that are used to permanently program a desired function delay within the detonator circuit. Electronic detonators of the type described in the aforementioned US Patent 5,435,248 and US Patent 5,377,592 comprise conventional oscillators and counters. The present invention provides several novel features that find utility in electronic delay detonators. A feature of the present invention relates to an oscillator circuit for generating a clock signal comprising a series of clock pulses. The oscillator circuit comprises reference voltage means for producing a reference voltage. There are at least two capacitors in the oscillator, each capacitor having one of a charged state and a discharged state in relation to the reference voltage. "A capacitor in the discharged state has a lower voltage than the reference voltage and is designated as a discharged capacitor and a capacitor in the charged state has a voltage that exceeds the reference voltage y. It is designated as a charged capacitor. There are charging means for charging a capacitor discharged to a charged state and discharge means for discharging a charged capacitor, designed as a charged working capacitor, to a discharged state. The oscillator further comprises a comparator, to generate an internal signal each time a charged working capacitor becomes a discharged capacitor. Switching means exist to execute a switching function to execute a switching function comprising effectively disconnecting a capacitor discharged from the discharge means and connecting it to the charging means, and effectively disconnecting a charged capacitor from the means charge and connect it to the discharge media; and a retention circuit for emitting a clock pulse in response to internal signals. The switching means can respond to the holding circuit to execute the switching function in response to the clock pulses emitted by the holding circuit The invention also relates to a programmable electronic timer circuit for outputting an output signal. of timer after the completion of a programmed time delay following the reception of an electrical initiation signal The timer circuit comprises a cyclically disconnected oscillator circuit (optionally as referred to above), for emitting, in response to a clock activation signal, a clock signal comprising a series of clock pulses, and a reset circuit for generating a power ON RESET signal. The timer also comprises an initializable jitter counter configured to count the clock pulses and to produce the timer output signal when a predetermined count is reached. The fluctuation counter comprises a plurality of sequential counter stages each capable of having either one of the set state and one erase state and comprising an adjustment input by which the status of the counter stage can be adjusted and an input Delete by which the status of the counter stage can be erased. Each counter stage further comprises at least one output for a single "counter stage signal indicating the state of the counter stage." The timer circuit further comprises a program bank comprising an adjustment circuit and an associated clearing circuit. with each counter stage Each setting circuit provides a signal to the setting input of the associated counter input in response to a counter load signal from a control circuit and each clearing circuit provides a signal to the input of the counter. erasing the counter stage in response to a counter charge signal and a RESET ON signal The erasing circuit produces a time-bound signal, although the adjustment device is configured to provide a signal having two different defined durations , one of which exceeds the duration of the clearing circuit signal.The associated counter stage can receive signals to the circuit and the erase circuit simultaneously and the counter stage is configured so that the longest signal determines the initial state of the counter stage. The timer circuit further comprises a control circuit which responds to an ignition RESET signal and an electrical initiation signal for emitting the counter load signal (RST) and the clock activation signal (CLKEN). In accordance with one aspect of the invention, each adjustment circuit may comprise non-volatile program means that can be adjusted to conform the adjustment circuit that provides the signal of greater duration than the signal of the erase circuit. Optionally, each adjustment circuit may comprise a "programming input" and a data input, wherein the state of the non-volatile program means is determined by the state of the data signal when a programming signal is received at the program activation input In accordance with another aspect of the invention, the non-volatile program means may comprise an EEPROM cell In accordance with a further aspect of the invention, the counter stage outputs may be connected to the inputs of the associated setting circuit program so that each counter stage can provide a data signal for the associated adjustment circuit The present invention also provides an electronic closing timer circuit, which may or may not be programmable as described above, to emit a timer output signal after the completion of a delay followed by the reception of an electric initiation signal. This timer circuit comprises an oscillator circuit (optionally as described above) which responds to a RESET signal, to emit at least one reference clock signal comprising a series of reference clock pulses. A jitter counter is configured to count the reference clock pulses to produce a timer output signal _ when a predetermined count is reached. There is a clock input through which the jitter counter receives the reference clock pulses when the clock input receives, a CLKEN signal. There is also a control circuit comprising a control bank containing three control stages connected in the form of jitter. The three control stages comprise a closing control stage, a countercharge control stage and a clock activation control stage, and each control stage is able to have either one of an adjustment state and a status of erased and responding to a RESET signal that initializes each control stage to the erased state, each control stage having an output that provides a signal indicating the status of the control stage. The control circuit further comprises an input control circuit that generates a CLKEN signal when the clock activation control stage generates an adjustment signal. The control circuit further comprises a programmable non-volatile closing circuit capable of having either one of an adjustment state and a deletion state. The closing switch circuit is driven to the setting state in response to the output signal from the closing control stage and assumes a clearing state in response to at least one programming signal. The closing switching circuit has an output connected to the logic input of the closing control stage and is configured to supply a signal to the logic input of the closing control stage only when the closing circuit is in a state of deletion when it receives the initiation signal. In this way, the closing switch circuit activates the counterload control stage, subsequently the clock activation stage. The closing control stage provides a signal to the closing switch circuit to prevent the closing switch circuit from restarting the control bank until the closing switch circuit is restored. According to another aspect of the invention, a timer circuit as described above can be incorporated * into a transducer circuit assembly. Such an assembly comprises a transducer module for converting an impact wave pulse into an electric power pulse and an electronic module secured to the transducer module. The electronic module comprises a delay circuit and an initiation element. The delay circuit comprises storage means connected to the transducer module for receiving and storing the electrical energy from the transducer module, a switching circuit that connects the storage means to an initiation element for releasing the energy stored in the storage means towards the initiation element in response to a signal from a delay portion comprising a timer circuit as described above. The timer circuit is operatively connected to the switch circuit to control the release of the initiation element by the switching circuit of the energy stored in the storage means. The initiation element is operatively connected to the storage means through the switching circuit to receive the energy from the storage means and to generate an output initiation signal in response to it. One or more of the following features may be incorporated in a detonator. Such a detonator may comprise, for example a housing having a closed end and an open end, the open end which is sized and configured for connection to initial signal transmission means.; means for transmitting initiation signal in the housing to provide an electrical initiation signal to the input terminal of a delay circuit; a power source for providing power to initiate the exit initiation means; a delay circuit in the housing comprising, as described in. present, detonator outlet means positioned in the housing to generate an explosive output signal upon discharge of the storage means. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic block diagram of a digital delay circuit according to a particular embodiment of the present invention; the Figure 2A is a schematic block diagram of the start circuit of the circuit of Figure 1; Figure 2B is a schematic circuit diagram of a particular mode of the start control circuit of Figure 2A; Figure 3A is a schematic block diagram of the oscillator circuit portion of the circuit of Figure 1; Figure 3B is a schematic circuit diagram of a particular embodiment of the oscillator circuit portion of Figure 3A; Figure 3C is a circuit diagram of a mode of comparator 34e of Figure 3B; Figure 3D is a circuit diagram of one embodiment of the diversion circuit 34s of Figure 3B; Figure 4A is a schematic block diagram of a programmable counter according to a particular mode of the counter portion of the circuit of Figure 1; Figure 4B is a schematic diagram of a counter stage and an associated setting circuit and the erase circuit according to a particular mode of the counter of Figure 4A; Figure 4C is a circuit diagram of an alternative embodiment of a programmable counter setting circuit of Figure 4A; Figure 5 is a partial cross-sectional perspective view of a transducer circuit assembly comprising an electronic module and a sleeve together with a transducer module; Figure 6A is a partially cross-sectional, schematic view showing a delay detonator comprising an encapsulated delay circuit _ according to an embodiment of the present invention; and Figure 6B is an enlarged view, relative to Figure 6A, of the isolation bowl and the impulse charge components of the detonator of Figure 6A. The electronic circuitry according to the present invention comprises an initiation delay circuit having one or more novel aspects which, in so far as they can be used independently of one another in the detonator delay circuits and in another The circuitry is preferably combined in a single circuit as described below: A schematic representation of the electronic initiation delay circuit that may incorporate one or more of the features of the present invention is provided in FIG. initiation delay 10 is powered by a storage capacitor 14 that takes its charge from the output of a piezoelectric transducer 12. Piezo transducer 12 is well known in the art for producing an electrical power pulse in response to a pressure pulse that can be supplied by, for example, a transmission signal line of the electric as detonating cord or shock tube or by a small charge of explosive material. The electrical energy produced by the transducer 12 provides an electrical initiation signal to the delay circuit 10_ at the input terminal 18a. The majority of the energy is stored by the storage capacitor 14, which subsequently provides the electrical energy for the energy initiation delay circuit 10 and for activating the electric initiation element such as the semiconductor bridge ("SCB") 16 connected to the circuit 10. Semiconductor bridges are well known in the art for use in the start charges of the initiation detonator. The transducer and the capacitor allow the delay circuit of the present invention to be used with non-electrical initiation signal lines although, in alternative embodiments, the circuit may be connected to an electric initiation system, i.e. one in which the initiation signals and, optionally, energy are transported to the detonator as electrical signals as • length of fuse cables. Non-electric signal transmission lines are preferred over 5 fuse cables where it is desired to avoid electromagnetic signal interference from __radio waves, parasitic earth current, lighting, etc. As can be seen, the pressure pulse that stimulates the piezoelectric transducer 12 may comprise an initiation signal from the which the circuit measures a delay and activates the detonator. In a typical embodiment, the detonator delay circuit 10 is assembled in two. main components, an activation portion 18 and a delay portion 28, both comprising component circuits. The portion of Activation 18 can extract the energy from a power source, for example, a storage capacitor 14 and can provide a path through which the capacitor 14 can receive the pulse of electrical energy from the piezoelectric transducer 12, for example , by meters of an address diode 20 which inhibits the backflow of current to the transducer 12. Preferably, the storage capacitor 14 comprises a 0.5 microfarad capacitor capable of providing 4 microampers for at least 10 seconds. In an alternative modality, the activation portion 18 can extract energy from a battery. The activation portion 18 provides a controllable trigger function that inhibits energy from a power source from the initiation of the electrical initiation element until a trigger signal is received from the delay portion 28, which indicates that it has passed. the desired delay interval. The activation control function can be provided mainly by means of a switching element such as a silicon controlled rectifier ("SCR") 22 through which the power source, for example, storage capacitor 14 is connected to SCB 16. In the illustrated embodiment, the switching element prevents discharge of the capacitor 14 to the output terminal 18b and hence to SCB 16 until a signal is received from the trigger control circuit 24. The trigger control circuit 24 it extracts SCR 22 within a conducting state in response to an activation signal from the delay portion 28 indicating that the desired delay interval has elapsed. The activation portion 18 preferably also comprises a voltage regulator 26 which extracts part of the energy from the capacitor 14 to provide the energy for the delay portion 28 of the detonator delay circuit 10. The activation portion 18 preferably also comprises a fixed voltage circuit 30 which generates a signal of approximately 12 volts, designated PROGP, which is provided to the delay portion 28 through the input 42c upon receipt of an initiation signal. The PROGP signal is used by the delay portion 28, as described below. The activation portion 18 is also configured to produce an energy signal VDD "of approximately 5 volts, derived from the power source, upon receipt of the initiation signal Preferably, the activation portion 18 is manufactured as an integrated microcircuit. of dielectrically isolated bipolar metal oxide silicon (DI BiCMOS) since such circuitry is adapted to control signals of the magnitude required to power the circuit and to reliably turn on the initiation element. a standard CMOS microcircuit (complementary metal oxide silicon) Preferably, the delay portion 28 is fed from the voltage regulator 26 of the activation portion 18 through the input 42f to a voltage level designated VDD (usually from around 5 volts) (sometimes referred to herein as "VDD signal"). After a predetermined delay following the reception of the ignition signal VDD at the input 42f, the delay portion 28 generates an activation signal on the output pin 42d which is conveyed to the activation control circuit 24 of the activation portion 18 to allow SCR 22 to power SCB 16. Preferably, delay portion 28 comprises several component circuits, including a timer circuit 32 for measuring the delay interval. The timing circuit 32 of the delay portion 28 comprises an oscillator 34 and a counter 36. Preferably, the timer circuit 32 is programmable and the counter 36 comprises a jitter counter 38 and a program bank 40 that can adjust the initial value of the jitter counter 38. The delay portion 28 preferably also includes a start control circuit 46 which, after receiving the PROGP signal, prevents the timer circuit 32 from being reset after a loss of transient energy. The delay portion 28 preferably operates in two modes: a programming mode in which the delay interval to be counted by the circuit is determined and a delay mode in which the delay interval that is turned on in the VDD voltage level from the activation portion 18. The delay portion 28 operates in its delay mode unless other particular signals of the appropriate voltage are provided in the start control circuit 46, as described below. As indicated in the foregoing, a feature of the present invention relates to a start control circuit 46 that generates signals that control ignition restoration, start sequencing and control of other functions of the detonator delay circuit. For example, as will be described more fully below, the start control circuit 46 ensures that once the timer circuit 32 has been counted in the delay mode, it will not be reset after a loss of transient energy. Accordingly, the start control circuit 46 will prevent ignition of the detonator due to a loss of transient energy that threatens the accuracy of the delay interval as described below. The start control circuit 46 can be understood by reference to the schematic illustration thereof in Figure 2A. The start control circuit 46, in the illustrated embodiment, comprises a control ignition restoration circuit ("POR") 46a that responds to the delay portion 28 that is powered at the voltage level VDD. The POR circuit 46a is also responsible for overcoming a RESET signal generated by the restore generation circuit 48 (Figure 1) which is used to program the timer 32 when the delay portion 28 is in the programming mode, as described later. The POR circuit 46a responds to the VDD signal and to overcome the RESET, as described below, by generating a RESET START signal that is transported, for a limited time, to the oscillator 34 and to each stage of a bank. control comprising at least after control stages 46b, 46c and 46d. Preferably. every 5 control stage is configured to have a single data input and two outputs, that is, Normal and Inverted outputs. The control stage 46b is referred to as the closing control stage, the control stage 46c is referred to as the countercharge control stage and the control stage 46d is referred to as the activation control stage of • clock. The RESET START signal generated by the POR circuit 46a clears each of the control stages by adjusting the normal output of each control stage to an inactive or lower logic state and starts the oscillator 34, as shown in FIG. will describe later. The control stages 46b, 46c and 46d are connected together in a wavy fashion to carry one signal to the next according to a • clock signal CLK2A provided by the oscillator 34. The start control circuit 46 comprises Furthermore, a closing switch circuit 46e is configured to receive the input signals from the closing control stage 46b and, from the sources outside the microcircuit, a PROGP signal at the input 42c (Figure 1) and a V18 signal. The PROGP signal is received at the 42c input after the activation portion 18 receives the electrical initiation signal and the input signal V18, which is used during programming, as described below. The latch switch circuit 46e comprises a latch cell (described further below) which may have either an active state or an inactive state. The closing cell is not volatile, which means that its state will be retained even in the case of loss of "power" for any part of the timing circuit 10, and only changes to the reception of the closing switching circuit 46e of particular signals as For example, the latch switch circuit 46e may comprise an electrically programmable, but erasable, non-volatile read-only memory cell (EEPROM). The latch switch circuit ~ 46e is configured such that when the delay 28 is energized by the VDD signal for the first time after being programmed, the closing cell will be in its active state and the initial state of the line closure signal 46g "will be active. The two outputs of the control stage 46b are provided for the closing switch circuit 46e as described below, and the normal output of the control stage 46b is additionally provided to the input of the counter load stage 46c. The normal output of the counter charge control stage 46c is not only connected as an input of the clock activation control stage 46d, but is also provided as a counter load reference signal RST to the timer, as it will be described later. Upon receipt of an active input signal from the counter charge control stage 46c, the clock activation control stage 46d generates an active output signal on its normal output which is provided as an input to the activating limiter circuit 46f and an inactive output signal RESET START Z on its inverted output. The inactive signal RESET START Z releases the circuit • Ignition restoration 54 (Figure 1), thereby allowing an activation signal to be provided to the activation portion 18 after the predetermined delay interval. The activating limiter circuit 46f receives the output of the clock activation control stage 46d and, from a source to be described later, a signal F designated HV, which is provided when the delay portion 28 is placed into the programming mode. The activating limiter circuit 46f emits an activating signal of the CLKEN clock when it receives an active signal from step 46d, unless it receives an active HV signal. Therefore, the trigger limiting circuit 46f is deactivated by an active HV signal. Upon activation of the delay portion 28 in the delay mode, the closing signal on the line 46g will be placed in its active state and the POR circuit 46a erases the control stages 4ßb, 46c and 46d, ie its normal outputs are inactivated. Once the POR 46a circuit is deactivated and the RESET START signal is inactive, the closing control stage 46b responds to the reception of a clock signal pulse CLK2A, ie, "timestamp", by generating the normal output signal Q that follows the logic state of the closing signal on the line 46g. This change in the normal output of the control stage 46b from inactive to active clears the closing cell, ie places the cell in the inactive state, although the closing switching circuit 46 will maintain an active closing signal on the line 46g in so long as the POR 46a circuit does not generate a subsequent RESET START signal. The active normal output of the closing control stage 46b on the line 46j on the next clock pulse will activate the output from the counter charge control stage 46c. The active output from step 46c provides the RST signal and an active input to the clock activation control stage 46d. With an active input, the next clock pulse will cause step 46d to provide an active signal to enable the limiter circuit 46f over the normal output. The activating limiting circuit 46f then produces the active clock activation signal CLKEN. The active input to the clock activation control stage 46d also causes step 46d to provide an inactive signal on its inverted output, ie the RESET START Z signal will now be activated. As long as the input signal on the line 46g provided to the closing control stage 46b is active, the subsequent clock pulses CLK2A will not affect the state of the output from the stage 46b. Therefore, it can be seen that the active signals RST and CLKEN and the signals RESET START Z inactive will continue to be produced until another RESET START signal clears the control stages, that is, until the POR 46a circuit is reactivated. The RST signal and the CLKEN signal may be necessary for the operation of the detonator delay circuit as will be described below. Since those signals are derived from the outputs of the stages connected in -donulation, it will be understood that they will not be produced unless the input to the closing control stage 46b, which is received from the closing circuit 46e this in its active state when the control stages 46b, 46c and 46d receive the clock pulses CLK2A after the RESET START signal decreases. However, the closed switching circuit 46e is configured in such a way that its ability to generate the active signal on the line 46g at power-up depends on the active state of the closing cell. As described in the above, the closing control stage 46b causes the closing switch circuit 46e to erase the "closing cell.

Therefore, even if a new RESET START signal is received and the control stages 46b, 46c and 46d are erased, the RST and CLKEN signals will not be generated, because the signal on the line 46g is inactive. In other words, the control circuit 56 closes the subsequent operation of the timer circuit 10 until the closure cell is reactivated as described herein. - The RST signal produced by the start control circuit 46 in the normal delay mode operation is transported to the timer circuit 32 and turns on the restoration circuit 54 (Figure 1). The active SESET START Z signal produced by the start control circuit 46 in the normal delay mode operation is transported to the ignition restoration circuit 54 only in response to the RESET START signal, for example to the ignition. The active RESET START Z signal maintains the ignition restoration circuit 54 in its restore state so that it can not enable the ignition output circuit 44 to provide an activation signal to the activation portion 18 through the output 42d . The ignition restoration circuit 54 is configured such that upon receipt of an inactive RESET START Z signal and the -RST "signal (which are generated after the RESET START signal and control stages 46b, 46c are decreased, and 46d receives a series of clock pulses from the signal CLK2A), generates a signal designated CND that is transported to the ignition output circuit 44 to initialize that circuit, then, upon receipt of a timer output signal from the counter 38, the ignition output circuit 44 (Figure 1) ', will emit the activation signal on the pin 42d.The inputs for the signals V18 and HV close to the closing switching circuit 46e, are used to bypass the function of the start control circuit 46 described above, that is, they allow the start control circuit 46 to initiate the oscillator 34 and thus allow the timer 32 without the functions of Subsequent closing timer, for programming purposes, as described below. A schematic circuit diagram of a particular implementation of a circuit. Start control according to the present invention is shown in Figure 2B. With reference to Figure 2B, it can be seen that during normal operation, when the setting voltage circuit 30 (Figure 1) generates the PROGP signal (approximately 12 volts) and the POR circuit 46a outputs the RESET START signal, the input of program of the EEPROM cell 149 in a closing switch circuit 46e is kept low and that output of the transistor 151 determines the state of the signal on the line 46g. Provided that the EEPROM cell 149 is previously erased to a high impedance mode when the delay portion 28 was programmed, the output of the transistor 151 will be high, providing an active closing signal on the line 46g for the control stage of close 46b. Subsequently, when the outputs of step 46b fluctuate, the gate of transistor 152 is placed at a lower level. The program input comprises the transistor 157, which was holding the program input of the lower EEPROM cell 149, is released later, and the EEPROM cell 149 goes to a conducting state. As described above, this condition provides a "permanent" inactive input to control step 46b to the generation of a RESET START signal due to a loss of transient energy. Future restores of synchronizer 32 are disabled due to the output of transistor 151 which will be low and the signal on line 46g will be inactive. Yes, due to a loss of transient energy resulting from, for example, an intermittent connection between the capacitor 14 and the activation portion 18 in which a subsequent RESET START signal is generated by the POR 46a circuit, the EEPROM cell 149 will not be erased and the control stages will remain closed. The source of the signal CLK2A on which the start control circuit 46 depends can be any conventional oscillator circuit. However, the present invention provides a novel oscillator illustrated schematically in Figure 3A. Broadly described, oscillator 34 operates providing an RC circuit for the discharge of a charged capacitor. The load carried by the capacitor is monitored by a comparator that generates a signal when the capacitor voltage falls below a reference voltage REF, ie when the capacitor is discharged. The signal is used by switching means that replace a capacitor charged by the discharged capacitor and connect the discharged capacitor to the power source that charges it to a voltage exceeding REF. Typically, the oscillator then comprises two capacitors, although in other embodiments more than two capacitors may be employed. With reference to the embodiment illustrated schematically in Figure 3A, the oscillator 34 comprises a first capacitor 34a and a second capacitor 34b. A switching circuit 34c serves to connect a capacitor to a resistor outside the microcircuit connected to the node 34d through which the capacitor is discharged. The resistor at node 34d is connected to the microcircuit at the input _SETR 42g (Figure 1). The switch circuit 34c also connects the other capacitor to a load source. In response to a signal received on line 34i, switch circuit 34c effectively reverses the position of the two capacitors. The capacitor charge, that is, the load on the capacitor that is discharged through the "node 34d or a related load, for example the load on the node 34d is compared to a reference voltage by the comparator" 34e. When the capacitor charge drops below the reference voltage, the comparator 34e generates a signal that is conveyed to a latching circuit 34f. Upon reception of the comparator signal, "the holding circuit 34f generates a signal which is taken as the output signal of the oscillator on the line 34g. The output of the holding circuit 34f can be provided as the switching signal to the switch circuit 34c together with switching signal line 34i Thus, according to capacitors 34a and 34b are alternately charged and discharged, latch 34f will produce a series of pulses comprising a clock signal. Figure 3A, the clock signal on the line 34g is designated CLK2A, and this is the clock signal that drives the jitter operation of the start control circuit 46. Figure 3A also illustrates a clock input 34h that receives a output signal from the holding circuit 34f although it requires the signal CLKEN from the start control circuit 46 in order to produce a signal CLK2 corresponding to the clock signal produced by the holding circuit 34f. The signal CLK2"is" used to increase the fluctuation counter. Together, the counter and the oscillator comprise a timer, the operation of which is controlled by the start control circuit 46 through the clock input 34h. Without an active CLKEN signal, the clock input 34h will not generate the signal CLK2 although the latching circuit 34f is generating the signals CLK2A for use at any time in the delay portion 28. Therefore the operation of the timer as a. total and in particular, the operation of the counter in response to clock pulses, depends on the presence of an active CLKEN signal. The frequency of the oscillator is the frequency with which each output Q, QZ returns to a certain state, for example, the frequency with which the output. Q changes to the top or active state. It will be understood by one of ordinary skill in the art that the resistance value of the resistor on the node 34d affects the time constant for the discharge of a capacitor connected to the same., and that the resistor can be selected to produce a desired oscillation frequency. The oscillator may have a frequency or period of, for example, approximately 50 microseconds. A schematic circuit diagram of a particular implementation of an oscillator for use in accordance with the present invention is shown in Figure 3B. Here it can be seen that the first capacitor 34a and the second capacitor 34b are embedded within one. collection of • transistors comprising switching circuit 34c. The switching circuit 34c effectively connects the discharged capacitor to a power source for recharging while connecting the charged capacitor to a resistor at the node 34d to be discharged. It can also be seen that the output of the latching circuit 34f comprises two outputs Q and QZ, and that the output Q controls the transistors 34j and 34k by means of line 34iQ while output QZ controls transistors 34m and 34n by means of line 34ÍQZ. Together, the lines 34ÍQ and 34ÍQZ comprise the switching signal line 34i of Figure 3A. The oscillator 34 (Figure 3B) comprises the The forced starter circuitry comprises the load control circuit 34p, the tilting circuit 34q, the starter circuit 34r and the bypass circuit 34s to initiate the operation of the oscillator at start-up even when a large capacitance is imposed on the resistor _ in the node 34d. To test test or programming purposes. In the start-up charge control circuit 34p, it turns on the transistors 34t and 34u, thereby initiating the charging process of the capacitors 34a, 34b and overcoming any parasitic capacitance on the node 34d. When the signal RESET START becomes active, the output of the start circuit 34r causes the Q signal of the rocker circuit 34q to decrease, so that the "on" signal provided to the transistors 34t and 34u remains on. The load continues until the capacitor voltage detected by the comparator 34e in INT exceeds 2/3 VDD. At that point, the comparator 34e switches to a higher state, causing the output Q of the swing circuit 34q, which is connected to the load control circuit 34p to increase. In response, the charge control circuit 34p turns off the transistors 34t and 34u. The voltage at the INP input to the comparator 34e then starts to descend, discharging the capacitor 34a through the resistor at the node 34d. When INP drops below 2/3 VDD, the comparator switches to a lower state, causing the latching circuit 34f to change to the normal oscillator function which proceeds afterwards as described above. Figure 3C indicates a preferred circuit configuration for the comparator 34e, which has a fast switching, low current draw, double stage and high gain circuit. The deviation input signal is equalized in current at M9, M8, M7 and M5. The transistors MI, M2, M3 and M4 comprise the first stage of the input differential amplifier and the transistors M13, M14, M15 and M16 comprise the second stage.

Figure 3D illustrates a preferred circuit configuration for the bypass circuit 34s of Figure 3B.

• Transistor b5 ensures that the quadruple transistor set bl, b2, b3 and b4 is turned on upon reception of the RESET START signal. The quad set provides a source of "stable voltage over typical circuit variations in CMOS manufacturing taking advantage of differences in threshold voltages between p-type and n-type transistors. circuit 34s set the deviation of the comparator circuit • 34e and limit the extraction of current through the starting circuit 34r. The clock signals of oscillator 3 * 4 (Figure 3A) can be supplied for any counter of conventional fluctuation that can be programmed to generate a timer output signal after counting a specified number of clock pulses. One aspect of the present invention relates to a novel programmable counter 36 (Figure 1) that can be used in a circuit detonator. The programmable counter 36 comprises a jitter counter 38 comprising a plurality of counter steps (such as type D latching circuits) placed in a fluctuating manner. Each counter stage 38a, 38b, etc. (Figure 4A) is able to have one of a "set" of adjustment and "erasing" state and comprises inputs by means of which the state of the counter stage can be initialized. Each counter stage comprises at least one output to provide a signal indicating the state of that counter stage. Typically, the output ~ is designated Q and each counter stage also provides a reverse output, for example QZ. The programmable counter 36 also comprises a program bank comprising a plurality of adjustment circuits 40a, 40a ', etc., and a plurality of deletion circuits 40b, 40b', etc., being an adjustment circuit and a circuit erase associated with each counter stage. The outputs of the adjustment circuits 40a, 40a ', etc., and the erasing circuits 40b, 40', etc., are connected to appropriate inputs of an associated counter stage and the adjustment circuits, the erasing circuits and the counter stages are configured so that an active signal from an adjustment circuit will place the counter stage in the setting state and an active signal from the clearing circuit will place the counter stage in the clearing state. The counter stages are configured such that when an erase signal and an adjustment signal are simultaneously received, the longer duration signal will determine the status of the counter stage. The jitter counter 38 has an inverting circuit that reverses the polarity of the PROG signal emitted by the PROG circuit 52 (FIG. 1) to generate the VEN signal. • The first counter stage 38a (Figure 4A) receives the clock pulses from an oscillator and can receive the clock signal with input CLK2 described in the foregoing with reference to Figure 2A. The adjustment circuits have inputs for the signals designated VPP, VEN (from the PROG circuit 52) and RST; the erase circuits are provided with inputs for the RST signal and a RESET signal from the restore generation circuit 48 (FIG. • 1) • Each adjustment circuit can assume any of two states in which it generates a long or letter duration adjustment signal respectively. The state of The adjustment circuit can be set by a signal provided at a suitable input P. In a preferred embodiment, an output signal from the associated counter stage provides the programming signal at the P input of the adjustment circuit to facilitate a programming method described in the following. To facilitate programming, the delay portion 28 (Figure 1) comprises a control input 42a, an energy input 42f (for a power signal designated VDD, typically around 5 volts), a restore generation circuit 48 and a program input 42b (sometimes designated V18), the latter being a multiple function input as will be explained later. The procedure for programming the counter illustrated schematically in Figure 4A is as follows. First, the ignition signals of approximately 5 volts are provided at the inputs 42b and 42f (Figure 1) from an external programming device. An active or higher logic CONTROL signal is "provided from the external device via the input 42a to restore the generation circuit 48. The restoration generation circuit 48 generates a RESET signal that is provided to the POR 46a circuit ( Figure 2A) of the start control circuit 46 (Figure 1) to overcome the internal POR function and restore the full delay portion 28. When the control signal is reduced, the POR 46a circuit (Figure 2A) generates a RESET START signal which restores the start control stages and activates the oscillator circuit 34. The oscillator 34 starts to cycle and drives the control stages of the start control circuit 46. When the circuit 46f generates the signal CLKEN, the clock pulses are released to the jitter counter 38, which starts to increase.The oscillator 34 and the counter 36 have the opportunity to cycle for the desired interval, at which point the signal in the input 42b is incremented over VDD by at least one volt, ie VDD ~ + 1.

Preferably the signal at input 42b is initially 0.5 volts-less than VDD (ie VDD-0.5) and is • increases to 2 volts higher than VDD (VDD + 2) after the desired interval that has elapsed. As indicated in Figure 1, the input 42b is connected to a V / H circuit 50 which damps and distinguishes between several signals from the input 42b and generates the appropriate output signals. When the signal at 42b is increased to exceed VDD by more than 1 volt at the end of the desired delay, the V / H circuit 46f produces an HV signal that is transported to the circuit 46f (Figure 2A) of the start control circuit 46. The circuit 46f responds by inactivating the signal CLKEN, thus stopping the timer by preventing the oscillator additionally increase the counter by means of the input 34h (Figure 3A). The V / H circuit 50 also produces a VPP programming signal whenever the signal at the input 42b exceeds 6 volts. (The effect of the VPP signal will be described later). Accordingly, a signal of at least 0.5 VDD input to the input 42b will result in the generation of a PROG signal. A signal at input 42b that exceeds VDD + 1 will result in the generation of an HV signal that stops the counter, and a signal at input 42b that exceeds 6 volts will result in the generation of a VPP signal. During programming, the The signal at the input 42a will reach approximately 14 volts and the closing switching circuit 46e (Figure 2a) is configured such that said signal restores the closing bit thereof. In view of the function of the V / H circuit 50 as described above, providing an initial signal at the input 42a of between 0.5 VDD and VDD + 1 concurrently with a control signal at the input 42a (both of which are connected to the restoration generation circuit 48) produces a RESET signal that clears the jitter counter 38 and maintains the POR circuit 46a (FIG. 2A) in the restoration state. When the CONTROL signal goes down, the internal POR function ends. The oscillator 34 (Figure 1) starts and the counter stages are increased. After the desired interval has passed, the signal at the input 42a is raised above VDD + 1, causing the V / H circuit 50 to produce the HV signal which stops the counter as described in FIG. previous. The signal at the input 42b is then increased to a level of at least 6 volts, which causes the V / H circuit 50 to generate the VPP signal, which allows the state of the adjustment circuit that has been determined by the state of the signal in the programming input of the adjustment stage. The high level signal V18 also restores the closing bit in the start control circuit 46 to allow the subsequent timer function. Thus, by initiating and terminating the CONTROL signal and adjusting the signal at input 42b appropriately, the start sequence and the clock operation occurring in normal operation, (i.e. The result of an input signal at the input 18a that results in a PROGP signal at 42c) can be synchronized with the measurement of a desired delay by an external programming device, to properly program the timer circuit with the desired delay. In the preferred embodiment illustrated, the adjustment circuits receive the output signals from the associated counter stages, so that the state of each counter stage at the time when the counter stops, ie at the end of the desired interval, it is reflected by the state of the associated adjustment circuit. Preferably, each adjustment circuit comprises a non-volatile circuit element such as the EEPROM cell which is programmed by the state of the input signal of the adjustment circuit. Accordingly, once the state of the adjustment circuit has been programmed, the energy can be withdrawn from the timer circuit and the counter configuration at the end of the desired delay will be maintained. In the operation, once the timer has been restored in response to a RESET signal, the initial states of the counter stages must be loaded from the associated adjustment circuits. This is achieved when 'the signal RST is generated by the start control circuit illustrated in Figures 2A and 2B. The RST signal allows the adjustment circuit and the erase circuit associated with each counter stage to convey a signal to the counter stage. The adjusting circuit and the clearing circuit are configured so that the signal pulse RST goes down, they generate their signals for the associated counter stage simultaneously although at different intervals. Generally, the adjustment circuits are configured so that when they are not programmed, the time constant for the adjustment circuit is about half the time constant of the erase circuit. Consequently, the erase signal will be of longer duration than and will remain on the setting signal of an unscheduled setting circuit and the stage of. counter will be deleted. On the other hand, the adjustment circuits are configured in such a way that, if the non-volatile program means, for example the EEPROM cell, are programmed, the time constant of the adjustment circuit extends beyond the time constant of the circuit. of deletion, so that after the RST signal ends, the adjustment signal will prevail over the deletion signal and the counter stage will be set or "charged", with the programming of the adjustment circuit. The additional detail for the particular modes of the adjustment circuits and deletion circuit for use in the counter according to the present invention are shown in Figure 4B, which shows a counter stage 38 'with its associated adjustment circuit 40a "and the associated erasure circuit 40b". In the setting circuit 40a ", Q2 indicates the non-volatile EEPROM cell.When the programming is completed, the signals received subsequently PROGP and VDD at the inputs 42c and 42f" respectively, will cause the POR 46a circuit to generate a signal RESET START for the different circuit components of the delay portion 28 and causes "the oscillator 34 to start operating." When the PROGP signal and the initial pulses from the oscillator 34 are received by the start control circuit 46, the circuit start control 46 produces the RST signal, the CLKEN signal and the RESET START Z signal that allow other circuits in the delay portion 28 to operate.At the same time, a closing portion of the start control circuit 46, i.e. , the start switch circuit 46e is set to prevent the subsequent operation of the start control sequence, therefore, in the case of a transient energy loss at the start. 42f after the timer operation has been initiated, restoring the energy of the 42f input will not result in recharging the timer or restarting the timer due to the non-volatile closing cell of the start control circuit 46, the which was adjusted before the power loss, will prevent the start control circuit 46 from enabling those functions. Specifically, the closing switch circuit 46e will continue to generate an inactive output signal despite the loss and reinstallation of the power for the delay portion 28, and the inactive signal received by the closure control stage 46b will prevent the generation of the active signals RST and CLKEN. Therefore, the delay circuit of the present invention ensures that the detonator will not turn on if a transient energy loss occurs during the "delay" interval In an alternative embodiment of a programmable electronic timer circuit in accordance with this invention, the The non-volatile program of the adjustment circuit may comprise a fuse link in place of an EEPROM cell A circuit diagram for such an adjustment circuit "is shown in Figure 4C. The adjustment circuit 140a "has the inputs for the same signals as the adjustment circuit 40a" of Figure 4B, ie, VEN, VPP, RST, data (Q), and generates the same output signal SDN (adjustment). The programming of the adjustment circuit 140a ", and the loading of an associated counter stage therefrom is achieved in the same general way as for the adjustment circuits comprising EEPROM cells, however," the programming procedure results in leaving the fuse link 142 intact or in causing it to be open. Specifically, when an active signal from the corresponding counter stage is received over the data input during the programming process, the fuse link 142 remains intact. Subsequently, when the program bank settings are loaded into the counter, the intact fuse link effectively short-circuits the output signal from the setting circuit 140a. "Consequently, the clear signal from the hard erase circuit more than the adjustment signal from the adjustment circuit, and the corresponding counter stage is erased, conversely, when an inactive or "zero" signal is received at the data input during programming, the link is opened. fuse When the associated counter stage is charged to the last, the setting circuit 140a "is capable of producing an adjustment signal (SDN) that lasts longer than the clear signal from the associated clearing circuit, and the counter stage it will adjust. Typically, more current is required to open a fuse link than to fit an EEPROM cell. Accordingly, the adjustment circuit 140a "has a configuration somewhat different than the adjustment circuit 40a" of Figure 4B. For example, the circuit elements 112 and 114 of the adjustment circuit 140a "are larger than the corresponding elements of the circuit '40a" such as Qi and Q., so that they can handle enough current to open the fuse link in voltages compatible with CMOS circuitry. An alternative programming method could be to cut (ie, open) the appropriate fuse links using a laser instead of operating the counter for a desired interval and using the output signals from the counter stages to control the opening currents of the meter. fuse. In this alternative approach, the accuracy of the oscillator frequency is given more certainty than in the previously described programming method. In the previously described method, the circuit is allowed to start for a measured period against a known clock, and when the desired interval is reached, the counter is stopped and the program bank is programmed in accordance with the output signals of the counter stages. Therefore, all timers will measure the interval counted by the external clock, even if the oscillator frequencies (and hence the program counts) vary from one microcircuit to another. However, the cutoff method is insensitive to variations in the oscillator frequency and can only establish a known delay if the oscillator frequency is known in advance. Therefore, the trimming method requires greater precision in the manufacture of the oscillator. While in the embodiment of Figure 1, the delay portion 28 is used in relation to an activation portion 18 for controlling the firing of a SCB for the initiation of a detonator, the driving signal produced by the delay portion 28. it can be used to control any device that must operate with a predetermined interval from the reception of the initiation signals provided to the delay portion 28. Similarly, the programmable timer circuit 32 can be used in devices other than detonators whenever needed an electronically programmable and non-volatile timer. Likewise, the oscillator 34 which is advantageously employed as part of a timer, can be used as part of any other device that requires a "clock" boost. An electronic delay circuit according to the present invention can be incorporated into a transducer circuit assembly generally shown in Figure 5 for convenient incorporation into a detonator. The transducer circuit assembly 155 comprises an electronic module 154 comprising the delay circuit 10 of Figure 1 with an initiation element 146 (eg, an SCB) attached thereto Figure 5 shows various components of the delay circuit 10, including the delay portion 28 with an associated resistor 134d (attached to the node 34d, Figure 3A), a drive portion 18, a storage capacitor 14, an optional leaf resistor 116 (to slowly discharge the capacitor 14 if the the detonator does not turn on after the capacitor 14 is charged, in a mode that does not include the closing feature described above) and the output conduits 137 that provide a solid terminal to which the storage capacitor is discharged. 14. The different components are mounted on lattice-like portions or traces 141 of a conductive structure and, except for, the output (or "output") conductors 137 are placed within an encapsulation 115. The transducer circuit assembly 155 comprises the initiation element 146 comprising the semiconductor bridge 16, which is connected through the external conductors 137), an initiation charge 146a which preferably comprises a fine particle explosive material such as BNCP perchlorate (tetramine-cis-bis (5-nitro-2H-tetrazolate-N2) cobalt (III), DXN-1, DDNP, lead azide or lead stifnate, in an initiation shell 146b which is folded over the neck region 144 of the encapsulation 115 and which maintains the initiation charge 146a in energy transfer relation with the "semiconductor bridge 16. The initiation charge 146a is preferably pressed into the initiation shell 146b to a density of less than 80% of its theoretical maximum density (TMD). For example, the initiation unit may be pressed into the shell 146b at a pressure of approximately 1,000 psi. Preferably, SCB 16 is secured to the output conduits 137 in a manner that allows SCB 16 to protrude, and be encircled by the initiation load 146a. Alternatively, such materials can be converted into a paste or bed mixture that can be applied to the SCB. The output initiation element 146 may comprise part of the output means of a detonator and may be used, for example, to initiate the base charge or "output" charge of the detonator wherein the transducer circuit assembly 155 is placed as described later. The package 115 preferably couples a sleeve 121 only along longitudinally extending protruding edges or fins (which are not visible in Figure 5) and thus establish a space 148 between the encapsulation 115 and the sleeve 121 in the circumferential regions around the encapsulation 115 between the fins. (Alternatively, the encapsulation 115 may comprise an absorption and impact material which may optionally make complete contact with the sleeve 121). The encapsulation 115 optionally defines cutouts 150 which make test conduits 152 accessible although preferably they allow the conductors to remain within the encapsulation surface profile 115, ie the conduits preferably do not extend into the space 148. If the cutouts 150 are omitted, it is preferred that the test conduits do not extend through the space 148 to make contact with the surrounding enclosure. Consequently, before the electronic module, which comprises the different circuit elements, the output initiation element 146 and the encapsulation 115, is placed inside the sleeve 121, the conduits such as the conductors 152 can be accessed to test the assembled circuitry. . Then, the electronic module 154 can be inserted into the sleeve 121 and the conductors 152 will not make contact with the sleeve 121. The electronic module 154 is designed so that the output conduits 137 and the input conductors 156, through the which storage capacitor 14 can be loaded, protrude from respective opposite ends of electronic module 154. A transducer module 158. comprises a piezoelectric transducer 12 and two transfer conductors 162 enclosed within transducer housing 164. Transducer housing 164 is dimensioned and configured to engage the sleeve 121 so that the transducer module 158 can be secured on the end of the sleeve 121 with the conductors 162 in contact with the input conductors 156. Preferably, the encapsulation 115, the sleeve 121 and the transducer encapsulation 164 are dimensioned and configured such that when assembled as shown in Figure 5, an air space indicated at 166 is established between the encapsulation 115"and the transducer package 164. In this way, the electronic module 154 is at least partially protected from the detonation impact wave that causes the piezoelectric transducer 12 to create the electrical impulse that initiates the electronic module 154. The pressure imposed by such a knock impact wave is transferred through the transducer module 158 on the sleeve 121 as indicated by the force arrows 168, instead of on the electronic module 154. The different circuit packages and elements can be mounted directly on the metal traces 141 of the conductive structure or, alternatively, on a polymeric or ceramic substrate in an arrangement of e type of board on circuit. Referring now to Figure 6A, a mode of a delay detonator 200 comprising an electronic module according to the present invention is shown. The delay detonator 200 comprises a housing 212 having an open end 212a and a closed end 212b. Housing 212 is made of an electrically conductive material, usually aluminum, and is preferably of the size and shape of conventional detonators, i.e. detonators. The detonator-200 comprises initiation signal transmission means for supplying an electrical initiation signal to the delay circuit. As indicated in the foregoing, the initiating signal transmission means may simply comprise fuse wires connected to the input terminal of the delay circuit. Preferably, however, the detonator is used as part of a non-electrical system and the initiating signal transmission means comprise the end of a non-electric signal transmission line (e.g. impact tube) and a transducer for converting the non-electrical initiation signal to an electrical signal, as described herein. In the illustrated embodiment, the delay detonator 200 is coupled to non-electrical initiation signal means comprising, in the illustrated case, an impact tube 210, a driving load 220 and a transducer module 158. It should be understood that the transmission lines of non-electrical signal in addition to the impact tube, such as the detonation cord, the low-energy detonation cord, the low-velocity impact tube and assimilators can be used. As is known to those skilled in the art, the impact tube comprises hollow plastic pipe, the inner wall of which is covered with an explosive material so that, upon ignition, a low energy impact wave is propagated to through the tube. See, for example, Thureson et al US Pat. No. 4,607,573, issued August 26, 1986. The impact tube 210 is secured in the housing 212 by an adapter bearing 214 that surrounds the tube 210. The housing 212 is "folded over." bearing 214 in folds 216, 216a to secure the impact tube 210 in the housing 212 and to form a protective seal of the environment between the housing 212 and the external surface of the impact tube 210. A segment 210a of the impact tube 210 is extends within the housing "212 and terminates at the end 210b in close proximity to, or in abutting contact with, an antistatic insulation bowl 218. The isolation bowl _ 218 has * a friction fit within the housing 212 and is made of a semiconductor material, for example, a polymeric material filled with carbon so as to form a conductive ground path from the impact tube 210 to the housing to 212 to dissipate any static electricity that may travel along "the impact tube 210. Such isolation bowls are well known in the art. See for example, US Patent 3,981,240 to "Gladden, issued September 21, 1976.

• A low energy booster 220 is placed adjacent to the antistatic insulation bowl 218. As best seen in Figure 6B, T the antistatic insulation bowl 218 comprises, as is well known in the art, a generally cylindrical body ( which is usually in the shape of a truncated cone, with the larger diameter end placed towards the open end 212a of housing 212) which is divided by a # thin fracturable membrane 218b within an entry chamber 218a and an exit chamber 218c. The end 210b of the impact tube 210 Figure 6A is received within the inlet chamber 218a (the impact tube 210 is not shown in FIG.

Figure 6B for illustration clarity). The s-alida chamber 218c provides an air space or separation in the entire end 210b of the impact tube 210 and the driving load 220 that are placed in mutual signal transfer relation to each other. In operation, the impact wave signal emitted from the end 210b of the impact tube 210 will fractionate the membrane 218b, traverse the space provided by the outlet chamber 218c and initiate the boost charge 220. The boost load 220 comprises a small charge. amount of primary explosive 224 such as lead azide (or Any suitable secondary explosive material such as BNCP), which is disposed between a driving shell 232 and on which it is placed, a first damping element 226 (not shown in Figure "6A for ease of illustration). "damping" element 226 which is of annular configuration except for a thin central membrane, which is located between the isolation bowl 218 and the explosive 224 and serves to protect the explosive 224 from the pressure imposed on it during manufacture. The insulating bowl 218, the first damping element 226, and the driving load 220 can be conveniently adjusted within a driving shell 232 as shown in Figure 6 B. The outer surface - of the insulating bowl 218 is in conductor contact with the inner surface of the driving shell 232 which in turn is in conductive contact with the housing .212 to provide an electric current path for any static electricity discharged from the impact tube 210. In general, the shell " drive 232 is inserted "into the housing 212 and the housing 212 is bent to retain the driving shell 232 therein as well as to protect the contents of the housing 212 from the environment.A nonconductive damper 228 (not shown in FIG. ease of illustration), which is typically 0.038 cm thick (0.015 inches), is located between the drive chamber 220 and the module the transducer 158 _ for electrically isolating the transducer module 158 from the driving load 220. The transducer module 158 comprises a piezoelectric transducer (not shown in Figure 6A) "which is placed in force communication relationship with the driving load 220 and for to be able to convert the output force of the driving load 220 towards an impulse of the electrical energy. The transducer module 158 is operatively connected to the electronic module 154 as shown in Figure 5. The initiating signal transmission means comprise the impact tube segment 210a the boost load 220 and the transducer module 158 serves to supply -al "delay circuit 10, in electric form, of a non-electric initiation signal received by means of the impact tube 210 as described below.The enclosure for the initiation and exit charges provided by the detonator 200 comprises, in addition of the housing 212, the optional open-ended steel sleeve 121 enclosing the electronic module 154. The electronic module 154 comprises at its output end an output initiation element 146 (shown, in Figure 5), which comprises part of the output means for the detonator. Adjacent to the initiation element of the electronic module 154 is a second damping element 242, which is similar to the first damping element 226. The second damping element 242 separates the output end of the electronic module 154 from the rest of the output means of detonator, comprising an output load 244 which is pressed into the closed end 212b of the housing 212. The output load 244 comprises a secondary explosive 244b which is sensitive to the initiation element of the electronic module 154 and which has sufficient impact energy to detonate the explosive range, dynamite, etc. The output load 244 may optionally comprise a relatively small charge of a primary explosive 244a to initiate the secondary explosive 244b, although the primary explosive 244a may be omitted if the initiation load of the electronic module 154 has sufficient output force to initiate the secondary explosive. 244b. The secondary explosive 244b has sufficient impact energy to fracture the housing 212 and detonate the range, dynamite, etc. explosives placed in proximity of signal transfer to the detonator 20"0. The output means for the detonator comprises those components, including reactive materials, for example explosives, which are initiated by the discharge of the storage means towards the output terminal. Thus, in the embodiment illustrated in FIGS. 5, 6A and 6B, the detonator output means comprises initiation element 146, initiation charge 146a and output charge.244. In use, a non-electrical initiation signal passing through impact tube 210 is emitted at end 210b. The signal fractures the membrane 218b of the isolation bowl 218 and the first damping element 226 to activate the driving load 220 by initiating the primary explosive 224. The primary explosive 224 generates a detonation impact wave which imposes a force of "alida on the piezoelectric generator in the transducer module 158. The piezoelectric generator is in force communication relationship with the driving load 220 and thus converts the output force to an" electrical output signal in the form of a pulse of electrical energy which is received by the electronic module 154. As indicated in the above, the electronic module 154 stores the electrical energy pulse and, after a predetermined delay, releases or transports the energy to the detonator's output means. illustrated, the load is released to the initiation element, which initiates the load "output 244. The output load 2 44 fractionate the housing 212 and emit an explosive output signal that can be used to initiate other explosive devices, as is well known in the art.

While it has been described in detail in the invention with reference to a particular embodiment thereof, it will be evident that upon reading and understanding the foregoing, numerous alterations to the described modality will be presented to those with experience in the art and it is intended to include such alterations within the scope of the appended claims.

Claims (10)

1. CLAIMS 1. An oscillator circuit for generating a clock signal comprising a series of clock pulses, the circuit is characterized in that it comprises: (a) reference voltage means for producing a reference voltage; (b) at least two capacitors, each capacitor having one of a charged state and one state discharged relative to the reference voltage, a capacitor- in the discharged state having a voltage less than the reference voltage and which is designated as a discharged capacitor, and a capacitor in the charged state that has a voltage that exceeds the reference voltage and that is designated as a charged capacitor; (c) charging means for charging a capacitor discharged to a charged state; (d) discharge means for charging a charged capacitor, designated as a charged working capacitor, to a discharged state; (e) a comparator to generate an internal signal each time a charged working capacitor becomes a discharged capacitor; (f) switching means for executing a switching function comprising effectively disconnecting a capacitor "discharged from the discharge means and connecting the capacitor discharged to the charging means, and for effectively disconnecting a charged capacitor from the charging means and connecting the charged capacitor to the discharge means; and "" (g) ~ uh a holding circuit for emitting a clock pulse in response to the internal signals 2. The oscillator circuit according to claim 1, characterized in that the switching means respond to the holding circuit to execute the switching function in response to the clock pulses emitted by the holding circuit 3. A programmable electronic timer circuit for outputting a timer output signal after the completion of a programmed delay that follows the reception of an electrical initiation signal, the porizador circuit. hoisted because it comprises: (a) an oscillator circuit for emitting, in response to the clock activating signal, a clock signal comprising a series of clock pulses; "(b) - a restoration generation circuit for generating a RESET signal of ignition; (c) an initializable jitter counter set to count the clock pulses and to produce the timer output signal when a predetermined count is reached , the fluctuation counter comprising a plurality of sequential counter stages each capable of having one of an adjustment state and an erase state, and comprising an adjustment input by which the state of the counted stage can be adjusted and an erase input by means of which the state of the counter stage can be erased, each counter stage further comprising at least one output for a counter stage signal indicating the status of the counter stage; d) a program bank comprising an adjustment circuit and an erase circuit associated with each counter stage, each adjustment circuit providing an adjustment signal to the to adjusting input of the associated counter stage in response to a counter load signal from a control circuit and each clearing circuit that provides a clear signal for the clearing input of the counter stage in response to a signal meter load and the ignition RESET signal, wherein the erase circuit produces a signal of defined duration and wherein - the adjustment circuit is configured, to provide a signal having either of two different determined durations, one of the which exceeds the duration of the clearing circuit signal, wherein the associated counter stage can receive the signals from the adjustment circuit and the clearing circuit simultaneously, and wherein the counter stage is configured so that the signal plus long determine the initial state of the counter stage; and (e) a control circuit that responds to an ignition RESET signal and an electrical initiation signal to output the counter charge signal and the clock activation signal. The timer circuit according to claim 3, characterized in that each adjustment circuit comprises non-volatile program means that can be. adjusted to cause the adjustment circuit to provide the longest duration signal that the erase circuit signal. The time circuit according to claim 4, characterized in that each adjustment circuit comprises a programming input and a data input, wherein the state of the non-volatile program means is determined by the state of the data signal when a programming signal is received at the program activating input. The timer circuit according to claim 4 or claim 5, characterized in that the non-volatile program means comprises an EEPROM cell. The timer circuit according to claim 5, characterized by the counter stage outputs are connected to the program input of the associated adjustment circuit whereby each counter stage can provide a data signal for the adjustment circuit associated. 8. An electronic closing timer circuit, powered by a power supply, for outputting a timer circuit output signal after the completion of a programmed delay following the reception of an electrical initiation signal, the timer circuit is characterized because it comprises: (a) an oscillator circuit that responds to a RESET signal, to emit at least one reference clock signal comprising a series of reference clock pulses; (b) a jitter counter configured to count the reference clock pulses and to produce the timer output signal when a predetermined count is reached; (c) a clock input through which the jitter counter receives the reference clock pulses when the clock input receives a CLKEN signal; and (d) a control circuit comprising a control bank comprising three control stages connected in a "fluctuating" fashion, the three control stages comprising a closing control stage, a counter load control stage and a step of clock activating control, each control stage being able to have one of an adjustment state and a deletion state _ and responding to a RESET signal - which initializes each control stage to erase state, and each control stage having an output that provides a signal _ indicating the status of the control stage; the control circuit further comprising an input control circuit for generating a CLKEN signal when the The clock activating control generates a setting signal, and further comprising a programmable non-volatile closing switching circuit capable of having one ~ "of an adjustment state and an erase state, the closing switching circuit which is driven to ia the adjustment state in response to the output signal from the closing control stage and assuming a clearing state in response to at least one programming signal, wherein the closing switching circuit has an output connected to "_ the logic input of the closing control stage, the closing control stage which is configured to supply a signal to the logic input of the closing control stage only when the closing circuit is in the state of erased when it receives the initiation signal, thus allowing the charge control stage of the counter and subsequently the clock activating stage, and which also provides a signal to the closing switch circuit to prevent the closing circuit-switch reirricie the control bank until res.taure the circuit closure switch. 9. A transducer circuit assembly characterized in that it comprises: a transducer module for converting an impact wave impulse to a pulse of electrical energy; an electronic module secured to the transducer module, the electronic module comprising: (a) a delay circuit comprising (i) means of. storage connected to the transducer module _ for receiving and storing electrical energy from the transducer module; (ii) a switching circuit that connects the storage means to an initiation element to release the energy stored in the storage means to the element of. initiation in response to a signal from a timer circuit; and (iii) a delay portion comprising the timer circuit of claim 3 or claim 8 operably connected to the switching circuit to control the release to the output terminal by the switching circuit "of energy stored in the media. of storage, and (b) an initiation element operatively connected to the storage means through the • switching circuit to receive the energy from the storage media and to generate a signal from 5 exit initiation in response to it. A detonator characterized in that it comprises: a housing having an open end and an open end, the open end that is dimensioned and configured for connection to the initiation signal transmission means; • means for transmitting initiation signal in the housing to supply an electrical initiation signal to the input terminal of the delay circuit; 15 a "power source to provide power to initiate the output initiation means; a delay circuit in the housing that • comprises (i) an input terminal for receiving the initiation signal, "(ii) a switching circuit that connects the storage means to an output terminal to release the energy stored in the storage means to the output means. of a detonator in response to a signal "from a timer circuit and (iii) the timer of claim 3 or claim 8 operatively connected to the switch circuit to control the release of the detonator output means via the circuit. switching the energy stored in the storage means; and detonator outlet means positioned in the housing in operative relation to the outlet terminal to generate an explosive exit signal upon discharge from the storage facilities. • • SUMMARY An electronic delay circuit (10) useful for the delayed initiation of detonators, illustrates several new presentations that can be combined, including a new oscillator (34), a programmable chronometer circuit (32) and a start control circuit ( 46). The oscillator. (34) generates a clock signal determined by the average discharge of a capacitor (34a) relative to a reference voltage -REF. A second capacitor (34b) is charged ~~ to a voltage that exceeds the REF, and when the first capacitor (34a) falls below the REF, an internal signal is generated and the capacitors are connected, thus the first capacitor is charged while the second capacitor is discharged. A holding circuit (34f) produces clock pulses in response to the "internal" signals The programmable timing circuit (32) includes a jitter counter (38) and a program bank (40) that charges an account in the counter from its start Each step of the counter (38) has separate inputs to adjust "and clear the signals, and the program bank (40) has a setting circuit and a clearing circuit for each stage of the counter. Each clearing circuit generates a set duration signal and each adjustment circuit can generate a signal of two different durations, one of which "" exceeds the clear signal. During programming, the adjustment signal of short or long duration is chosen, and when the counter is discharged, the longest of the adjustment signals or of the deletion signals, determines the state of the counter stage. The start control circuit (46) controls an input (34h) that allows the pulsations of the oscillator to increase the counter (38), but closes the input (34h) if a temporary loss of energy occurs thus preventing the timer ( 32) will restart.