EP0817337B1 - Herstellungsverfahren für einen Oberflächenemittierenden Laser - Google Patents

Herstellungsverfahren für einen Oberflächenemittierenden Laser Download PDF

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Publication number
EP0817337B1
EP0817337B1 EP97401489A EP97401489A EP0817337B1 EP 0817337 B1 EP0817337 B1 EP 0817337B1 EP 97401489 A EP97401489 A EP 97401489A EP 97401489 A EP97401489 A EP 97401489A EP 0817337 B1 EP0817337 B1 EP 0817337B1
Authority
EP
European Patent Office
Prior art keywords
layer
etching
undercutting
mesa
protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97401489A
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English (en)
French (fr)
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EP0817337A1 (de
Inventor
Antonina Plais
Paul Salet
Joel Jacquet
Francis Poingt
Estelle Derouin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oclaro North America Inc
Original Assignee
Alcatel CIT SA
Alcatel SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18341—Intra-cavity contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0207—Substrates having a special shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18316—Airgap confined
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18338—Non-circular shape of the structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054—Methods of obtaining the confinement
    • H01S5/2081—Methods of obtaining the confinement using special etching techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054—Methods of obtaining the confinement
    • H01S5/2081—Methods of obtaining the confinement using special etching techniques
    • H01S5/209—Methods of obtaining the confinement using special etching techniques special etch stop layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3202—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures grown on specifically orientated substrates, or using orientation dependent growth

Definitions

  • the invention relates to semiconductor lasers called “surface emission lasers” or “VCSEL” (from English: “Vertical Cavity Surface Emitting Laser”).
  • These lasers are produced from a substrate composed of a III-V type semiconductor alloy such as gallium arsenide GaAs or indium phosphide InP.
  • the component essentially consists of a cavity resonant delimited by two dielectric or semiconductor mirrors opposed.
  • the resonant cavity is formed of a p-doped InP layer, with a quaternary active layer Undoped GaInAsP and an n-doped InP layer.
  • injection current is effected by means of two electrodes arranged on either side of the resonant cavity.
  • the mirror is made of a dielectric material, at at least one of the electrodes is necessarily placed next to or more generally around this mirror.
  • the good performance of such a structure is conditioned by sufficient confinement of the layer active, both optically and electrically.
  • the active layer is buried in a medium with a lower index of refraction. If the active layer is further buried in a p-doped medium at the border of medium n, we will obtain also an electrical confinement due to the threshold voltage of the p-n junction which surrounds the active layer.
  • the proposed structure includes a active non-buried layer above which is placed a current confinement layer.
  • This layer is made from a continuous layer of arsenide aluminum which is subjected to lateral oxidation controlled to leave a current opening located below the upper mirror.
  • This solution ensures good flatness of the surface receiving the mirror but requires delicate control of the lateral oxidation step. It is otherwise necessary to deposit a layer of silicon nitride protection to stop oxidation of the aluminum arsenide layer.
  • This confinement layer will therefore have the form a diaphragm having the effect of concentrating the lines of current flowing through the active layer over a defined area located directly above the upper mirror.
  • the proposed process first has the advantage of avoiding any problem of flatness of the semiconductor layers located between the diaphragm and mirror. Furthermore, the fact that the layer of electrical confinement is achieved by lateral etching provides perfect electrical insulation all around the diaphragm.
  • the invention aims to facilitate this engraving lateral.
  • the method according to the invention provides further that the side walls of the mesa are formed of four vertical planes oriented at about 45 degrees from the substrate cleavage planes.
  • the deposition of the protective layer is preceded by a slight lateral engraving of the contact layer. This provision improves the fixation of the protective layer on the vertical walls of the mesa.
  • a layer 2 likewise composition as the substrate, an active layer CA made up of an undoped InGaAsP quaternary alloy, the composition defines the characteristic wavelength of the active layer, a layer 3 of p-doped indium phosphide, a layer of under-etching a, a layer 4 of phosphide p-doped indium, a contact layer c composed of InGaAs ternary or strongly InGaAsP quaternary alloy p doped and finally a metallic layer k composed for example of an alloy of gold and platinum.
  • the set of layers 3, a, 4, c constitutes a current injection layer IC intended to conduct the electric current from the surrounding upper electrode a corresponding mirror.
  • the sub-etching layer a is composed of a InGaAsP quaternary alloy whose composition ensures characteristic wavelength less than that of the active layer CA. We will also choose a composition that gives this layer different etching properties from that of neighboring layers 3 and 4.
  • an etching of the metal layer k is then carried out to form an opening 6 defining the location and the shape of the upper mirror.
  • the entire component is then covered with a protective layer 5.
  • the layer 5 is for example made of silica SiO 2 or silicon nitride Si 3 N 4 .
  • Ionic machining of the layer of metal k increases the height of the mesa so that reach the contact layer c. The result appears in Figure 4.
  • the wafer with a new protective layer 8 produced by an isotropic deposition of a protective material such as silica This deposition can be carried out by the P E C V D process. (chemical vapor deposition assisted by plasma).
  • Non-selective RIE etching of the wafer using the silica covering the mesa m as a mask then makes it possible to free the lateral ends of the under-etching layer a directly above the vertical walls 9.
  • the anchoring zone 7 has the effect to reinforce the adhesion of the silica layer 8 covering the wall 9.
  • a controlled selective etching of the under-etching layer a is carried out so as to form the current confinement layer consisting of a diaphragm a2 and its periphery etched a1, as shown in figure 8. This controlled etching can be carried out wet with a 3H 2 SO 4 / H 2 O 2 / H 2 O solution.
  • the final shape of the component appears in section on Figure 10. It is obtained after deposition of a layer passivation 10 consisting for example of nitride silicon playing the role of electrical insulator. We deposit then the upper mirror MS and we cover the whole of a conductive coating 11 consisting for example of a thin layer of gold (0.2 ⁇ m) on which is deposited a weld diffusion barrier composed for example of a mixture of titanium, tungsten and gold. To finish the manufacturing, an engraving of the part is then carried out bottom of the substrate to the etch stop layer b, we form the lower MI mirror and place the electrode lower than k '.
  • a layer passivation 10 consisting for example of nitride silicon playing the role of electrical insulator.
  • a conductive coating 11 consisting for example of a thin layer of gold (0.2 ⁇ m) on which is deposited a weld diffusion barrier composed for example of a mixture of titanium, tungsten and gold.
  • an engraving of the part is then carried out bottom of the substrate to the
  • Figure 11 shows a top view of the containment layer in relationship with the crystallographic planes of the substrate.
  • the face horizontal of the substrate is oriented along the plane crystallographic (001). So by orienting the walls vertical of the mesa in the directions (100) and (010), we define planes oriented at 45 degrees planes of substrate cleavage and these planes have properties identical engraving.
  • the containment layer shown is consisting of a square diaphragm a2 surrounded by the part under-engraved a1 also delimited by a square.
  • the resin mask defining the mesa (figure 3) is also square. it implies that the vertical walls of the mesa are identical.
  • the invention is not limited to only embodiment which has just been described.
  • the deposition of the metallic layer k can be performed towards the end of the process using a technique called "lift" to discover the area of the mirror next to the diaphragm.

Claims (7)

  1. Verfahren zur Herstellung einer Halbleiterlaser-Komponente mit Oberflächenemission, die einen vertikalen Resonanzraum aufweist, der in einem aus Elementen der Gruppe III-V gebildeten Substrat ausgebildet ist, wobei der Raum eine Schicht (IC) für die Einleitung von elektrischem Strom umfasst, die mit einer horizontalen Schicht (a1, a2) für den elektrischen Einschluss, die zwischen einer horizontalen aktiven Schicht (CA) und einem den Raum begrenzenden Spiegel (MS) angeordnet ist, versehen ist, wobei die Bildung der Stromeinleitungsschicht (IC) die folgenden Schritte umfasst:
    Aufwachsenlassen einer Unterätzschicht (a), die bei der Betriebswellenlänge der Komponente durchlässig ist, auf der aktiven Schicht (CA),
    wenigstens ein Aufwachsenlassen einer dotieriten Schicht, die aus Elementen der Gruppe III-V besteht, auf der Unterätzungsschicht (a),
    Bilden eines Mesa (m), das in Bezug auf den für den Spiegel (MS) vorgesehenen Ort zentriert ist und dessen Seitenwände (9) die Unterätzschicht (a) frei lassen, und
    gesteuertes seitliches Ätzen der Unterätzschicht (a), um die Schicht (a1, a2) für den elektrischen Einschluss zu bilden,
       wobei das Verfahren dadurch gekennzeichnet ist, dass die Seitenwände (9) des Mesa (m) aus vier vertikalen Ebenen gebildet sind, die unter etwa 45 Grad zu den Spaltungsebenen des Substrats orientiert sind.
  2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Seitenwände gleiche Abmessungen haben.
  3. Verfahren nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, dass die Bildung des Mesa (m) dann, wenn die Stromeinleitungsschicht (IC) eine Kontaktschicht (c), die Ätzeigenschaften besitzt, die zu jenen der Unterätzschicht (a) ähnlich sind, aufweist und über jener angeordnet ist, umfasst:
    einen ersten Ätzschritt, der die Unterätzschicht (a) nicht angreift, jedoch die Kontaktschicht (c) freilegt,
    eine Ablagerung einer Schutzschicht (8), die andere Ätzeigenschaften als die Unterätzschicht (a) besitzt, auf der Kontaktschicht (c) und
    wenigstens einen zweiten Ätzschritt, der die Unterätzschicht (a) freilegt.
  4. Verfahren nach Anspruch 3, dadurch gekennzeichnet, dass der Ablagerung der Schutzschicht (8) eine geringfügige seitliche Ätzung (7) der Kontaktschicht (c) vorhergeht.
  5. Verfahren nach einem der Ansprüche 3 oder 4, dadurch gekennzeichnet, dass die Ablagerung der Schutzschicht (8) aus einer isotropen Ablagerung einer Schicht aus Schutzwerkstoffen auf der gesamten Oberfläche der Komponente, gefolgt von einer anisotropen Ätzung zur Beseitigung der Schicht aus Schutzwerkstoffen von den horizontalen Flächen der Komponente, besteht.
  6. Verfahren nach einem der Ansprüche 3 bis 5, dadurch gekennzeichnet, dass die Schutzschicht (8) aus Siliciumdioxid gebildet ist.
  7. Verfahren nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass die Unterätzschicht (a) dann, wenn das Substrat aus Indiumphosphid gebildet ist, aus einer Quartärverbindung aus Phosphor, Indium, Gallium und Arsen gebildet ist.
EP97401489A 1996-07-04 1997-06-26 Herstellungsverfahren für einen Oberflächenemittierenden Laser Expired - Lifetime EP0817337B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9608338A FR2750804B1 (fr) 1996-07-04 1996-07-04 Procede de fabrication d'un laser a emission par la surface
FR9608338 1996-07-04

Publications (2)

Publication Number Publication Date
EP0817337A1 EP0817337A1 (de) 1998-01-07
EP0817337B1 true EP0817337B1 (de) 2003-08-06

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EP97401489A Expired - Lifetime EP0817337B1 (de) 1996-07-04 1997-06-26 Herstellungsverfahren für einen Oberflächenemittierenden Laser

Country Status (5)

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US (1) US5854088A (de)
EP (1) EP0817337B1 (de)
JP (1) JP3225211B2 (de)
DE (1) DE69723923T2 (de)
FR (1) FR2750804B1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4024994B2 (ja) * 2000-06-30 2007-12-19 株式会社東芝 半導体発光素子
DE10111501B4 (de) * 2001-03-09 2019-03-21 Osram Opto Semiconductors Gmbh Strahlungsemittierendes Halbleiterbauelement und Verfahren zu dessen Herstellung
JP2003086839A (ja) * 2001-09-07 2003-03-20 Sharp Corp 窒化物半導体発光素子およびその製造方法
US7860137B2 (en) * 2004-10-01 2010-12-28 Finisar Corporation Vertical cavity surface emitting laser with undoped top mirror
US20090032799A1 (en) 2007-06-12 2009-02-05 Siphoton, Inc Light emitting device
US7972190B2 (en) * 2007-12-18 2011-07-05 Seiko Epson Corporation Organic electroluminescent device, method for producing organic electroluminescent device, and electronic apparatus
US20110108800A1 (en) * 2008-06-24 2011-05-12 Pan Shaoher X Silicon based solid state lighting
US20110114917A1 (en) * 2008-07-21 2011-05-19 Pan Shaoher X Light emitting device
US20100308300A1 (en) * 2009-06-08 2010-12-09 Siphoton, Inc. Integrated circuit light emission device, module and fabrication process
US8283676B2 (en) * 2010-01-21 2012-10-09 Siphoton Inc. Manufacturing process for solid state lighting device on a conductive substrate
US8722441B2 (en) 2010-01-21 2014-05-13 Siphoton Inc. Manufacturing process for solid state lighting device on a conductive substrate
US8674383B2 (en) * 2010-01-21 2014-03-18 Siphoton Inc. Solid state lighting device on a conductive substrate
US8624292B2 (en) 2011-02-14 2014-01-07 Siphoton Inc. Non-polar semiconductor light emission devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343487A (en) * 1992-10-01 1994-08-30 Optical Concepts, Inc. Electrical pumping scheme for vertical-cavity surface-emitting lasers
US5416044A (en) * 1993-03-12 1995-05-16 Matsushita Electric Industrial Co., Ltd. Method for producing a surface-emitting laser
JPH0758408A (ja) * 1993-08-17 1995-03-03 Furukawa Electric Co Ltd:The 面発光半導体レーザ素子の製造方法

Also Published As

Publication number Publication date
JP3225211B2 (ja) 2001-11-05
FR2750804A1 (fr) 1998-01-09
FR2750804B1 (fr) 1998-09-11
DE69723923T2 (de) 2004-07-29
EP0817337A1 (de) 1998-01-07
DE69723923D1 (de) 2003-09-11
JPH1065268A (ja) 1998-03-06
US5854088A (en) 1998-12-29

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