EP0810505B1 - Agencement de circuit pour la génération d'une résistance à coefficient de température positif et réglable ainsi que son utilisation - Google Patents
Agencement de circuit pour la génération d'une résistance à coefficient de température positif et réglable ainsi que son utilisation Download PDFInfo
- Publication number
- EP0810505B1 EP0810505B1 EP97108343A EP97108343A EP0810505B1 EP 0810505 B1 EP0810505 B1 EP 0810505B1 EP 97108343 A EP97108343 A EP 97108343A EP 97108343 A EP97108343 A EP 97108343A EP 0810505 B1 EP0810505 B1 EP 0810505B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit
- circuit arrangement
- temperature coefficient
- resistance
- resistance element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S323/00—Electricity: power supply or regulation systems
- Y10S323/907—Temperature compensation of semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Semiconductor Integrated Circuits (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Led Devices (AREA)
Claims (2)
- Montage de production d'un comportement résistant à coefficient de température positif réglable, comprenant un circuit série constitué d'un premier élément (1) résistant ohmique et d'un élément (3) formant d'iode,
caractérisé en ce qu'un second élément (2) résistant ohmique est monté en parallèle au circuit série, la valeur du second élément (2) résistant ohmique pouvant être réglée en fonction du coefficient de température souhaité. - Utilisation du montage suivant la revendication 1, dans un circuit à miroir de courant dans lequel un courant (1) d'entrée alimente le montage caractérisée en ce que la chute de tension (U) entre ses bornes est envoyée à la section base émetteur d'un transistor (5), le courant (Q) de sortie au collecteur du transistor (5) peut être prélevé et un élément (4) résistant formant émetteur a, à la borne d'émetteur du transistor (5), la même valeur que le premier élément (1) résistant ohmique du montage.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19621749A DE19621749C2 (de) | 1996-05-30 | 1996-05-30 | Schaltungsanordnung zum Erzeugen eines Widerstandsverhaltens mit einstellbarem positiven Temperaturkoeffizienten sowie Verwendung dieser Schaltungsanordnung |
DE19621749 | 1996-05-30 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0810505A2 EP0810505A2 (fr) | 1997-12-03 |
EP0810505A3 EP0810505A3 (fr) | 1998-04-22 |
EP0810505B1 true EP0810505B1 (fr) | 1999-07-28 |
Family
ID=7795705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97108343A Expired - Lifetime EP0810505B1 (fr) | 1996-05-30 | 1997-05-22 | Agencement de circuit pour la génération d'une résistance à coefficient de température positif et réglable ainsi que son utilisation |
Country Status (3)
Country | Link |
---|---|
US (1) | US6121763A (fr) |
EP (1) | EP0810505B1 (fr) |
DE (2) | DE19621749C2 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004062357A1 (de) | 2004-12-14 | 2006-07-06 | Atmel Germany Gmbh | Versorgungsschaltung zur Erzeugung eines Referenzstroms mit vorgebbarer Temperaturabhängigkeit |
US20120326185A1 (en) * | 2006-12-22 | 2012-12-27 | Epistar Corporation | Light emitting device |
DE102009003632B4 (de) | 2009-03-17 | 2013-05-16 | Lear Corporation Gmbh | Verfahren und Schaltungsanordnung zur Ansteuerung einer Last |
DE102017107412A1 (de) * | 2017-04-06 | 2018-10-11 | Lisa Dräxlmaier GmbH | Schaltungsanordnung, beleuchtungsanordnung und verfahren |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3956661A (en) * | 1973-11-20 | 1976-05-11 | Tokyo Sanyo Electric Co., Ltd. | D.C. power source with temperature compensation |
NL7907161A (nl) * | 1978-09-27 | 1980-03-31 | Analog Devices Inc | Geintegreerde temperatuurgecompenseerde spannings- referentie. |
US4243948A (en) * | 1979-05-08 | 1981-01-06 | Rca Corporation | Substantially temperature-independent trimming of current flows |
US4313082A (en) * | 1980-06-30 | 1982-01-26 | Motorola, Inc. | Positive temperature coefficient current source and applications |
DE3137504A1 (de) * | 1981-09-21 | 1983-04-07 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordnung zur erzeugung einer temperaturunabhaengigen referenzspannung |
JPS5922433A (ja) * | 1982-07-29 | 1984-02-04 | Toshiba Corp | 温度補償用回路 |
US4736126A (en) * | 1986-12-24 | 1988-04-05 | Motorola Inc. | Trimmable current source |
US4882533A (en) * | 1987-08-28 | 1989-11-21 | Unitrode Corporation | Linear integrated circuit voltage drop generator having a base-10-emitter voltage independent current source therein |
US4956567A (en) * | 1989-02-13 | 1990-09-11 | Texas Instruments Incorporated | Temperature compensated bias circuit |
US5198701A (en) * | 1990-12-24 | 1993-03-30 | Davies Robert B | Current source with adjustable temperature variation |
JP3266177B2 (ja) * | 1996-09-04 | 2002-03-18 | 住友電気工業株式会社 | 電流ミラー回路とそれを用いた基準電圧発生回路及び発光素子駆動回路 |
-
1996
- 1996-05-30 DE DE19621749A patent/DE19621749C2/de not_active Expired - Fee Related
-
1997
- 1997-05-22 EP EP97108343A patent/EP0810505B1/fr not_active Expired - Lifetime
- 1997-05-22 DE DE59700279T patent/DE59700279D1/de not_active Expired - Lifetime
- 1997-05-30 US US08/866,415 patent/US6121763A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0810505A2 (fr) | 1997-12-03 |
DE59700279D1 (de) | 1999-09-02 |
EP0810505A3 (fr) | 1998-04-22 |
DE19621749C2 (de) | 1998-07-16 |
US6121763A (en) | 2000-09-19 |
DE19621749A1 (de) | 1997-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102006003123B4 (de) | Bezugsspannungsschaltkreise | |
DE4237122C2 (de) | Schaltungsanordnung zur Überwachung des Drainstromes eines Metall-Oxid-Halbleiter-Feldeffekttransistors | |
DE102008059853A1 (de) | Schaltungsanordnung mit einem Lasttransistor und einem Messtransistor | |
DE3238880A1 (de) | Schaltungsanordnung | |
DE102014107017A1 (de) | Schaltungsanordnung | |
DE102010006865B4 (de) | Stromquelle, Stromquellenanordnung und deren Verwendung | |
DE10143032C2 (de) | Elektronische Schaltung zum Erzeugen einer Ausgangsspannung mit einer definierten Temperaturabhängigkeit | |
EP1278402B1 (fr) | Circuit pour LED avec commande de courrant dépendent de la temperature | |
DE102005011653B4 (de) | Schaltungsanordnung mit einem Transistor mit verringertem Rückstrom | |
EP0810505B1 (fr) | Agencement de circuit pour la génération d'une résistance à coefficient de température positif et réglable ainsi que son utilisation | |
EP0255067A1 (fr) | Circuit limiteur de courant | |
DE2853581C2 (de) | Emitterfolgerschaltung | |
DE2416533C3 (de) | Elektronische Schaltungsanordnung zur Spannungsstabilisierung | |
DE10049994A1 (de) | Schaltungsanordnung zum Überwachen und/oder zum Einstellen von Versorgungsspannungen | |
DE2404850C3 (de) | Elektronische Sicherung für einen Gegentakt-Verstarker | |
DE69822389T2 (de) | Verstärkerschaltung | |
DE1805855A1 (de) | Gegentaktverstaerker | |
DE3246144C2 (de) | Schaltungsanordnung zur Stromkonstanthaltung | |
EP0575587B1 (fr) | Circuit pour la detection de sous-tensions | |
DE102016007752A1 (de) | Schutzschaltung, Beleuchtungsanordnung und Betriebsverfahren | |
DE2849153A1 (de) | Schaltungsanordnung zur erzeugung einer konstanten hilfsgleichspannung | |
EP0766163B1 (fr) | Circuit pour générer une tension de polarisation | |
DE4112310C2 (fr) | ||
DE10024515B4 (de) | Spannungsregler mit einem Leistungstransistor | |
DE2457549A1 (de) | Schaltung zum abschneiden eines signales |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB IT |
|
RHK1 | Main classification (correction) |
Ipc: G05F 3/26 |
|
17P | Request for examination filed |
Effective date: 19980519 |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
17Q | First examination report despatched |
Effective date: 19981217 |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IT |
|
REF | Corresponds to: |
Ref document number: 59700279 Country of ref document: DE Date of ref document: 19990902 |
|
ET | Fr: translation filed | ||
ITF | It: translation for a ep patent filed |
Owner name: STUDIO JAUMANN P. & C. S.N.C. |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 19990929 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
REG | Reference to a national code |
Ref country code: GB Ref legal event code: IF02 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20030512 Year of fee payment: 7 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20040427 Year of fee payment: 8 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050131 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED. Effective date: 20050522 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050522 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20050522 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 59700279 Country of ref document: DE Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: SIEMENS AKTIENGESELLSCHAFT, 80333 MUENCHEN, DE Effective date: 20111107 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20160714 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 59700279 Country of ref document: DE |