EP0806084A1 - Circuit for switching the actuator outputs off in an asi system in the event of data communication failure - Google Patents

Circuit for switching the actuator outputs off in an asi system in the event of data communication failure

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Publication number
EP0806084A1
EP0806084A1 EP96900266A EP96900266A EP0806084A1 EP 0806084 A1 EP0806084 A1 EP 0806084A1 EP 96900266 A EP96900266 A EP 96900266A EP 96900266 A EP96900266 A EP 96900266A EP 0806084 A1 EP0806084 A1 EP 0806084A1
Authority
EP
European Patent Office
Prior art keywords
connection
voltage
circuit
positive
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96900266A
Other languages
German (de)
French (fr)
Inventor
Manfred Schmitt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0806084A1 publication Critical patent/EP0806084A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C25/00—Arrangements for preventing or correcting errors; Monitoring arrangements
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/4185—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by the network communication
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/31—From computer integrated manufacturing till monitoring
    • G05B2219/31154—Actuator sensor bus, asi, intelligent actuator, motor, sensor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/33—Director till display
    • G05B2219/33242—Watchdog for datacommunication, on error switch off supply to bus modules
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • Circuit arrangement for switching off the actuator outputs in the ASI system in the event of data communication failure
  • the invention relates to a circuit arrangement for the defined switching off of output switching stages, which are supplied with DC voltage via a circuit of a slave communicating with a master in an ASI system, the circuit having a positive, a negative DC voltage connection and a connection which trigger pulses only occur during data communication between the master and the slave.
  • the actuator sensor interface (ASI) (the actuator sensor interface for automation, Werner Kriesel, Otto W. Madelung, Carl Hanser Verlag, Kunststoff - Vienna, 1994) is for data exchange between a large number of participants intended. It is a so-called “single master system” in which one master controls the data exchange for each line strand. He calls the slaves lying in the wiring harness one after the other and awaits their response. Each slave is assigned its own address as an identifier, via which it can be called. Since each slave can transmit 4 Bi data and a maximum of 31 slaves (31 addresses) can be connected per line string, there can be a maximum of 124 binary participants on an ASI line with static operation of the four data lines. In the bidirectional operation of the four data lines, the number of participants can be expanded to 124 actuators (outputs) plus 124 sensors (inputs).
  • the invention is therefore based on the object of providing a circuit arrangement for the defined shutdown of the actuator outputs in the actuator / sensor interface system in the event of data communication failure.
  • the circuit arrangement has a timer which can be controlled by the trigger pulses and which opens a downstream electrical switch after the trigger pulses have failed, so that the output switching stages are cut off from the supply with the DC voltage.
  • timing element has a combination of a capacitor and a first ohmic resistor, which is fully charged with each trigger pulse and, after the trigger pulses have failed, with the resultant from the capacitor and the first ohmic resistor Time constants are discharged so that after the minimum control voltage of the subsequent electrical switch is undershot, the latter opens.
  • the circuit arrangement is advantageously carried out in detail in such a way that a second ohmic resistance lies between the connection and the positive DC voltage connection, that a parallel connection of the capacitor and the first ohmic resistance is provided, which on the one hand with the positive DC voltage connection and on the other hand via a Diode is electrically connected to the emitter of a first transistor, the base of which is connected to the terminal and the collector of which is connected to the negative direct voltage terminal, that the connection point between the diode, on the one hand, and the first resistor and capacitor, on the other hand, is led to the base of a second transistor, the Collector is connected to the negative DC voltage connection and whose emitter is connected via a third ohmic resistor to the base of the switch designed as a third transistor, whose emitter is connected to the positive direct voltage connection and to whose collector the output switching stages, for example relays, are connected, a fourth ohmic resistor being connected between the The basis of the third transistor and the positive direct voltage connection lies.
  • FIG. 1 shows the circuit arrangement according to the invention for the defined switching off of output switching stages.
  • each slave of the "ASI system" described at the beginning there is a special circuit 1 which, according to FIG. 1, is provided with a connection 2, the so-called data strobe connection, and DC voltage connections 6, 7.
  • the circuit arrangement according to the invention for the defined switching off of actuator outputs 5 in the ASI system is located at these connections 2, 6, 7 if the data communication between the master and the respective slave fails.
  • the circuit arrangement essentially consists of a retriggerable timer 3 and an electronic switch 4 which can be controlled by it.
  • the circuit is constructed as follows:
  • the retriggerable timing element 3 consists of two transistors 9, 10 and a parallel connection of a capacitor 11 and a nem ohmic resistor 12, the parallel connection being connected on the one hand to the positive DC voltage connection 6 and on the other hand via a diode 13 to the emitter of the transistor 9, the base of which is connected to the connection 2 and the collector of which is connected to the negative DC voltage connection 7.
  • the connection point 14 between the diode 13 on the one hand and the resistor 12 and the capacitor 11 on the other hand is led to the base of the transistor 10, the collector of which is also connected to the negative DC voltage connection 7.
  • Its emitter is connected via an ohmic resistor 15 to the base of the further transistor 4, which is connected downstream of the timing element and whose emitter is connected to the positive DC voltage connection 6.
  • a resistor 16 is provided between the base of transistor 4 and the positive direct voltage connection.
  • the function of the circuit is explained with reference to FIG 2, where four curves are shown.
  • the top curve shows different phases of the ON and OFF switching of data communication between the master and the slave.
  • the ASI circuit 1 in the slave emits a trigger pulse U 1 according to the second curve in FIG. 2 to its address on the data strobe connection 2 with each master call.
  • the retriggerable timer is triggered with this signal U1. If the master calls and thus the trigger pulses fail, the downstream transistor 4 is opened after the time tz specified by the timing element has elapsed, and the connected output switching stages 5 switch off.
  • This is illustrated by the third curve U2 with the potential of the connection point 14 in relation to the negative DC voltage connection 7, which corresponds to the differential voltage between the DC voltage and the voltage at the capacitor 11 and the fourth curve with the supply voltage U3 of the output switching stages 5.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Quality & Reliability (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)
  • Small-Scale Networks (AREA)

Abstract

The circuit of the invention makes it possible to switch in a defined manner the output switching stages (5) off in an actuator-sensor-interface system on the failure of data communication. This is attained by a timer (3) controlled by trigger pulses available at the data strobe connector (2) of the circuit (1) during data communication. If there are no trigger pulses, a downstream electric switch (4) opens so that the output switching stages (5) are cut off from the d.c. power supply.

Description

Beschreibungdescription
Schaltungsanordnung zum Abschalten der A tuatorausgänge im ASI-System bei Ausfall der DatenkommunikationCircuit arrangement for switching off the actuator outputs in the ASI system in the event of data communication failure
Die Erfindung bezieht sich auf eine Schaltungsanordnung zum definierten Abschalten von Ausgangsschaltstufen, die über einen Schaltkreis eines mit einem Master kommunizierenden Slaves in einem ASI-System mit Gleichspannung versorgt wer- den, wobei der Schaltkreis einen positiven, einen negativen Gleichspannungsanschluß und einen Anschluß aufweist, an dem nur während der Datenkommunikation zwischen dem Master und dem Slave Triggerimpulse anstehen.The invention relates to a circuit arrangement for the defined switching off of output switching stages, which are supplied with DC voltage via a circuit of a slave communicating with a master in an ASI system, the circuit having a positive, a negative DC voltage connection and a connection which trigger pulses only occur during data communication between the master and the slave.
Das Aktuator-Sensor-Interface (ASI) (das Aktuator-Sensor-In- terface für die Automation, Werner Kriesel, Otto W. Madelung, Carl Hanser Verlag, München - Wien, 1994) ist zum Datenaus¬ tausch zwischen einer Vielzahl von Teilnehmern vorgesehen. Es ist ein sogenanntes "Single-Master-System", bei dem pro ei- tungsstrang ein Master den Datenaustausch steuert. Er ruft nacheinander die im Leitungsstrang liegenden Slaves auf und erwartet ihre Antwort. Jedem Slave ist als Erkennungszeichen eine eigene Adresse zugewiesen, über die er aufgerufen werden kann. Da jeder Slave 4 Bi -Daten übertragen kann und pro Lei- tungsstrang maximal 31 Slaves (31 Adressen) anschließbar sind, kann es an einer ASI-Leitung maximal 124 binäre Teil¬ nehmer bei statischem Betrieb der vier Datenleitungen geben. Im bidirektionalen Betrieb der vier Datenleitungen kann die Teilnehmerzahl auf 124 Aktuatoren (Ausgänge) plus 124 Senso- ren (Eingänge) erweitert werden.The actuator sensor interface (ASI) (the actuator sensor interface for automation, Werner Kriesel, Otto W. Madelung, Carl Hanser Verlag, Munich - Vienna, 1994) is for data exchange between a large number of participants intended. It is a so-called "single master system" in which one master controls the data exchange for each line strand. He calls the slaves lying in the wiring harness one after the other and awaits their response. Each slave is assigned its own address as an identifier, via which it can be called. Since each slave can transmit 4 Bi data and a maximum of 31 slaves (31 addresses) can be connected per line string, there can be a maximum of 124 binary participants on an ASI line with static operation of the four data lines. In the bidirectional operation of the four data lines, the number of participants can be expanded to 124 actuators (outputs) plus 124 sensors (inputs).
Beim Ausfall der Datenkommunikation auf dem Aktuator-Sensor- Interface besteht das Problem, daß die Schaltausgänge ihren momentanen Schaltzustand beibehalten, solange die Gleich- Spannung am Slave anliegt. Der Erfindung liegt daher die Aufgabe zugrunde, eine Schal¬ tungsanordnung zum definierten Abschalten der Aktuator-Aus- gänge im Aktuator-Sensor-Interface-System bei Ausfall der Datenkommunikation zu schaffen.If the data communication on the actuator-sensor interface fails, there is the problem that the switching outputs maintain their current switching state as long as the DC voltage is present at the slave. The invention is therefore based on the object of providing a circuit arrangement for the defined shutdown of the actuator outputs in the actuator / sensor interface system in the event of data communication failure.
Dies wird erfindungsgemäß mit einer Schaltungsanordnung mit den Merkmalen gemäß Patentanspruch 1 erreicht. Die Schal¬ tungsanordnung weist ein durch die Triggerimpulse ansteuer¬ bares Zeitglied auf, welches nach Ausbleiben der Trigger- impulse einen nachgeschalteten elektrischen Schalter öffnet, womit die Ausgangsschaltstufen von der Versorgung mit der Gleichspannung abgeschnitten werden.This is achieved according to the invention with a circuit arrangement with the features according to claim 1. The circuit arrangement has a timer which can be controlled by the trigger pulses and which opens a downstream electrical switch after the trigger pulses have failed, so that the output switching stages are cut off from the supply with the DC voltage.
Eine vorteilhafte Ausgestaltung der erfindungsgemäßen Schal- tungsanordnung besteht, wenn das Zeitglied eine Kombination aus einem Kondensator und einen ersten ohmschen Widerstand aufweist, die bei jedem Triggerimpuls voll aufgeladen wird und nach Ausbleiben der Triggerimpulse mit der aus dem Kon¬ densator und dem ersten ohmschen Widerstand resultierenden Zeitkonstanten entladen wird, so daß nach Unterschreiten der minimalen SteuerSpannung des nachfolgenden elektrischen Schalters dieser öffnet.An advantageous embodiment of the circuit arrangement according to the invention exists if the timing element has a combination of a capacitor and a first ohmic resistor, which is fully charged with each trigger pulse and, after the trigger pulses have failed, with the resultant from the capacitor and the first ohmic resistor Time constants are discharged so that after the minimum control voltage of the subsequent electrical switch is undershot, the latter opens.
Die Schaltungsanordnung wird vorteilhafter Weise im einzelnen derart ausgeführt, daß ein zweiter ohmscher Widerstand zwi¬ schen dem Anschluß und dem positiven Gleichspannungsanschluß liegt, daß eine Parallelschaltung aus dem Kondensator und dem ersten ohmschen Widerstand vorgesehen ist, die einerseits mit dem positiven Gleichspannungsanschluß und andererseits über eine Diode mit dem Emitter eines ersten Transistors elek¬ trisch verbunden ist, dessen Basis am Anschluß und dessen Kollektor an dem negativen Gleichspannungsanschluß anliegt, daß der Verbindungspunkt zwischen der Diode einerseits und dem ersten Widerstand und Kondensator andrerseits an die Basis eines zweiten Transistors geführt ist, dessen Kollektor mit dem negativen Gleichspannungsanschluß verbunden ist und dessen Emitter über einen dritten ohmschen Widerstand mit der Basis des als dritter Transistor ausgeführten Schalters ver¬ bunden ist, dessen Emitter am positiven Gleichspannungsan¬ schluß anliegt und an dessen Kollektor die Ausgangsschalt- stufen, z.B. Relais angeschlossen sind, wobei ein vierter ohmscher Widerstand zwischen der Basis des dritten Transi¬ stors und dem positiven Gleichspannungsanschluß liegt.The circuit arrangement is advantageously carried out in detail in such a way that a second ohmic resistance lies between the connection and the positive DC voltage connection, that a parallel connection of the capacitor and the first ohmic resistance is provided, which on the one hand with the positive DC voltage connection and on the other hand via a Diode is electrically connected to the emitter of a first transistor, the base of which is connected to the terminal and the collector of which is connected to the negative direct voltage terminal, that the connection point between the diode, on the one hand, and the first resistor and capacitor, on the other hand, is led to the base of a second transistor, the Collector is connected to the negative DC voltage connection and whose emitter is connected via a third ohmic resistor to the base of the switch designed as a third transistor, whose emitter is connected to the positive direct voltage connection and to whose collector the output switching stages, for example relays, are connected, a fourth ohmic resistor being connected between the The basis of the third transistor and the positive direct voltage connection lies.
Ein Ausführungsbeiεpiel der Erfindung wird im folgenden anhand einer Zeichnung näher erläutert:An exemplary embodiment of the invention is explained in more detail below with reference to a drawing:
FIG 1 zeigt die erfindungsgemäße Schaltungsanordnung zum definierten Abschalten von Ausgangsschaltstufen. In1 shows the circuit arrangement according to the invention for the defined switching off of output switching stages. In
FIG 2 sind vier Kurvenzüge mit voneinander abhängigen Signalen über den Datenverkehr, die Triggerimpulse, das Verhalten des Zeitglieds und die Ansteuerung der Ausgangsschaltstufen dargestellt.2 shows four curves with interdependent signals about the data traffic, the trigger pulses, the behavior of the timing element and the activation of the output switching stages.
In jedem Slave des eingangs beschriebenen "ASI-Systems" be- findet sich ein spezieller Schaltkreis 1, der gemäß FIG 1 mit einem Anschluß 2, dem sogenannten Data-Strobe-Anschluß, und Gleichspannungsanschlüssen 6,7 versehen ist. An diesen An¬ schlüssen 2,6,7 liegt die erfindungsgemäße Schaltungsanord¬ nung zum definierten Abschalten von Aktuator-Ausgängen 5 im ASI-System bei Ausfall der Datenkommunikation zwischen dem Master und dem jeweiligen Slave.In each slave of the "ASI system" described at the beginning there is a special circuit 1 which, according to FIG. 1, is provided with a connection 2, the so-called data strobe connection, and DC voltage connections 6, 7. The circuit arrangement according to the invention for the defined switching off of actuator outputs 5 in the ASI system is located at these connections 2, 6, 7 if the data communication between the master and the respective slave fails.
Die Schaltungsanordnung besteht im wesentlichen aus einem retriggerbaren Zeitglied 3 und einem von diesem ansteuerbaren elektronischen Schalter 4. Im einzelnen ist die Schaltung wie folgt aufgebaut:The circuit arrangement essentially consists of a retriggerable timer 3 and an electronic switch 4 which can be controlled by it. In detail, the circuit is constructed as follows:
Zwischen dem positiven Gleichspannungsanschluß 6 und dem Anschluß 2 ist' ein ohmscher Widerstand 12 geschaltet. Das retriggerbare Zeitglied 3 besteht aus zwei Transistoren 9,10 und einer Parallelschaltung aus einem Kondensator 11 und ei- nem ohmschen Widerstand 12, wobei die Parallelschaltung ei¬ nerseits mit dem positiven Gleichspannungsanschluß 6 verbun¬ den ist und andererseits über eine Diode 13 mit dem Emitter des Transistors 9, dessen Basis am Anschluß 2 und dessen Kollektor an dem negativen Gleichspannungsanschluß 7 anliegt. Der Verbindungspunkt 14 zwischen der Diode 13 einerseits und dem Widerstand 12 und dem Kondensator 11 andererseits ist an die Basis des Transistors 10 geführt, dessen Kollektor eben¬ falls mit dem negativen Gleichspannungsanschluß 7 verbunden ist.Between the positive DC voltage terminal 6 and the terminal 2 is an ohmic resistor 12 'is connected. The retriggerable timing element 3 consists of two transistors 9, 10 and a parallel connection of a capacitor 11 and a nem ohmic resistor 12, the parallel connection being connected on the one hand to the positive DC voltage connection 6 and on the other hand via a diode 13 to the emitter of the transistor 9, the base of which is connected to the connection 2 and the collector of which is connected to the negative DC voltage connection 7. The connection point 14 between the diode 13 on the one hand and the resistor 12 and the capacitor 11 on the other hand is led to the base of the transistor 10, the collector of which is also connected to the negative DC voltage connection 7.
Sein Emitter ist über einen ohmschen Widerstand 15 mit der Basis des weiteren Transistors 4 verbunden, der dem Zeitglied nachgeschaltet ist und dessen Emitter am positiven Gleich- spannungsanschluß 6 anliegt. An dessen Kollektor sind Aus¬ gangsschaltstufen 5, z.B. Relais, angeschlossen. Zwischen Basis von Transistor 4 und dem positiven Gleichspannungs¬ anschluß ist ein Widerstand 16 vorgesehen.Its emitter is connected via an ohmic resistor 15 to the base of the further transistor 4, which is connected downstream of the timing element and whose emitter is connected to the positive DC voltage connection 6. Output switching stages 5, e.g. Relay connected. A resistor 16 is provided between the base of transistor 4 and the positive direct voltage connection.
Die Funktion der Schaltung wird anhand von FIG 2 erläutert, wo vier Kurvenzüge dargestellt sind. Der oberste Kurvenzug zeigt unterschiedliche Phasen der EIN- bzw. AUS-Schaltung der Datenkommunikation zwischen dem Master und dem Slave. Der ASI-Schaltkreis 1 im Slave gibt bei jedem Masteraufruf an seine Adresse am Data-Strobe-Anschluß 2 einen Triggerimpuls Ul gemäß dem zweiten Kurvenzug in FIG 2 ab. Mit diesem Signal Ul wird das retriggerbare Zeitglied getriggert. Bei Ausblei¬ ben der Masteraufrufe und damit der Triggerimpulse wird nach Ablauf der vom Zeitglied vorgegebenen Zeit tz der nachge- schaltete Transistor 4 geöffnet, und die angeschlossenen Aus¬ gangsschaltstufen 5 schalten ab. Dies verdeutlichen der drit¬ te Kurvenzug U2 mit dem Potential des Verbindungspunktes 14 bezogen auf den negativen Gleichspannungsanschluß 7, was der Differenzspannung zwischen der Gleichspannung und der Span- nung am Kondensator 11 entspricht sowie der vierte Kurvenzug mit der VersorgungsSpannung U3 der Ausgangsschaltstufen 5. The function of the circuit is explained with reference to FIG 2, where four curves are shown. The top curve shows different phases of the ON and OFF switching of data communication between the master and the slave. The ASI circuit 1 in the slave emits a trigger pulse U 1 according to the second curve in FIG. 2 to its address on the data strobe connection 2 with each master call. The retriggerable timer is triggered with this signal U1. If the master calls and thus the trigger pulses fail, the downstream transistor 4 is opened after the time tz specified by the timing element has elapsed, and the connected output switching stages 5 switch off. This is illustrated by the third curve U2 with the potential of the connection point 14 in relation to the negative DC voltage connection 7, which corresponds to the differential voltage between the DC voltage and the voltage at the capacitor 11 and the fourth curve with the supply voltage U3 of the output switching stages 5.

Claims

Patentansprüche claims
1. Schaltungsanordnung zum definierten Abschalten von Aus¬ gangsschaltstufen (5), die über einen Schaltkreis (1) eines mit einem Master kommunizierenden Slaves, insbesondere in einem ASI-System, mit Gleichspannung versorgt werden, wobei der Schaltkreis (1) einen positiven (6), einen negativen Gleichspannungsanschluß (7) und einen Anschluß (2) aufweist, an dem nur während der Datenkommunikation zwischen dem Master und dem Slave Triggerimpulse anstehen, mit einem durch die1. Circuit arrangement for the defined switching off of output switching stages (5), which are supplied with DC voltage via a circuit (1) of a slave communicating with a master, in particular in an ASI system, the circuit (1) having a positive (6 ), a negative DC voltage connection (7) and a connection (2), to which trigger pulses are only present during data communication between the master and the slave, with a through the
Triggerimpulse ansteuerbaren Zeitglied (3), welches nach Aus¬ bleiben der Triggerimpulse einen nachgeschalteten elektri¬ schen Schalter (4) öffnet, womit die Ausgangsschaltstufen (5) von der Versorgung mit der Gleichspannung abgeschnitten wer- den.Trigger pulse triggerable timer (3), which opens a downstream electrical switch (4) after the trigger pulses remain off, whereby the output switching stages (5) are cut off from the supply with the DC voltage.
2. Schaltungsanordnung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß das Zeitglied (3) eine Kombination aus einem Kondensator (11) und einem ersten ohm- sehen Widerstand (8) aufweist, die bei jedem Triggerimpuls voll aufgeladen wird und nach Ausbleiben der Triggerimpulse mit der aus dem Kondensator (11) und dem Widerstand (8) re¬ sultierenden Zeitkonstanten entladen wird, so daß nach Unter¬ schreiten der minimalen Steuerspannung des nachfolgenden Schalters (4) dieser öffnet.2. Circuit arrangement according to claim 1, characterized in that the timing element (3) has a combination of a capacitor (11) and a first ohmic resistor (8), which is fully charged with each trigger pulse and after the absence of the trigger pulses with the the resulting time constant is discharged from the capacitor (11) and the resistor (8), so that after the minimum control voltage of the subsequent switch (4) has fallen below, the latter opens.
3. Schaltungsansordnung nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß ein zwei¬ ter ohmscher Widerstand (12) zwischen dem Anschluß (2) und dem positiven Gleichspannungsanschluß (6) liegt, daß eine Parallelschaltung aus dem Kondensator (11) und dem ersten ohmschen Widerstand (8) vorgesehen ist, die einerseits mit dem positiven Gleichspannungsanschluß (6) und anderseits über eine Diode (13. mit dem Emitter eines ersten Transistors (9) elektrisch verbunden ist, dessen Basis am Anschluß (2) und dessen Kollektor an dem negativen Gleichspannungsanschluß (7) anliegt, daß der Verbindungspunkt (14) zwischen der Diode (13) einerseits und dem ersten Widerstand (8) und dem Konden¬ sator (11) andererseits an die Basis eines zweiten Transi¬ stors (10) geführt ist, dessen Kollektor mit dem negativen Gleichspannungsanschluß (7) verbunden ist und dessen Emitter über einen dritten ohmschen Widerstand (15) mit der Basis des als dritter Transistor (4) ausgeführten Schalters verbunden ist, dessen Emitter am positiven Gleichspannungsanschluß (6) anliegt und an dessen Kollektor die Ausgangsschaltstufen (5), z.B. Relais, angeschlossen sind, wobei ein vierter ohmscher Widerstand (16) zwischen der Basis des dritten Transistors (4) und dem positiven Gleichspannungsanschluß (6) liegt. 3. Circuit arrangement according to claim 1 or 2, characterized in that a two-ohmic resistor (12) between the terminal (2) and the positive DC voltage terminal (6) that a parallel connection of the capacitor (11) and the first ohmic resistor (8) is provided, which is electrically connected on the one hand to the positive direct voltage connection (6) and on the other hand via a diode (13.) To the emitter of a first transistor (9), the base of which is connected to the connection (2) and the collector of the negative direct voltage connection (7) that the connection point (14) between the diode (13) on the one hand and the first resistor (8) and the capacitor (11) on the other hand is led to the base of a second transistor (10), the collector of which has the negative one DC voltage connection (7) is connected and its emitter is connected via a third ohmic resistor (15) to the base of the switch designed as a third transistor (4), the emitter of which is connected to the positive DC voltage connection (6) and the output switching stages (5) on the collector. , for example relays, are connected, a fourth ohmic resistor (16) being located between the base of the third transistor (4) and the positive DC voltage connection (6).
EP96900266A 1995-01-24 1996-01-10 Circuit for switching the actuator outputs off in an asi system in the event of data communication failure Withdrawn EP0806084A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19502118 1995-01-24
DE19502118A DE19502118A1 (en) 1995-01-24 1995-01-24 Circuit arrangement for switching off the actuator outputs in the ASI system in the event of data communication failure
PCT/DE1996/000025 WO1996023357A1 (en) 1995-01-24 1996-01-10 Circuit for switching the actuator outputs off in an asi system in the event of data communication failure

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EP0806084A1 true EP0806084A1 (en) 1997-11-12

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WO (1) WO1996023357A1 (en)

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JP2000066706A (en) * 1998-08-21 2000-03-03 Matsushita Electric Ind Co Ltd Robot controller and its control method
DE102013100467A1 (en) 2013-01-17 2014-07-17 Netstal-Maschinen Ag Microprocessor-controlled control device for an injection molding plant

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GB1256638A (en) * 1969-08-02 1971-12-08
AT325108B (en) * 1970-03-13 1975-10-10 Siemens Ag Oesterreich CIRCUIT TO ACHIEVE A FAST INCREASE AND SLOW DECREASE IN THE OUTPUT VOLTAGE OF A REINFORCING ELEMENT
DD208898A1 (en) * 1982-07-28 1984-04-11 Inst F Regelungstechnik Im Kom CIRCUIT ARRANGEMENT FOR TEMPORARY LOAD SHUTDOWN

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Title
See references of WO9623357A1 *

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WO1996023357A1 (en) 1996-08-01

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