DD208898A1 - CIRCUIT ARRANGEMENT FOR TEMPORARY LOAD SHUTDOWN - Google Patents

Abstract

The invention relates to a circuit arrangement for time-dependent load connection by a control voltage with the aim that the delay time is not effective until load shutdown. The object of the invention is to develop a simple circuit arrangement for delayed load connection and undamped load disconnection using an RC element. According to the invention, the control signal is fed both via an RC element to the base of a first switching transistor and via a resistor to the base of a second switching transistor. The emitter-collector paths of the transistors and the load are connected in series between supply voltage and ground. Application: Power supply of electronic assemblies, actuators.

Description

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Inventor: Dipl.-Ing. Helmut John Berlin, 23-07.1982

Dipl.-i-ag .. i-iens-Dieter Seidel P 1304 ·

Zustellungsbevollm .:

Institute of Control Engineering

in the combine VEB EA ¥ Berlin-Treptow

"Friedrich Ebert"

Fri.

1055 Berlin, Storkower Str. 101 Büro für Scirutzrechte

Circuit arrangement for time-dependent jjas tab circuit

H 03 E --- 17/28

Field of application of the invention

The invention relates to a circuit arrangement for time-dependent load switching by a 3teuerspannung, for example, for the power supply of electronic modules.

Characteristic of the known technical solutions

It is well known that the relay delay and turn-off delays can be realized by using the relay self-delay. Hachteil of these arrangements is the large wear of the component and the associated low., Reliability. In addition, the avoidance of egg? Switching delays realize only unsatisfactory, ^ uch the range of settings for the switch-off delay is low. '.

Furthermore, circuit arrangements are known which, for the delayed Las ν shutdown use an HC element whose disadvantage is that the delay time is in principle effective even with load connection.

Further, arrangements are known which include ZG7GHG-G songs, e.g. 148 598 or a diode connected to diodes, HC. B, 103 110, to achieve different delay times

for load or load shutdown use. The disadvantage of these arrangements is also that, due to circuit technology, when switching-off delays come into effect, switch-on delays can not be avoided.

Object of the invention

The aim of the invention is to ensure the turn-off delay of a load without turn-on delay by a control voltage.

read the invention

The object of the invention is to develop a simple circuit arrangement for time-dependent load shutdown and instantaneous load connection using an HC element.

According to the invention, the object is achieved by virtue of the fact that the control voltage fed to the input of the circuit via an -uperation module via an EC element for the delayed signal path to the "base" of a first switching transistor and. is passed through a resistor for the instantaneous signal path to the base of a second Schalttrahsistors. The emitter-collector paths of the two transistors are connected in parallel and arranged in series with the load resistance between the supply voltage and ground. In the event of a positive jump of the control voltage, the second transistor will go over the instantaneous. Signal path immediately conductive, which also has the undelayed connection of the load and thus the output signal result. At the same time, the capacitor of the delayed signal path is charged via its resistor. Thus, the first transistor switches on delayed. If the control voltage is negative, the second transistor is immediately blocked, but the output signal still remains at high potential. Only after 'degradation of the Sondensatorladung the first switching transistor is blocked. The load and thus the

The output signal is therefore switched off with a delay.

embodiment

5 shows the circuit arrangement Pig. 2 according to the invention the waveform of the voltage

At low potential at the control input ST of the ^ .befoereitungsbaustein j and thus high potential at the input 2, the capacitor C is discharged. Thus, the transistors T and T are disabled and the output is low potential. '· · -.

With a positive jump at the control input ST and thus a negative jump at the input 3, the switching transistor T _p

immediately conductive and at the output ^ - high-potential appears. The capacitor C is charged via the resistor. Thus, the first switching transistor T 'switches on delayed. Since the second switching transistor T _{p is} already switched on, the output signal does not change. In case of a negative voltage jump at the control input ST _; and thus, positive voltage jump at the "input Ξ, the transistor T _{p is} immediately blocked via the resistor R 1, but the output signal remains high-potential, since the transistor T is still switched on, only after the charge of C has been depleted by the Base current of the first transistor T ^ or on the, 'Viderstände' R ^ and R- the first transistor T. is turned off and the output A low potential. _:

Claims (1)

τ ι ν ν ι Srfindungsanspruch Circuit arrangement for time-dependent Las tab circuit and instantaneous load connection by a control voltage, the _; via a processing module to the input of the circuit, the time delay being realized with an EC element, characterized in that the input (E) is connected via an RC element (H, C) to the base of a first switching transistor ( ¹ T,.) And a resistor (Hp) to the base of a second transistor ('T ₂ ) is connected and that the Smitter-Eollektor-sections of the transistors (T'; Tp) connected in parallel and in series with the load resistor ( R ₁ -) between the supply voltage (TX-.) And ground (M) are arranged. - xiiersa