EP0788144B1 - Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid - Google Patents

Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid Download PDF

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Publication number
EP0788144B1
EP0788144B1 EP96830039A EP96830039A EP0788144B1 EP 0788144 B1 EP0788144 B1 EP 0788144B1 EP 96830039 A EP96830039 A EP 96830039A EP 96830039 A EP96830039 A EP 96830039A EP 0788144 B1 EP0788144 B1 EP 0788144B1
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European Patent Office
Prior art keywords
layer
forming
thickness
oxide
masking layer
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Expired - Lifetime
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EP96830039A
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English (en)
French (fr)
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EP0788144A1 (de
Inventor
Livio Baldi
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STMicroelectronics SRL
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STMicroelectronics SRL
SGS Thomson Microelectronics SRL
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Priority to DE69630864T priority Critical patent/DE69630864T2/de
Priority to EP96830039A priority patent/EP0788144B1/de
Priority to US08/792,893 priority patent/US5817557A/en
Publication of EP0788144A1 publication Critical patent/EP0788144A1/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Definitions

  • the present invention relates to a process of fabricating tunnel-oxide nonvolatile memory devices, in particular EEPROM memories.
  • EEPROM memories are programmed by storing electric charges in a floating gate region and tunneling current through a thin oxide region (Fowler-Nordheim tunneling); the thin oxide region (tunnel oxide) is surrounded by a thicker oxide region (gate oxide, used in the sensing transistor of the cell for reading the cell).
  • the gate oxide region located between the floating gate region and the substrate provides for:
  • EEPROM memories also require an implanted region (normally phosphorous for N-channel cells) beneath and to the side of the tunnel oxide region and partially superimposed on the drain region of the cell to ensure electric continuity between the substrate region beneath the tunnel oxide (tunnel area) and the drain region of the cell.
  • implanted region normally phosphorous for N-channel cells
  • EEPROM memories of the type described it is desirable to minimize the tunnel oxide area, which seriously affects the overall area of the cell and hence of the memory itself, and so enable the fabrication of memories with smaller, i.e. a greater number of, cells. Moreover, reducing the tunnel area also provides for enhanced coupling of the floating gate and control gate regions, which therefore explains the effort currently being made to reduce the size of the tunnel oxide region to the minimum permitted by the lithographic process by which it is formed.
  • Figures 2 and 3 show a portion of a known memory device 1 comprising a cell 2 and a selection transistor 3.
  • Number 10 in Figures 2 and 3 indicates the P-type substrate of device 1, which is formed, using or not the twin-tub technique, inside a wafer of monocrystalline semiconductor material (silicon), and which houses an N-type source region 11 of the cell, an N-type implanted electric continuity region 12, an N-type drain/source region 13 defining the drain region of cell 2 and the source region of selection transistor 3, and an N-type drain region 14 for selection transistor 3. Regions 11-14 all face the surface 15 of substrate 10.
  • a gate oxide region 18 of cell 2 incorporating a thin tunnel oxide region 19; a floating gate region 20 of polycrystalline silicon; an interpoly dielectric region 21; and a control gate region 22 of polycrystalline silicon.
  • a gate oxide region 25 and a gate region 26 of polycrystalline silicon both pertaining to selection transistor 3.
  • An intermediate dielectric layer 30 covers the structure and insulates the various layers.
  • floating gate region 20 is insulated and surrounded at the top and sides by interpoly dielectric layer 21 (preferably an ONO layer comprising superimposed silicon Oxide-silicon Nitride-silicon Oxide) and at the bottom by gate oxide 18 and tunnel oxide 19 of the cell.
  • interpoly dielectric layer 21 preferably an ONO layer comprising superimposed silicon Oxide-silicon Nitride-silicon Oxide
  • Portion 15' of surface 15 beneath tunnel oxide region 19 forms the tunnel area; the distance between floating gate region 20 and surface 15 is minimum (about 7-10 nm (70-100 ⁇ )) at portion 15', and is greater (about 20 nm (200 ⁇ )) at gate oxide region 18; and portion 31 of the substrate between continuity region 12 and source region 11 forms the channel of cell 2.
  • electric continuity region 12 and channel region 31 are defined laterally, widthwise, by a thick field oxide layer 32.
  • Device 1 is formed using the masks illustrated in Figure 1, in which 4 indicates the tunnel mask; 5 (dotted line) the mask for defining the floating gate region widthwise; 6 a self-align etching mask (explained below); 7 the active area mask (also corresponding to the source/drain implant of cell 2 and selection transistor 3); and 8 a mask for forming drain contact D.
  • Device 1 is fabricated using a typical CMOS (twin- or single-tub) process wherein, commencing with P-type substrate 10 and using the nitride active area mask 7 covering the active area of cell 2 and transistor 3, a field oxide layer 32 ( Figure 3) is grown to define the active areas of device 1; after growing a sacrificial oxide layer and a photolithographic masking step, capacitors are implanted to form continuity region 12; after removing the sacrificial oxide layer, a pre-gate oxide layer 42 (eventually forming part of gate region 18 of cell 2 and gate oxide region 25 of selection transistor 3) is deposited; tunnel mask 5 is deposited, comprising a layer of photosensitive material 43 covering the whole of layer 42 except for a window 41 where tunnel region 19 is to be formed ( Figure 4); and dedicated etching is performed to clean surface 15, remove the exposed part of layer 42, and so obtain the intermediate structure shown in Figure 5.
  • CMOS twin- or single-tub
  • tunnel mask 5 is removed; tunnel oxide region 19 is grown; and, at the same time, the thickness of pre-gate oxide layer 42 also increases to form a gate oxide layer 44 of a thickness equal to the desired final thickness of gate oxide region 18 (and region 25), thus resulting in the intermediate structure shown in Figure 6.
  • a layer of polycrystalline silicon (poly1) 45 is then deposited and doped to give the intermediate structure shown in Figure 7.
  • the process may proceed in various ways, depending on whether memories with one or two polycrystalline silicon levels are being formed, on whether or not the two polycrystalline silicon layers are shorted at the circuit transistors, etc..
  • a process currently employed by the Applicant comprises the steps of: masking poly1 layer 45 to define the floating gate regions 20 of the cells widthwise (horizontal direction in Figures 1 and 3); depositing the composite ONO layer; etching ONO layer 21 at the selection transistors and at the circuit portion of device 1; depositing and doping a second polycrystalline silicon layer (poly2); depositing a tungsten silicide layer (not shown in Figures 2 and 3 for the sake of simplicity); etching the poly2 layer without removing the mask; masking and self-align etching the ONO layer and etching the poly1 layer using mask 6 to define floating gate and control gate regions 20 and 22 lengthwise (vertical direction in Figure 1); removing mask 6; source/drain implanting to form regions 11, 13, 14; and finish steps including forming intermediate dielectric layer 30, forming the contacts and interconnecting layer/s, and depositing the passivation layer.
  • tunnel oxide region 19 is especially critical for various reasons:
  • Patent Abstracts of Japan, vol 13, no. 58 (E-714), 9 February 1989 & JP-A-63 246875 disclose a process for manufacturing EEPROM memories.
  • This known process is disadvantageous since it is susceptible to stress on the surface of gate oxide layer, due to the different coefficient of expansion of gate oxide layer and nitride layer.
  • any defects (pinholes) in the nitride may result in etching of gate oxide layer when forming the openings of the tunnel oxide regions, and hence in impaired quality of the gate oxide.
  • a gate oxide layer 50 is grown on a substrate 10 of semiconductor material, typically monocrystalline silicon doped to present P-type conductivity, and housing an N-type continuity region 12. Unlike the known process described above, layer 50 already presents the desired final thickness of gate oxide region 18 ( Figures 2 and 3).
  • a thin layer (20-50 nm) of polycrystalline or amorphous silicon 51 is then deposited, preferably doped in situ, e.g. by adding phosphine or arsine in known manner to the silane in the deposition furnace to improve its electric characteristics; and a thin layer (20-50 nm) of silicon nitride 52 is deposited to obtain the intermediate structure shown in Figure 8.
  • a photolithographic masking step is performed to form a resist mask 54 presenting a window 55 at the portion in which the tunnel oxide region is to be formed ( Figure 9); and nitride layer 52 and polycrystalline or amorphous silicon layer 51 are plasma etched to give the intermediate structure shown in Figure 9, wherein layers 51 and 52 define a tunnel window 56 of the same area as window 55.
  • nitride layer 52 is wet removed, e.g. using a hot phosphoric acid solution at 150°C; the first polycrystalline silicon layer 45 is deposited to give the intermediate structure in Figure 12; and the usual steps for forming intermediate dielectric 21, depositing the second polycrystalline silicon layer, patterning and implanting, etc. are performed as described above.
  • opening 57 in gate oxide layer 50 is formed of width l (about 0.5-0.7 ⁇ m) corresponding to one side of tunnel oxide region 19 (square in shape when viewed from above), so that the thickness of the mask (equal to the total thickness of layers 51 and 52, i.e. 40-100 nm) is much smaller than the width of opening 57.
  • nitride layer 52 permits much more thorough washing of the gate oxide surface than that permitted in the known process by the presence of exposed pre-gate oxide. For example, washing may be performed using oxide etching solutions (in particular, diluted or buffered hydrofluoric acid solutions).
  • the protective polycrystalline or amorphous silicon layer 51 is not removed, and subsequently contacts first polycrystalline silicon layer 45 with which it forms the floating gate region. The presence of layer 51 therefore in no way interferes with the formation of cell 2.
  • nitride as the masking material when etching oxide layer 50 is especially advantageous on account of nitride being depositable to a thickness equal to a fraction of the width of the tunnel oxide region of the cells (0.5-0.7 ⁇ m) while at the same time maintaining the required resistance to etching of the oxide. Moreover, it is removable without damaging the existing layers, i.e. tunnel oxide 19 and polycrystalline or amorphous silicon layer 51 in the described embodiment.

Claims (11)

  1. Verfahren zur Herstellung von nicht-flüchtigen Tunnel-Oxyd-Speichereinrichtungen, insbesondere EEPROM-Speichern, welches folgende Schritte aufweist:
    Bilden einer Schicht aus einem isolierenden Material (50) mit einer ersten Dicke auf einem Halbleitersubstrat (10), Niederschlagen einer Schutzschicht (51) auf dem Halbleitermaterial auf der Oberseite der Schicht aus isolierendem Material (50),
    Bilden einer Maskierungsschicht (52).aus einem Material mit chemisch-physikalischen Widerstandseigenschaften gegenüber Ätzbedingungen der Schicht aus Isoliermaterial (50) auf der Oberseite der Schutzschicht (51);
    Bilden von Öffnungen (57) mit einer Größe (1), die größer als die Dicke der Maskierungsschicht (52) ist, auf der Maskierungsschicht, der Schutzschicht und der Schicht aus Isoliermaterial;
    Bilden eines Tunnel-Oxyds (19) mit einer zweiten Dicke, die kleiner ist als die erste Dicke, innerhalb dieser Öffnungen.
  2. Verfahren nach Anspruch 1,
    dadurch gekennzeichnet, dass das Material der Maskierungsschicht (52) thermische Widerstandscharakteristiken liefert, die vergleichbar sind mit jenen von Keramikmaterialien und gegenüber einer Oxydation undurchlässig ist.
  3. Verfahren nach Anspruch 1 oder 2,
    dadurch gekennzeichnet, dass die Maskierungsschicht (52) eine Dicke aufweist, die kleiner ist als ein Drittel der Breite bzw. Größe (1) der Öffnung (57).
  4. Verfahren nach wenigstens einem der vorangehenden Ansprüche,
    dadurch gekennzeichnet, dass die Maskierungsschicht (52) aus Nitrid besteht.
  5. Verfahren nach einem der vorangehenden Ansprüche,
    dadurch gekennzeichnet, dass der Schritt der Bildung einer Maskierungsschicht folgende Schritte aufweist:
    Niederschlagen der Maskierungsschicht (52);
    Bildung einer Maske (54) aus fotoempfindlichem Material, die erste Fenster (55) aufweist an den zu erzeugenden Öffnungen (57);
    Bilden zweiter Fenster (56) in der Maskierungsschicht innerhalb des ersten Fensters; und
    Entfernen der Maske aus fotoempfindlichem Material.
  6. Verfahren nach Anspruch 5,
    dadurch gekennzeichnet, dass die erste Dicke der Schicht aus Isoliermaterial (50) gleich einer vorbestimmten gewünschten Enddicke ist; und
    dass der Schritt des Bildens eines Tunnel-Oxyds den Schritt aufweist, dass das Tunnel-Oxyd (19) innerhalb der zweiten Fenster (56) in der Maskierungsschicht (52) aufgewachsen wird.
  7. Verfahren nach Anspruch 6,
    dadurch gekennzeichnet, dass der Schritt des Aufwachsens des Tunnel-Oxyds (19) gefolgt wird durch die Schritte des Entfernens der Maskierungsschicht (52) und des Niederschlagens bzw. Aufsprühens einer Halbleiter-Gate-Schicht (45).
  8. Verfahren nach Anspruch 7,
    dadurch gekennzeichnet, dass der Schritt der Bildung der zweiten Fenster (56) auch beinhaltet den Schritt der Entfernung der freigelegten Abschnitte der Schutzschicht (51).
  9. Verfahren nach Anspruch 8,
    dadurch gekennzeichnet, dass die Halbleiter-Gate-Schicht (45) über der Schutzschicht niedergebracht wird.
  10. Verfahren nach Anspruch 8 oder 9,
    dadurch gekennzeichnet, dass die Schutzschicht (51) aus einem polykristallinen oder amorphen Halbleitermaterial besteht.
  11. Verfahren nach Anspruch 10,
    dadurch gekennzeichnet; dass die Schutzschicht (51) eine dotierte N-Typ-Schicht ist.
EP96830039A 1996-01-13 1996-01-31 Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid Expired - Lifetime EP0788144B1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE69630864T DE69630864T2 (de) 1996-01-31 1996-01-31 Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid
EP96830039A EP0788144B1 (de) 1996-01-31 1996-01-31 Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid
US08/792,893 US5817557A (en) 1996-01-13 1997-01-31 Process of fabricating tunnel-oxide nonvolatile memory devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96830039A EP0788144B1 (de) 1996-01-31 1996-01-31 Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid

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EP0788144A1 EP0788144A1 (de) 1997-08-06
EP0788144B1 true EP0788144B1 (de) 2003-11-26

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EP96830039A Expired - Lifetime EP0788144B1 (de) 1996-01-13 1996-01-31 Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid

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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19534780A1 (de) * 1995-09-19 1997-03-20 Siemens Ag Verfahren zum Erzeugen sehr kleiner Strukturweiten auf einem Halbleitersubstrat
US6127222A (en) * 1997-12-16 2000-10-03 Advanced Micro Devices, Inc. Non-self-aligned side channel implants for flash memory cells
US5972752A (en) * 1997-12-29 1999-10-26 United Semiconductor Corp. Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile
JP4081854B2 (ja) * 1998-05-11 2008-04-30 沖電気工業株式会社 半導体装置の製造方法
KR100267010B1 (ko) * 1998-06-15 2000-09-15 윤종용 반도체 장치의 제조 방법
US6573141B1 (en) * 1999-03-12 2003-06-03 Zilog, Inc. In-situ etch and pre-clean for high quality thin oxides
US6617204B2 (en) * 2001-08-13 2003-09-09 Macronix International Co., Ltd. Method of forming the protective film to prevent nitride read only memory cell charging
JP2005236062A (ja) * 2004-02-20 2005-09-02 Nec Electronics Corp 不揮発性半導体記憶装置の製造方法
KR100572327B1 (ko) * 2004-07-06 2006-04-18 삼성전자주식회사 불휘발성 메모리 소자의 터널링 절연막을 형성하는 방법

Citations (1)

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Publication number Priority date Publication date Assignee Title
EP0597124A1 (de) * 1992-05-29 1994-05-18 Citizen Watch Co. Ltd. Nichtflüchtige halbleiterspeicheranordnung, halbleiteranordnung und verfahren zur herstellung

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JP2670262B2 (ja) * 1987-01-09 1997-10-29 株式会社東芝 半導体装置の製造方法
JPS63246875A (ja) * 1987-04-01 1988-10-13 Mitsubishi Electric Corp 半導体記憶装置とその製造方法
JPH067574B2 (ja) * 1987-04-02 1994-01-26 日本電気株式会社 半導体装置
JP2577383B2 (ja) * 1987-06-16 1997-01-29 株式会社東芝 不揮発性半導体メモリ装置の製造方法
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5429970A (en) * 1994-07-18 1995-07-04 United Microelectronics Corporation Method of making flash EEPROM memory cell

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0597124A1 (de) * 1992-05-29 1994-05-18 Citizen Watch Co. Ltd. Nichtflüchtige halbleiterspeicheranordnung, halbleiteranordnung und verfahren zur herstellung

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DE69630864T2 (de) 2004-11-04
DE69630864D1 (de) 2004-01-08
US5817557A (en) 1998-10-06
EP0788144A1 (de) 1997-08-06

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