EP0783767A1 - Bipolartransistor zur benutzung in linearen verstärkern - Google Patents
Bipolartransistor zur benutzung in linearen verstärkernInfo
- Publication number
- EP0783767A1 EP0783767A1 EP95944784A EP95944784A EP0783767A1 EP 0783767 A1 EP0783767 A1 EP 0783767A1 EP 95944784 A EP95944784 A EP 95944784A EP 95944784 A EP95944784 A EP 95944784A EP 0783767 A1 EP0783767 A1 EP 0783767A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- bipolar transistor
- conductivity type
- dopant concentration
- order
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000002019 doping agent Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims 4
- 239000002184 metal Substances 0.000 claims 4
- 238000000034 method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
- H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
- H01L29/66303—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor with multi-emitter, e.g. interdigitated, multi-cellular or distributed emitter
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
Definitions
- This invention relates generally to linear amplifiers, and more particularly the invention relates to a bipolar transistor for use in a linear amplifier which reduces harmonic distortion.
- any device embedded in a real amplifier will generate a number of intermodulation products when driven with an input signal composed of multiple frequencies.
- Second order distortion products can be generally minimized by circuit construction, so the interest in distortion reduction at the device level begins with third order and higher products.
- the amplifier illustrated in Fig. 1A has a two-tone input signal of equal amplitude as illustrated in Fig. IB, which will produce four third order intermodulation products (2f x ⁇ f 2 and 2f 2 ⁇ f ⁇ ) , along with the amplified input signal ( f ⁇ , f 2 ) as illustrated in Fig. IC.
- the difference products are typically considered since sum products typically fall outside of the amplifier bandwidth.
- bipolar junction transistor devices have been designed on the basis of emitter perimeter utilization, large ballast resistors, and low parasitic capacitances which are all good conditions to achieve large power output capability.
- typical devices experience a "hill and valley" on the third order distortion curve as shown in Fig. 2 that limits the minimum distortion values in the operating dynamic range to the maximum value of distortion encountered on the "hill" of the curve.
- a device designed to operate as a driver in a Class AB linear amplifier for cellular base station applications has to maintain third order distortion products better than 40dB below the fundamental carrier frequencies (or dBc) when operated at rated power or below, then the design of a Class AB driver device requires a "hill" of 40dBc or better.
- the "hill and valley” behavior is believed to be related to a non-linearity in the value of the intrinsic base resistance (Rbb) that is also related to the onset of the current crowding of the emitter fingers.
- This variation in the intrinsic base resistance (Rbb) occurs at low power inputs and is believed to be a direct result of the side wall component of the base current.
- This side wall component is due to emitter-base space charge and surface recombination.
- Modern high power, high frequency bipolar transistors are designed with a large perimeter/area ratio emitter which increases the relative importance of this base current component which has been demonstrated by computer simulation as shown in Fig. 3 to effect the size and magnitude of the "hill” in the power transfer curve.
- the present invention is directed to a bipolar transistor device design and fabrication process which minimizes sources of third order and higher non-linearity.
- a bipolar junction transistor is provided which has a ratio of emitter width to base depth between three and four which has proved to be optimum in minimizing emitter current crowding over a large range of low base current values while maintaining large intrinsic gain.
- ballast resistance of the device is minimized, contingent to the demand that the device be sufficiently rugged to sustain a device output impedance mismatch. The resulting device provides reduced distortion in third order and higher intermodulation products.
- Figs. 1A, IB, and IC illustrate a convention non ⁇ linear amplifier, two-tone input signals, and output signals including third order intermodulation products, respectively.
- Fig. 2 is a graph illustrating third order distortion.
- Fig. 3 is a computer simulated plot of side wall base current (Ise) and third order intermodulation output Power (dBc) vs. Carrier Output Power.
- Fig. 4 is a side view in section illustrating the structure of bipolar junction transistor in accordance with the invention.
- Figs. 5A-5D are section views illustrating a process in accordance with the invention for fabricating the device of Fig. 4.
- Fig. 4 is a section view of a bipolar junction transistor in accordance with one embodiment of the invention for realizing reduced third harmonic intermodulation distortion in a linear amplifier.
- the device includes a substrate 10 of N-doped silicon with an N-doped epitaxial layer 11 formed thereon.
- epitaxial layer 11 forms the collector region of the bipolar transistor and is of high resistivity and sufficiently thin to provide constant and low output capacitance.
- a p-ring 21 surrounds the active transistor region for breakdown enhancement, and a p base region 24 extends from ring 21 across the surface of the epitaxial layer 11.
- Shallow N-doped emitter regions 25 are then formed in the surface of the base region 24, and emitter contact fingers 30 contact the emitter regions 25 through openings in silicon oxide layer 20 along with the base contact fingers 32.
- FIG. 5A Fabrication of the device of Fig. 4 is illustrated in the section views of Figs. 5A through 5D.
- the process starts with an N-type silicon substrate 10 having an arsenic dopant concentration on the order of 10 19 cm "3 on which a very thin epitaxial N- layer 11 is grown to define the material characteristics responsible for collector-base breakdown voltage and capacitance.
- the dopant concentration in epitaxial layer 11 will be on the order of 2.5 x l ⁇ 16 cm "3 and the thickness of the epitaxial layer will be on the order of four microns.
- a silicon oxide layer 20 is then grown or deposited on the surface of the epitaxial layer 11.
- a standard photo resist masking technique is used to define an opening through oxide layer 20 to expose the silicon surface area into which is diffused or implanted a p-dopant, boron for example, to form the p-ring 21.
- P-ring 21 enhances breakdown of the transistor region within the ring and the p-type dopant is diffused to a desired depth, such as one and a half microns.
- a second opening is formed inside the ring area and the p-type base 24 is formed by diffusion or by implantation of boron dopant on the order of 5xl0 18 atoms cm "3 to the desired depth such as 0.6 micron as shown in Fig. 5C.
- Oxide is then regrown or deposited over the base region.
- a composite mask with both emitter and base contact openings is etched in the oxide covering the base, and an N-type dopant such as arsenic is implanted to form the emitter 25 having a width on the order of 2.0 microns and dopant concentration on the order of 10 21 atoms cm “3 using an enlarged opening emitter resist layer 27 as a protective mask as shown in Fig. 5D.
- the photo resist is removed and the emitter implant thermally activated, the device is completed by depositing or sputtering the emitter and base metal fingers and bonding pads as shown in Fig. 4.
- the described bipolar junction transistor in which the ratio of emitter width to the base depth is between 3 and 4 minimizes emitter current crowding over a large range of low base current values while maintaining large intrinsic gain.
- the ballast resistance in the fabrication approach is made as small as possible contingent on the demand that the device be rugged enough to sustain the desired output impedance mismatch. Accordingly, third order and higher intermodulation distortion is significantly reduced to provide improved Class A and Class AB RF power amplifiers.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Bipolar Transistors (AREA)
- Amplifiers (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31616694A | 1994-09-30 | 1994-09-30 | |
US316166 | 1994-09-30 | ||
PCT/US1995/006479 WO1996010844A1 (en) | 1994-09-30 | 1995-05-22 | Bipolar transistor for use in linear amplifiers |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0783767A1 true EP0783767A1 (de) | 1997-07-16 |
EP0783767A4 EP0783767A4 (de) | 1997-12-29 |
Family
ID=23227798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95944784A Withdrawn EP0783767A4 (de) | 1994-09-30 | 1995-05-22 | Bipolartransistor zur benutzung in linearen verstärkern |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0783767A4 (de) |
JP (1) | JPH10509558A (de) |
KR (1) | KR970706613A (de) |
AU (1) | AU2555095A (de) |
WO (1) | WO1996010844A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9807115D0 (en) * | 1998-04-03 | 1998-06-03 | Zetex Plc | Alignment method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4566176A (en) * | 1984-05-23 | 1986-01-28 | U.S. Philips Corporation | Method of manufacturing transistors |
US5148252A (en) * | 1990-02-13 | 1992-09-15 | Kabushiki Kaisha Toshiba | Bipolar transistor |
EP0609052A2 (de) * | 1993-01-29 | 1994-08-03 | STMicroelectronics, Inc. | Verfahren zur Herstellung von einem selbstausgerichteter Transistor mit erhöhter Basis-Kontakt Leitfähigkeit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60165759A (ja) * | 1984-02-07 | 1985-08-28 | Nippon Denso Co Ltd | 集積回路素子 |
-
1995
- 1995-05-22 WO PCT/US1995/006479 patent/WO1996010844A1/en not_active Application Discontinuation
- 1995-05-22 EP EP95944784A patent/EP0783767A4/de not_active Withdrawn
- 1995-05-22 KR KR1019970702040A patent/KR970706613A/ko not_active Application Discontinuation
- 1995-05-22 AU AU25550/95A patent/AU2555095A/en not_active Abandoned
- 1995-05-22 JP JP8511714A patent/JPH10509558A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4566176A (en) * | 1984-05-23 | 1986-01-28 | U.S. Philips Corporation | Method of manufacturing transistors |
US5148252A (en) * | 1990-02-13 | 1992-09-15 | Kabushiki Kaisha Toshiba | Bipolar transistor |
EP0609052A2 (de) * | 1993-01-29 | 1994-08-03 | STMicroelectronics, Inc. | Verfahren zur Herstellung von einem selbstausgerichteter Transistor mit erhöhter Basis-Kontakt Leitfähigkeit |
Non-Patent Citations (1)
Title |
---|
See also references of WO9610844A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPH10509558A (ja) | 1998-09-14 |
AU2555095A (en) | 1996-04-26 |
EP0783767A4 (de) | 1997-12-29 |
WO1996010844A1 (en) | 1996-04-11 |
KR970706613A (ko) | 1997-11-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5512496A (en) | Method of making collector-up bipolar transistor having improved emitter injection efficiency | |
US5084750A (en) | Push-pull heterojunction bipolar transistor | |
US8697532B2 (en) | InP based heterojunction bipolar transistors with emitter-up and emitter-down profiles on a common wafer | |
EP0829906A2 (de) | Monolithisch integrierter Mikrowellen-Schaltkreis mit Sperrschicht-Transistor mit hoher Elektronenbeweglichkeit und Heteroübergang-Bipolartransistor und Herstellungsverfahren | |
Ma et al. | A high-power and high-gain X-band Si/SiGe/Si heterojunction bipolar transistor | |
US6876060B2 (en) | Complimentary bipolar transistor | |
US3817794A (en) | Method for making high-gain transistors | |
US6506659B2 (en) | High performance bipolar transistor | |
EP0197424A2 (de) | Herstellungsverfahren für einem bipolaren Transistor mit Heteroübergang | |
US6239475B1 (en) | Vertical bipolar transistor having a field shield between the metallic interconnecting layer and the insulation oxide | |
EP1021835B1 (de) | Verfahren zur herstellung eines leistungsbipolartransistors | |
US20060022306A1 (en) | Method for integration of three bipolar transistors in a semiconductor body, multilayer component, and semiconductor arrangement | |
WO1996010844A1 (en) | Bipolar transistor for use in linear amplifiers | |
US5880000A (en) | Method for fabricating an NPN transistor of minimum surface | |
US20060145299A1 (en) | Method for improving the electrical properties of active bipolar components | |
Gruhle et al. | Collector-up SiGe heterojunction bipolar transistors | |
Sawdai et al. | Power performance of InGaAs/InP single HBTs | |
KR20030028477A (ko) | 바이폴라 트랜지스터 | |
JP3022897B2 (ja) | 半導体装置 | |
KR920017278A (ko) | 저전력, 저잡음 및 고출력 회로 응용에 적합한 마이크로파 헤테로 접합 바이폴라 트랜지스터 및 이의 제조방법 | |
EP1238424B1 (de) | Verfahren zum herstellen eines bipolartransistors mit obenliegendem kollektor | |
JP3068510B2 (ja) | 半導体装置 | |
Zipperian et al. | Channel-collector transistors | |
KR20000062604A (ko) | 바이폴라 트랜지스터를 포함하는 반도체장치 | |
KR930007759B1 (ko) | 화합물 반도체소자 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19970325 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IT NL SE |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 19971105 |
|
AK | Designated contracting states |
Kind code of ref document: A4 Designated state(s): DE FR GB IT NL SE |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19991201 |