EP0759233A1 - Digital-to-digital conversion using nonuniform sample rates - Google Patents

Digital-to-digital conversion using nonuniform sample rates

Info

Publication number
EP0759233A1
EP0759233A1 EP95915415A EP95915415A EP0759233A1 EP 0759233 A1 EP0759233 A1 EP 0759233A1 EP 95915415 A EP95915415 A EP 95915415A EP 95915415 A EP95915415 A EP 95915415A EP 0759233 A1 EP0759233 A1 EP 0759233A1
Authority
EP
European Patent Office
Prior art keywords
digital
data rate
εignal
firεt
εecond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95915415A
Other languages
German (de)
English (en)
French (fr)
Inventor
James Wilson
Ronald A. Cellini
James M. Sobol
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/241,059 external-priority patent/US5497152A/en
Priority claimed from PCT/US1994/010268 external-priority patent/WO1995008220A1/en
Priority claimed from PCT/US1994/010269 external-priority patent/WO1995008221A1/en
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority claimed from PCT/US1995/003739 external-priority patent/WO1995031860A1/en
Publication of EP0759233A1 publication Critical patent/EP0759233A1/en
Withdrawn legal-status Critical Current

Links

Definitions

  • the present invention relates generally to the field of methods and circuits for digital-to-digital conversion. More particularly, the present invention relates to a method and circuit for digital-to-digital signal conversion using sigma-delta modulation of the temporal spacing between digital samples.
  • FIG. 1 is an overall functional block diagram of the AD 1890/1891. As shown in FIG.
  • the input digital data at a data rate Fsl is interpolated at some ratio by inserting zero valued samples between each of the original input signal samples by the interpolator.
  • the oversampled signal is then fed into a digital FIR low-pass filter to smooth or integrate the sequence.
  • the interpolated and filtered digital data is then passed to a zero-order hold register and then asynchronously resampled by decimating the digital data stream in the decimation block to produce the digital data out at a data rate Fs2.
  • the digital-to-digital converter were to receive digital data at two different data rates, that are not necessarily divisible into the master clock (or more generally, digital data at a rate that is not integrally divisible into the master clock) , there must be two different frequency master clocks available for clocking the digital-to-digital converter (or more generally, there must be a master clock that has an integer relationship with the data rate of the incoming digital data available to clock the digital-to-digital converter).
  • Another problem with conventional digital-to-digital converters is that they are typically not designed to be clocked by an externally supplied clock signal.
  • the components of the digital-to-digital converter are typically optimized to operate at the clock frequency determined by the master clock on the digital-to-digital converter chip.
  • the number of FIR filter taps and associated coefficients can become so large as to make the filter complicated and difficult to obtain a high throughput when the incoming digital data stream has a fast data rate.
  • an object of the present invention is to provide a method and apparatus for performing digital-to-digital conversion using NONUNIFORM sampling (i.e., variable temporal spacing of the sampling points).
  • Another object of the present invention is to provide a method and apparatus for performing digital-to-digital conversion that can lock to an externally supplied clock signal and can provide a sampling rate that is independent of the converter's master clock.
  • the apparatus includes a first interpolator or other comparable circuitry such as a sample and hold circuit for receiving digital signals at a first data rate and for supplying the digital signals at a first increased data rate and a first decimator, coupled to the first interpolator, for decimating the digital signals at the first increased data rate to provide digital signals at a second data rate.
  • a first interpolator or other comparable circuitry such as a sample and hold circuit for receiving digital signals at a first data rate and for supplying the digital signals at a first increased data rate and a first decimator, coupled to the first interpolator, for decimating the digital signals at the first increased data rate to provide digital signals at a second data rate.
  • a first sigma-delta modulator is coupled to and controls the first decimator and provides a first sigma-delta modulated output signal representative of the first data rate and controls the first decimator to provide the digital signals at the second data rate.
  • This part of the invention interpolates digital data by a fixed ratio and then decimates the interpolated digital data by a variable ratio depending on the second data rate desired.
  • a sigma-delta modulator is coupled to and controls the interpolator and provides a sigma-delta modulated output signal representative of the first data rate and controls the interpolator to provide a digital data stream at the increased data rate so that, upon decimation by the decimator, the digital signals are at the second rate.
  • This part of the invention interpolates the digital data by a variable ratio depending on the second data rate desired and then decimates the interpolated data by a fixed ratio.
  • the decimated digital data at the second data rate may then be filtered to remove, for example, sigma-delta noise introduced by the variable decimation of the digital data at the first increased data rate.
  • the digital data at the second data rate is supplied to a second interpolator or other comparable circuitry such as a sample and hold circuit that receives the digital data at the second data rate and supplies the digital signals at a second increased data rate.
  • a second decimator is coupled to the interpolator and decimates the digital signals at the second increased data rate to provide digital signals at a third data rate.
  • a second sigma-delta modulator is coupled to and controls the second interpolator and provides a second sigma-delta modulated output signal representative of the third data rate to control the second interpolator to provide the digital signals at the second increased data rate so that, upon decimation by the second decimator, the digital signals are at the third data rate.
  • This part of the invention interpolates the digital data by a variable ratio depending on the third data rate desired and then decimates the interpolated digital data by a fixed ratio.
  • a sigma-delta modulator is coupled to and controls the decimator and provides a sigma-delta modulated output signal representative of the third data rate and controls the decimator to provide the digital signals at the third data rate.
  • This part of the invention interpolates the digital data by a fixed ratio and then decimates the interpolated digital data by a variable ratio depending on the third data rate desired.
  • a first phase locked loop which may be a digital PLL or may be an analog PLL having its output coupled to the first sigma-delta modulator is provided for receiving a signal representative of the first data rate, locking to the signal, and providing a first control signal to the first sigma-delta modulator that controls the first sigma-delta modulator to provide the sigma-delta modulated output signal.
  • the first sigma-delta modulator forms part of the digitally controlled oscillator in the PLL.
  • the first phase locked loop allows the circuit to lock to and track any externally-supplied clock signal.
  • a second phase locked loop which may be a digital PLL or may be an analog PLL having its output coupled to the second sigma-delta modulator is provided for receiving a signal representative of the third data rate, locking to the signal, and providing a second control signal to the second sigma-delta modulator that controls the second sigma-delta modulator to provide the second sigma-delta modulated output signal.
  • the second sigma-delta modulator forms part of the digitally controlled oscillator in the PLL.
  • the second phase locked loop allows the circuit to lock to and track any externally-supplied clock signal.
  • the method of the present invention includes sigma-delta modulation of the time base such that errors produced by NONUNIFORM sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. That is, the present invention provides temporally noise-shaped digital signals.
  • the method is to perform a fixed interpolation (or other method of increasing the data rate or sample rate of the digital signal or digital data stream) and filtering to remove images followed by variable decimation with the decimation controlled by a first sigma-delta modulator that is fed a frequency selection signal representing the sampling frequency or data rate of the input data stream.
  • Fixed interpolation means that the interpolation ratio is the same regardless of the sample rate.
  • Variable decimation means that the decimation ratio is varied as a function of the desired output sample rate. More particularly, a digital data stream at a data rate within some predetermined limits is interpolated to a higher data rate.
  • This higher data rate digital data stream is then decimated using a control signal that is a sigma-delta modulated signal that represents the data rate of the incoming digital data stream.
  • the frequency selection signal is modulated using a first n-th order m-bit sigma-delta modulator.
  • This control signal (the sigma-delta modulated frequency selection number output by the second sigma-delta modulator) represents, on average, the data rate of the incoming digital data stream. Data thus emerges from the interpolation/decimation process at the clock rate of the first n-th order m-bit sigma-delta modulator.
  • This part of the method thus converts the data rate of the incoming digital data stream to the data rate of the first n-th order m-bit sigma-delta modulator.
  • another part of the method is to perform a variable interpolation (or other method to increase the data rate or sampling frequency of the digital signal or digital data stream) and filtering to remove images followed by a fixed decimation with the interpolation controlled by a second sigma-delta modulator that is fed a frequency selection signal representing the desired output sample rate.
  • Variable interpolation means that the interpolation ratio is varied as a function of the desired output sample rate.
  • Fixed decimation means that the decimation ratio is the same regardless of the sample rate. More particularly, the digital data stream at the data rate of the first n-th order m-bit sigma-delta modulator is interpolated to a higher data rate using a control signal that is a sigma-delta modulated signal that represents the desired output data rate (i.e., sample rate or sampling frequency).
  • the frequency selection signal is modulated using a second n-th order m-bit sigma-delta modulator.
  • This control signal (the sigma-delta modulated frequency selection signal output by the second sigma-delta modulator) represents, on average, the sample rate of the digital data to be output by the converter .
  • the control signal controls the interpolator to increase the data rate such that, upon fixed decimation, data emerges from the interpolation/decimation process at the desired output sample rate.
  • This part of the method thus converts the data rate of the digital data stream output by the variable decimation process from an oversampled signal to a digital data stream having the desired sample rate.
  • the method is to perform a variable interpolation (or other method to increase the sample rate of the digital data stream) and filtering to remove images followed by a fixed decimation with the interpolation controlled by a sigma-delta modulator that is fed a frequency selection number representing the sampling frequency of the input data stream.
  • Variable interpolation means that the interpolation ratio is varied as a function of the desired output sample rate.
  • Fixed decimation means that the decimation ratio is the same regardless of the sample rate.
  • a digital data stream at a data rate within some predetermined limits is interpolated to a higher data rate using a control signal that is a sigma-delta modulated signal that represents the data rate of the incoming digital data stream.
  • the frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator.
  • This control signal (the sigma-delta modulated frequency selection number output by the sigma-delta modulator) represents, on average, the data rate of the incoming digital data stream.
  • the control signal controls the interpolator to increase the data rate such that, upon fixed decimation, data emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator.
  • the part of the method thus convert the data rate of the incoming digital data stream to the data rate of the n-th order m-bit sigma-delta modulator.
  • Another part of the method is to perform a fixed interpolation (or other method to increase the sample rate of the digital data stream) and filtering to remove images followed by a variable decimation with the decimation controlled by a second sigma-delta modulator that is fed a frequency selection number representing the desired sample rate of the output digital data stream.
  • Fixed interpolation means that the interpolation ratio is the same regardless of the sample rate.
  • Variable decimation means that the decimation ratio is varied as a function of the desired output sample rate.
  • This higher data rate digital data stream is then decimated using a control signal that is a sigma-delta modulated ⁇ ignal that represents the desired output data rate (or sample rate) .
  • This control signal (the sigma-delta modulated frequency selection signal output by the sigma-delta modulator) represents, on average, the sample rate of the digital data to be output by the converter. Data thus emerges from the interpolation/decimation process at the desired output sample rate.
  • the part of the method thus converts the data rate of the digital data stream output by the variable interpolation process from an oversampled signal to a digital data stream having the desired sample rate.
  • FIG. 1 is a block diagram of a conventional digital-to-digital converter
  • FIG. 2 is a block diagram of a digital-to-digital converter circuit incorporating a first embodiment of the invention
  • FIG. 3 is a more detailed block diagram of the circuit of FIG. 2;
  • FIG. 4. is a block diagram of a circuit for supplying previously stored frequency numbers to the n-th order m-bit sigma-delta modulator of FIGS. 2-3, 5-5A, 9-10, 12, and 14-17;
  • FIG. 5 is a block diagram illustrating a locking circuit in the circuits of FIGS. 2-3 and 16-17;
  • FIG. 5A is a block diagram illustrating the use of a combination of a locking circuit and a sigma-delta modulator in the circuits of FIGS. 2-3 and 16-17;
  • FIG. 6 is a block diagram of a locking circuit that may be used in conjunction with the circuits of FIGS. 2-3, 5-5A, 9-10, 12, and 14-17, to lock the digital-to-digital converter to an externally supplied clock signal;
  • FIG. 7 is a block diagram of a second locking circuit that may be used in conjunction with the circuits of FIGS. 2-3, 5-5A, 9-10, 12, and 14-17, to lock the digital-to-digital converter to an externally supplied clock signal;
  • FIG. 8 is a flow chart illustrating the steps of a first embodiment of the method of the present invention.
  • FIG. 9 is a block diagram of a digital-to-digital converter circuit incorporating a second embodiment of the invention.
  • FIG. 10 is a more detailed block diagram of the circuit of FIG. 9;
  • FIG. 11 is a flow chart illustrating the steps of a second embodiment of the method of the present invention.
  • FIG. 12 is a block diagram of a digital-to-digital converter circuit incorporating a third embodiment of the invention.
  • FIG. 13 is a graph illustrating the relationship between the four-bit codes and the corresponding sampling frequency in the circuit of FIG. 12;
  • FIG. 14 is a block diagram illustrating a locking circuit in the circuits of FIGS. 9-10, 12, and 14-17;
  • FIG. 15 is a block diagram illustrating the use of a combination of a locking circuit and a sigma-delta modulator in the circuits of FIGS. 9-10, 12, and 14-17;
  • FIG. 16 is a block diagram illustrating a circuit that provides for digitally mixing signals that may have differing sample rates
  • FIG. 17 is a block diagram illustrating a circuit for providing, from a digital data stream having one data rate, digital data streams that may have differing data rates;
  • FIG. 18 is a flow chart illustrating the steps of the method of digitally mixing signals of the present invention.
  • FIG. 19 is a flow chart illustrating the step ⁇ of the method of providing multiple digital data streams from one digital data stream in accordance with the present invention.
  • FIG. 2 is a block diagram broadly illustrating a first embodiment of the invention.
  • the overall purpose of circuit 10 is to receive a digital data stream on line 12 at any data rate within a predetermined working range of the system and to convert the digital data to a digital data stream on line 42.
  • the data rate of the digital data stream on line 42 can be the same as, higher, or lower than the data rate of the digital data stream on line 12.
  • Circuit 10 performs this function by increasing the sample rate (Fsl) of the digital data stream on line 12 to create a first so-called “oversampled” signal and then decimates this higher rate data stream so that the data stream presented on line 14 is at a fixed, predetermined data rate.
  • circuit part 13 of circuit 10 receives digital data at any data rate within the predetermined working range of the system, and converts this data to a digital data ⁇ tream on line 14 at another data rate.
  • the data rate on line 14 may or may not be the same as the data rate of the input data stream and may be a fixed or a variable rate.
  • the digital data stream on line 12 may be of any width (i.e., any number of bits).
  • circuit 10 increases the sample rate of the digital data on line 14 to create a second so-called “oversampled” signal and then decimates this higher rate digital data stream so that the data presented on line 42 is at a desired output sampling rate.
  • circuit part 15 of circuit 10 receives digital data at the fixed, predetermined data rate and converts this data to a digital data stream at another data rate.
  • an interpolator 16 receives the digital data ⁇ tream on line 12 at any data rate (F ⁇ l) within the predetermined working range.
  • Interpolator 16 increases the sample rate of the digital data ⁇ tream (that i ⁇ , converts the digital data stream into a higher sample rate digital data ⁇ tream) on line 12 by, for example, in ⁇ erting zero ⁇ between data samples, in a manner well-known to those skilled in the art.
  • sample rate of the digital data ⁇ tream that i ⁇ , converts the digital data stream into a higher sample rate digital data ⁇ tream
  • Other techniques may be used for increasing the sample rate of the data stream on line 12, such a ⁇ sample and hold technique ⁇ .
  • a higher sample rate digital data stream 17 is then sent to a digital filter 18 which attenuates any images of the original digital signal as a result of the interpolation proces ⁇ .
  • the filtered digital data stream on line 19 is then sent to a decimation block 21 that decimates digital data stream on line 19 under control of the sigma-delta modulator 20.
  • filter 18 and decimation block 21 have been r illustrated as separate circuit elements for illustrative purposes, one skilled in the art will appreciate that these functions may be performed by a single computational element, ⁇ uch a ⁇ an FIR or IIR filter in a well-known manner.
  • the sigma-delta modulator 20 produces digital data at the frequency of clock 22, the data controlling the decimation of decimation block 21.
  • the ⁇ igma-delta modulator 20 ⁇ igma-delta modulate ⁇ a ⁇ ignal 24 representative of the data rate (Fsl) of the digital data ⁇ tream on line 12.
  • Fsl data rate of the digital data ⁇ tream on line 12.
  • An example will ⁇ erve to illu ⁇ trate this function. As ⁇ ume that the data rate of the data stream on line 12 is 48 kHz.
  • Interpolator 16 increases this data rate to 18.432 mHz by interpolating the data by a factor of 384. Assume the frequency of clock 22 is 3.072 mHz.
  • signal 24 is therefore a multi-bit digital number representative of a ⁇ ampling rate of 48 kHz where the number of bit ⁇ in the digital number control the preci ⁇ ion with which the data rate of digital data stream on line 12 can be specified.
  • This digital number is sigma-delta modulated by the sigma-delta modulator 20 and u ⁇ ed to control decimation block 21 to produce one output ⁇ ignal for every ⁇ ix samples in digital data stream 19.
  • the 18.432 mHz data i ⁇ then effectively decimated by a factor of ⁇ ix and the digital data stream on line 14 is therefore at, on average, a 3.072 mHz data rate.
  • Sigma delta modulator 20 is preferably an n-th order m-bit sigma-delta modulator.
  • Sigma-delta modulator 20 could also be a one bit modulator if the clock frequency used to run the modulator is increased a ⁇ nece ⁇ ary.
  • a key feature of the present invention as a whole and in particular circuit part 13 is that the temporal spacing of the sampling points is controlled by the n-th order m-bit sigma-delta modulator such that any errors (i.e., noise on the sampling points) produced by this NONUNIFORM sampling are shaped in the frequency domain. That is, the digital signal output by the present invention as well as the control signal produced by the ⁇ igma-delta modulator are temporally noise-shaped. All embodiment ⁇ of the invention provide thi ⁇ feature. As is well-known in the field of sigma-delta ⁇ ystems, this noise on the digital ⁇ ignal produced by circuit part 15 produced by errors resulting from the NONUNIFORM ⁇ ampling can be removed by conventional digital filtering technique ⁇ .
  • the signal to noise ratio of the digital data stream on line 14 can be controlled. Further degrees of freedom are available by varying the order of the sigma-delta modulator used to control the oversampling ratio. In another aspect of the invention, the degree of filtering used on the digital data stream on line 17 can also be varied to vary the signal-to-noi ⁇ e ratio a ⁇ well.
  • Filter 11 removes any sigma-delta noise on the digital data stream on line 14 as a result of the sigma-delta modulator's control of decimation block 21.
  • Filter 11 may be a sine-type
  • the filtered digital data ⁇ tream on line 28 is then sent to interpolator 30.
  • Interpolator 30 increase ⁇ the ⁇ ample rate of the digital data ⁇ tream (that i ⁇ , converts the digital data stream into a higher sample rate digital data ⁇ tream) on line 28 by u ⁇ ing a ⁇ ample and hold technique that repeat ⁇ the digital ⁇ ample for a specified number of clock cycles in a manner well-known to those skilled in the art.
  • technique ⁇ may be used for increasing the sample rate of the data stream on line 28, such as interpolation techniques that insert zeroes between data samples.
  • the purpose of interpolator 30 is to increase the sample rate of the digital data stream on line 28 to create an oversampled signal.
  • the interpolation ratio (i.e., the ratio by which the sample rate of the digital data on line 28 is increased by interpolator 30) is controlled by a sigma-delta modulator 32.
  • Sigma-delta modulator 32 may be the same type of modulator as sigma-delta modulator 20.
  • a higher sample rate digital data stream on line 34 is then sent to a digital filter 36 which removes any image ⁇ of the original digital ⁇ ignal a ⁇ a re ⁇ ult of the interpolation proce ⁇ .
  • the filtered digital data stream on line 38 i ⁇ then ⁇ ent to a decimation block 40 that decimates the digital data stream on line 38 by a fixed decimation ratio to produce the digital data stream on line 42 having a sample rate (F ⁇ 2) ⁇ elected by a sampling frequency ⁇ elect signal 44.
  • filter 36 and decimation block 40 have been illu ⁇ trated as separate circuit elements for illustrative purpose ⁇ , one ⁇ killed in the art will appreciate that these functions may be performed by a single computational element, such a ⁇ an FIR or IIR filter in a well known manner.
  • the sigma-delta modulator 32 produces digital data at the frequency of clock 22, the data controlling the interpolation of interpolator 30.
  • the sigma-delta modulator 32 sigma-delta modulates a signal 44 representative of the desired output sample rate (Fs2) of the digital data stream on line 42.
  • Fs2 desired output sample rate
  • An example will serve to illustrate this f nction. A ⁇ sume that the data rate of the digital data stream on line 28 is 3.072 mHz. Assume the frequency of clock 22 is 3.072 mHz.
  • signal 44 is therefore a multi-bit digital number representative of a sampling rate of 32 kHz where the number of bits in the digital number control the precision with which the data rate (Fs2) of the data ⁇ tream on line 42 can be ⁇ pecified.
  • This digital number is sigma-delta modulated by the ⁇ igma-delta modulator 32 and u ⁇ ed to control interpolator 30 to increase the sample rate of the digital data stream on line 28 by a factor of four.
  • Interpolator 28 increases this data rate to 12.288 mHz by interpolating the data by a factor of four.
  • the resulting 12.288 mHz data is then decimated, after filtering by filter 36, by a factor of 384 (decimator 40 having a decimation ratio of 384) and the digital data stream emerging on line 42 is therefore at, on average, a 32 kHz data rate.
  • Sigma-delta modulator 32 i ⁇ preferably an n-th order m-bit ⁇ igma-delta modulator.
  • the signal on line 46 output by sigma-delta modulator 32 is chosen to be m-bits (where m 1 n an ⁇ 3 is more than one bit in a preferred embodiment) because, a ⁇ the number of bit ⁇ which control interpolator 30 is increased, the clock rate neces ⁇ ary to operate ⁇ igma-delta modulator 32 can be reduced.
  • Sigma-delta modulator 32 could al ⁇ o be a one bit modulator if the clock frequency used to run the modulator is increased as nece ⁇ sary.
  • a key feature of the present invention is as a whole (a ⁇ di ⁇ cussed previously) and circuit part 15 in particular that the temporal spacing of the sampling points is controlled by the n-th order m-bit sigma-delta modulator such that any errors (i.e., noise on the sampling points) produced by this NONUNIFORM sampling are shaped in the frequency domain. That is, the digital signal output by the present invention as well as the control signal produced by the sigma-delta modulator are temporally noise- ⁇ haped. All embodiments of the invention provide this feature. As is well-known in the field of sigma-delta systems, this noise on the digital signal produced by circuit part 15 produced by errors re ⁇ ulting from the NONUNIFORM ⁇ ampling can be removed by conventional digital filtering technique ⁇ .
  • the signal-to-noi ⁇ e ratio of the digital data stream on line 42 can be controlled. Further degrees of freedom are available by varying the order of the sigma-delta modulator used to control the oversampling ratio. In another aspect of the invention, the degree of filtering used on the digital data stream on line 34 can also be varied to vary the ⁇ ignal-to-noise ratio as well.
  • FIG. 3 illustrates a more detailed embodiment of the digital-to-digital converter of FIG. 2.
  • circuit part 51 is analogou ⁇ to circuit part 13 in FIG. 2 and circuit part 90 i ⁇ analogou ⁇ to circuit part 15 in FIG. 2.
  • an n-bit wide digital data ⁇ tream on line 50 which may be, for example, in the range of 4 kHz to 48 kHz is received by interpolator 52.
  • Interpolator 52 increases the sample rate (Fsl) of digital data ⁇ tream on line 50 by a factor of four u ⁇ ing, for example, a zero fill technique that in ⁇ erts zeros between the digital samples.
  • the higher sample rate signal output by interpolator 52 (now in the range of 16 kHz to 192 kHz) i ⁇ then fed into a digital low pa ⁇ filter 54 which may be, for example, a finite impulse response type filter.
  • Low pas ⁇ filter 54 filters out of band images of the digital ⁇ ignal on line 50 out of the digital data stream on line 53.
  • the filtered digital data stream on line 56 from low pas ⁇ filter 54 is then fed into interpolator 58 that increases the sample rate of the digital data stream on line 56 by a factor of ninety-six. Inserting ninety-five zeros into the digital data stream on line 56 will reduce the gain of the original signals because of the dilution of the signal by the inserted zeros.
  • filter 62 can be adjusted to compensate for this los ⁇ of gain.
  • the higher ⁇ ample rate digital data ⁇ ignal on line 60 (now in the range of 1.536 mHz to 18.432 mHz) provided by interpolator 58 i ⁇ fed into digital filter 62.
  • sample and hold techniques may be used to increase the ⁇ ample rate in place of interpolator ⁇ 52, 58.
  • sample and hold techniques may be used to increase the ⁇ ample rate in place of interpolator ⁇ 52, 58.
  • the use of a sample and hold technique is advantageous because it automatically compensates for the energy lost in creating the images of the original signal due to the interpolation proces ⁇ .
  • digital filter 62 i ⁇ a ⁇ inc 96"-type filter that i ⁇ designed to have zeros at the image frequencies of the digital data stream on line 60.
  • Filter 62 could, however, be any type of IIR or FIR filter.
  • digital filter 62 provides both a low pass filtering function and a decimation function.
  • filter 62 outputs a digital data stream on line 64 at 3.072 mHz.
  • the digital data streams on lines 53, 56, 60, and 64 are indicated as being n-bits wide in FIG. 3.
  • N may be any number of bits and is typically chosen to be the widest bit stream commensurate with the signal-to-noi ⁇ e ratio requirement ⁇ of the particular application.
  • the digital data streams may be different widths on each of the lines.
  • the n-th order m-bit ⁇ igma-delta modulator 66 provides a four-bit number on line 68 that control ⁇ filter 62 to produce the output data ⁇ tream on line 64.
  • Sigma-delta modulator 66 i ⁇ in one embodiment, a third order four-bit modulator.
  • Sigma delta modulator 66 i ⁇ clocked using a 3.072 mHz clock 70.
  • a twenty-bit frequency selection number 72 (representing Fsl) i ⁇ input into ⁇ igma-delta modulator 66N Frequency selection number 72 ranges from -2 to +2 9 .
  • Thi ⁇ twenty-bit number controls the precision with which the four-bit number output by sigma-delta modulator 66 represent ⁇ the ⁇ ampling rate (Fsl) of the input digital data stream on line 50.
  • Sigma-delta modulator 66 modulates the twenty-bit number to produce sigma-delta modulated four-bit codes that control filter 62.
  • the first bit of the code is a sign bit.
  • the remaining three bits produce codes that direct the filter 62 to calculate and produce an output every P samples of the data stream on line 60, effectively sample rate converting the data stream.
  • Table 1 illustrate ⁇ the relationship among the four-bit codes that are produced by sigma-delta modulator 66, the intervals at which filter 62 produces an output, and the sampling frequency that the four-bit code correspond ⁇ to when modulator 66 is clocked using a 3.072 mHz clock. Some example ⁇ will illu ⁇ trate the operation of thi ⁇ part of the ⁇ ystem.
  • the digital data stream on line 50 has a data rate (Fsl) of 48 kHz.
  • Interpolator 52 increases this data rate to 192 kHz.
  • Interpolator 58 increa ⁇ es the 192 kHz ⁇ ampling rate to 18.432 mHz.
  • the digital data stream on line 60 at 18.432 mHz must be decimated by a factor of six.
  • twenty-bit frequency ⁇ election number 72 is selected such that upon sigma-delta modulation by the third order four-bit sigma-delta modulator 66, the four bit codes generated will be, on average, a +2 code although other four bit codes will be produced but with a lower frequency of occurrence.
  • the +2 code is the resulting average of all the codes produced by sigma-delta modulator 66 upon sigma-delta modulation of twenty-bit frequency selection number 72.
  • a +2 code is not produced every time sigma-delta modulator 66 is clocked even though the input sample rate (Fsl) and the output sample rate of the data stream on line 64 are related to each other by an integer multiple.
  • the time base i.e., the temporal spacing between samples
  • the time base is sigma-delta modulated so that the errors due to temporal displacement between the input and rate-converted digital data stream that cause noise are pushed into a higher frequency range. This noise is then removed by conventional filtering techniques ⁇ uch a ⁇ in filter 74.
  • the +2 (on average) code direct ⁇ filter 62 to produce an output every ⁇ ix data ⁇ amples of digital data stream on line 60. This results in the output data stream on line 64 having a data rate (i.e., a ⁇ ample rate or ⁇ ampling frequency) of 3.072 mHz on average.
  • a ⁇ ume that the digital data ⁇ tream on line 50 has a data rate (i.e., a sample rate or sampling frequency) (Fsl) of 4 kHz.
  • Interpolator 52 increases this data rate to 16 kHz.
  • Interpolator 58 increases the 16 kHz data rate to 1.536 mHz.
  • the digital data stream on line 64 have a data rate of 3.072 mHz (i.e., the clock rate of the clock controlling sigma-delta modulator 66)
  • the digital data stream on line 60 at 1.536 mHz must be effectively interpolated by a factor of 2.
  • twenty-bit frequency selection number 72 (representing Fsl) is chosen such that ⁇ igma-delta modulator 66 produces, on average, an equal number of -3 and -4 codes although other four bit codes will be produced, but with a lower frequency of occurrence. That is, occasionally, -2, -1, and even less frequently, +1, +2 codes will be produced.
  • the -3 code direct ⁇ ⁇ inc filter 62 to produce an output for each input ⁇ ample corresponding to a sampling frequency of 8 kHz for the clock frequencies and interpolation ratios illustrated.
  • the -4 code is u ⁇ ed to control filter 62 ⁇ o that it doe ⁇ not produce a new output but rather repeat ⁇ the previous output. That is, the filter 62 is directed to produce an output, but since a new data point has not been received and the previou ⁇ data point i ⁇ ⁇ till at the filter input, the filter 62 repeat ⁇ the calculation and produce ⁇ the same output again.
  • the -3 code repre ⁇ ents a sampling frequency of 8 kHz and the -4 code represent ⁇ a sampling frequency of DC (i.e., no signal). Therefore, on an average of many sample ⁇ , the -3 and -4 four-bit codes produce a ⁇ ampling frequency of 4 kHz to provide a digital data stream on line 64 at 3.072 mHz.
  • any sampling frequencie ⁇ within the 0 to 64 kHz range may be produced by varying the ratio of four-bit codes produced by sigma-delta modulator 66.
  • the appropriate ratio of +3 and +4 code ⁇ would be output by ⁇ igma-delta modulator 66 a ⁇ a function of twenty-bit number 72.
  • any ⁇ ample rate within the working range of the ⁇ y ⁇ tem can be produced through the appropriate combination of four-bit code ⁇ .
  • modulator 66 ha ⁇ been illustrated as a four-bit ⁇ igma-delta modulator, the invention is not so limited.
  • a ⁇ igma-delta modulator that output ⁇ fewer bit ⁇ can be u ⁇ ed if the clock rate of the clock ⁇ upplied to the modulator i ⁇ increa ⁇ ed as necessary.
  • a sigma-delta modulator that outputs a larger number of bits can be used and the modulator can then be clocked at a lower rate.
  • the number of bits used and the clock rate used are a function of the desired noise shaping and signal to noise ratio, and may be traded-off depending upon the requirements of a particular application.
  • FIG. 4 is a block diagram of an alternative sy ⁇ tem for determining frequency ⁇ election number 72.
  • a memory 80 (which may be RAM or ROM, for example) i ⁇ used to store a look up table containing twenty-bit numbers and the sampling frequency to which they corre ⁇ pond.
  • decoder 82 selects the twenty-bit number from memory 80 most closely corre ⁇ ponding to the desired sampling frequency specified by the frequency ⁇ elect signal.
  • the twenty-bit number is then output on bus 84 to sigma-delta modulator 66.
  • the system of FIG. 4 can be used in conjunction with all embodiments of the invention.
  • filter 74 which operates in a manner analogous to filter 11 in FIG. 2. That is, depending on the performance requirement ⁇ of the particular application, filter 74 may be u ⁇ ed to filter out sigma-delta noise on the digital data stream on line 64 as a re ⁇ ult of ⁇ igma-delta modulation control of ⁇ inc filter 62. In one embodiment of the invention, filter 74 may be a ⁇ inc-type filter, such a ⁇ a
  • the filtered digital data stream on line 86 is then ⁇ ent to interpolator 92.
  • Interpolator 92 increa ⁇ e ⁇ the ⁇ ample rate of the digital data stream on line 86 by using a sample and hold technique or an interpolation technique under control of sigma-delta modulator 94.
  • the use of a sample and hold technique is advantageous because it automatically compen ⁇ ates for the energy lost in creating the images of the original signal due to the interpolation process.
  • ⁇ uch a ⁇ interpolation technique ⁇ that in ⁇ ert zeroe ⁇ between data samples may be used to increase the sample rate of the data stream on line 86.
  • the higher rate digital data stream on line 96 is then sent to low-pas ⁇ filter 98 that remove ⁇ i ages and sigma-delta noise from the digital data stream on line 96 that may be present as a result of the interpolation process.
  • digital filter 98 is a sine 96 3 -type filter.
  • Filter 52 could, however, be any type of IIR or FIR filter.
  • the filtered digital data stream on line 102 i ⁇ then sent to a decimation block 104 that decimates the digital data ⁇ tream on line 102 by a fixed decimation ratio (96 in the illustrated embodiment).
  • the decimated digital data ⁇ tream on line 106 i ⁇ then filtered by low pa ⁇ s filter 108 to remove images and ⁇ igma-delta noi ⁇ e as a result of the NONUNIFORM sampling.
  • the digital data streams on lines 86, 96, 102, 106, and 110 are indicated as being n-bits wide in FIG. 3.
  • N may be any number of bits and is typically chosen to be the widest bit stream commensurate with the signal-to-noise ratio requirements of the particular application
  • the digital data streams may be different width ⁇ on each of the lines.
  • the n-th order m-bit sigma-delta modulator 94 provides a four-bit number on line 117 that controls interpolator 92 to produce the digital data ⁇ tream on line 96.
  • sigma-delta modulator 94 i ⁇ a third order four-bit modulator.
  • Sigma-delta modulator 94 i ⁇ al ⁇ o clocked using the 3.072 mHz clock 70.
  • a twenty-bit frequency selection number 116 (representing Fs2) is input into ⁇ igma-delta modulator 94N Frequency selection number 116 ranges from -2 19 to +2 19 . This twenty-bit number controls the precision with which the four-bit number output by sigma-delta modulator 94 represents the desired sampling rate
  • RECTIFIED SHEET (RULE 91) ISA/EP (F ⁇ 2) of the output digital data stream on line 114.
  • Sigma delta modulator 94 modulates the twenty-bit number to produce sigma-delta modulated four-bit codes that control interpolator 92.
  • the first bit of the code i ⁇ a ⁇ ign bit.
  • the remaining three bits produce codes that control the interpolation ratio (i.e., the factor by which the sample rate of the digital data stream on line 86 is increased) provided by interpolator 92 to effectively convert the sample rate of the data stream.
  • Table 2 illustrates the relationship among the four-bit codes that are produced by sigma-delta modulator 94, the ratio by which the sample rate of the digital data stream on line 86 is increased, and the sampling frequency that the four-bit code corresponds to when modulator 94 is clocked using a 3.072 mHz clock. Some examples will illustrate the operation of this part of the sy ⁇ tem.
  • the sample rate of the digital data stream on line 86 is an oversampled data stream having a constant sample rate of 3.072 mHz as a result of the interpolation/decimation proces ⁇ performed by circuit part 51 on the digital data ⁇ tream on line 50.
  • the de ⁇ ired sample rate (Fs2) of the digital data stream on line 114 i ⁇ 32 kHz.
  • the digital data stream on line 110 mu ⁇ t have a sample rate of 128 kHz and the digital data stream on line 96 must have a sample rate of 12.288 mHz.
  • twenty-bit frequency selection number 116 is selected such that upon ⁇ igma-delta modulation by the third order four-bit ⁇ igma-delta modulator 94, the four-bit codes generated will be, on average, a 0 code, although other four-bit codes will be produced but with a lower frequency of occurrence.
  • Interpolator 92 use ⁇ , in one embodiment, a ⁇ ample and hold technique under control of ⁇ igma-delta modulator 94 to increa ⁇ e the ⁇ ample rate of the digital data stream on line 86.
  • the use of a sample and hold technique is advantageous because it automatically compen ⁇ ate ⁇ for the energy lost in creating the images of the original ⁇ ignal due to the interpolation proce ⁇ .
  • the time ba ⁇ e i.e., the temporal spacing between samples
  • the time ba ⁇ e is sigma-delta modulated so that the error ⁇ due to temporal di ⁇ placement between the digital data ⁇ tream on line 86 and the rate-converted digital data ⁇ tream on line 96 that cause noise are pushed into a higher frequency range.
  • This noi ⁇ e i ⁇ then removed by conventional filtering technique ⁇ such as in digital filters 98 and 108.
  • the 0 code (on average) direct ⁇ interpolator 92 to increa ⁇ e the sample rate of the digital data stream on line 86 by a factor of four.
  • Interpolator 92 use ⁇ , in one embodiment, a ⁇ ample and hold technique under control of sigma-delta modulator 94 to increase the ⁇ ample rate of the digital data ⁇ tream on line 86.
  • the u ⁇ e of a ⁇ ample and hold technique i ⁇ advantageous because it automatically compensates for the energy lost in creating the images of the original signal due to the interpolation process.
  • interpolator 92 may increase the sample rate by interpolation using a zero fill technique to insert four zeros between every sample of the digital data stream on line 86.
  • the desired sample rate of the digital data stream on line 114 is 4 kHz.
  • the digital data ⁇ tream on line 110 mu ⁇ t have a ⁇ ample rate of 16 kHz and the digital data ⁇ tream on line 96 mu ⁇ t have a ⁇ ample rate of 1.536 mHz. Therefore, 20-bit frequency selection number 116 is selected ⁇ uch that sigma-delta modulator 94 produce ⁇ , on average, an equal number of -3 and -4 code ⁇ , although other 4-bit code ⁇ will be produced, but with a lower frequency of occurrence.
  • the -3 code directs interpolator ⁇ 92 not to increa ⁇ e the ⁇ ample rate (becau ⁇ e the sample rate increa ⁇ e factor is 1). This correspond ⁇ to a ⁇ ampling frequency of 8 kHz for the clock frequencie ⁇ and interpolation ratios illustrated.
  • the -4 code control ⁇ interpolator 92 to increa ⁇ e the sample rate of the digital data stream by a factor of zero. That is, interpolator 92, in respon ⁇ e to a -4 code, produce ⁇ no output, thus effectively decimating the digital data stream on line 86.
  • the -3 code represents a sampling frequency of 8 kHz and the -4 code repre ⁇ ent ⁇ a sampling frequency of DC (i.e., no signal). Therefore, on average of many samples, the -3 and -4 4-bit codes represent a sampling frequency of 4 kHz. Thu ⁇ , on average of many sample ⁇ , after decimation by decimator 104 and decimator 112, the data rate of the digital data on line 114 will be, on average, 4 kHz.
  • any ⁇ ampling frequencie ⁇ within the 0 to 64 kHz range may be produced by varying the ratio of four-bit codes produced by sigma-delta modulator 94.
  • the appropriate ratio of +3 and +4 code ⁇ would be output by ⁇ igma-delta modulator 94 a ⁇ a function of twenty-bit number 116.
  • any sample rate within the working range of the sy ⁇ tem can be produced through the appropriate combination of four-bit codes.
  • a four-bit sigma-delta modulator ha ⁇ been illu ⁇ trated, the invention is not so limited.
  • a sigma-delta modulator that outputs fewer bits can be u ⁇ ed if the modulator i ⁇ clocked at a fa ⁇ ter rate.
  • a sigma-delta modulator that outputs a larger number of bits can be u ⁇ ed and the modulator can then be clocked at a lower rate.
  • the number of bit ⁇ u ⁇ ed and the clock rate used are a function of the desired noise ⁇ haping and ⁇ ignal-to-noise ratio and may be traded off depending upon the requirements of a particular application.
  • one of the advantages of sigma-delta modulation of the time base in circuit part 90 is that the jitter or time variation produced on the sampling time (or sampling interval) due to the fact that interpolator 92 (under control of sigma-delta modulator 94) produces output sample ⁇ at time interval ⁇ that may not correspond exactly to the specified output sampling frequency (0 kHz to 64 kHz in the illustrated embodiment) on line 117 is varied by the sigma-delta modulator so that any noise that result ⁇ from the error or jitter around the sampling point has a ⁇ igma-delta characteristic that can be removed by conventional filtering techniques, as for example, by filter 98.
  • the alternative system for determining a frequency selection number as illustrated in FIG. 4 can also be used to determine 20 bit frequency selection number 116 in the same manner.
  • FIG. 5 illustrates another embodiment of the invention in which digital phase locked loops 120 and 122 are incorporated into the circuits of FIGS. 2 or 3.
  • the phase locked loops allow the digital-to-digital converter to operate at and lock to external clock signals, such as off-chip signal ⁇ .
  • Pha ⁇ e locked loop 120 locks to and tracks an external frequency ⁇ ource on line 124.
  • the frequency source on line 124 may be the sampling frequency select signal or the twenty bit frequency selection number illustrated in FIGS. 2 and 3, re ⁇ pectively.
  • the frequency ⁇ ource on line 124 may be a clock running at the data rate (Fsl) of the digital data coming into the circuit on line 126.
  • the frequency source on line 124 may be a clock from the circuit that supplie ⁇ the digital data on line 126 at a data rate of Fsl. Therefore, phase locked loop 120 will track changes in the clock that controls the data rate of the digital data on line 126, thus allowing this part of the circuit to respond to an external frequency source.
  • the first part of circuit 150 including interpolator 128, filter 130, and decimator 132 can be made to track the clock that controls the data rate of the digital data on line i26, thu ⁇ allowing this part of the circuit to
  • phase locked loop 122 responds to an external frequency source on line 136 to control interpolator 138, filter 140, and decimator 142.
  • the frequency ⁇ ource :>n line 136 may be the ⁇ ampling frequency ⁇ elect signal or the twenty bit frequency selection number illustrated in FIG. 2 and 3, re ⁇ pectively.
  • the external frequency ⁇ ource on line 136 i ⁇ typically a clock running at the desired output data rate (F ⁇ 2) of the digital data on line 144.
  • F ⁇ 2 desired output data rate
  • the data rate of the digital data on line 144 can be made to be independent of the clock rate of clock 134, ⁇ ince the phase locked loop 122 locks to and tracks the frequency of the external frequency ⁇ ource on line 136.
  • FIG. 5A illu ⁇ trate ⁇ another embodiment of the invention in which phase locked loop 120 receives, on line 124, an external frequency source having a frequency equal to the clock rate of the digital data stream being supplied to interpolator 128. Since phase locked loop 120 responds to a clock having the data rate of the incoming digital data stream, any changes in the frequency of the digital data on line 126 are tracked by phase locked loop 120, thereby keeping the operation of interpolator 128, filter 130, and decimator 132 in ⁇ ynchroni ⁇ m with the data rate of the incoming digital data on line 126.
  • the circuit of FIG. 5A al ⁇ o include ⁇ the ⁇ igma-delta modulator and variable interpolation/fixed decimation circuitry 90 illu ⁇ trated in FIG. 3.
  • FIG. 5A Thi ⁇ portion of the circuitry of FIG. 5A operate ⁇ in the manner described in conjunction with FIG. 3.
  • the circuit of FIG. 5A is advantageou ⁇ in that the fixed interpolation, variable decimation portion can be locked to the data rate of the incoming digital data ⁇ tream.
  • the data rate of the outgoing digital data ⁇ tream on line 114 i ⁇ controlled by the 20 bit frequency ⁇ election number 116. Thu ⁇ , both portion ⁇ 146 and 90 can re ⁇ pectively receive data and output data independent of the clock rate of clock 134.
  • the data rate of the digital data on line 114 can be independent of and unrelated to the data rate of the digital data on line 126.
  • FIGS. 5 and 5A are exemplary and that phase locked loops and ⁇ igma-delta modulator ⁇ can be combined in other way ⁇ in accordance with the pre ⁇ ent invention.
  • FIG. 6 illu ⁇ trate ⁇ a detailed embodiment of pha ⁇ e locked loop 120 of FIG. 5.
  • Digital pha ⁇ e locked loop 120 incorporate ⁇ a sigma-delta modulator such as ⁇ igma-delta modulator 20 or 66.
  • an external clock source on line 124 is applied to a frequency counter 164 that produces a signal representative of the period of the external frequency source on line 124.
  • the external clock on line 124 is applied to a phase detector 166 that produces a signal proportional to the pha ⁇ e difference between the external clock on line 124 and a signal on line 168 to be described in more detail hereinafter.
  • the output of the pha ⁇ e detector 166 i ⁇ filtered by differentiating filter 170 and ⁇ ummed in summer 172 with the ⁇ ignal repre ⁇ entative of the period of the external clock ⁇ ource on line 124 from the frequency counter 164.
  • the output of summer 172 is fed into an integrating filter 174 that functions as a low-pas ⁇ filter.
  • the output of integrating filter 174 i ⁇ then sent to a circuit 176 that converts the period to a frequency by performing a 1/period function and providing any application dependent scaling of the frequency signal.
  • the signal from circuit 176 is then sent to sigma-delta modulator 66.
  • the four-bit code from sigma-delta modulator 66 is u ⁇ ed to control decimator 132 or decimate block 21 or ⁇ inc filter 62 in the ⁇ ame manner a ⁇ de ⁇ cribed in connection with the embodiment of FIGS. 2 and 3, respectively.
  • the four-bit code is also fed into a clock generation circuit 178 that effectively produces an output clock at 384 times greater than the ⁇ ignal on line 124.
  • Circuit 178 performs this function by suppressing a certain number of 24.576 mHz clock cycle ⁇ in response to the four-bit code from sigma-delta modulator 66.
  • the following examples will serve to illustrate. Assume sigma-delta modulator 66 is clocked by a 3.073 mHz clock. For every 3.072 mHz clock, there are eight 24.576 mHz clocks applied to circuit 178.
  • circuit 178 suppresses a number of 24.576 mHz clocks a ⁇ a function of the four bit code output by sigma-delta modulator 66. For example, if the external frequency source on line 162 is 48 kHz, then sigma-delta modulator 66 output ⁇ , on average, a +2 code. The +2 code directs circuit 178 to allow six out of every eight 24.576 mHz clock ⁇ to pa ⁇ through. Stated another way, circuit 178 ⁇ uppre ⁇ e ⁇ two out of every eight 24.576 mHz clocks in respon ⁇ e to a +2 code.
  • sigma-delta modulator 66 output ⁇ , on average, an equal number of -3 and -4 codes.
  • the -3 code directs circuit 178 to allow one out of every eight 24.576 mHz clocks to pass through (i.e., circuit 178 suppre ⁇ e ⁇ ⁇ even out of every eight 24.576 mHz clock ⁇ in re ⁇ ponse to a -3 code) .
  • the -4 code direct ⁇ circuit 178 to allow no 24.576 mHz clock ⁇ to pa ⁇ through (i.e., circuit 178 suppre ⁇ ses eight out of every eight 24.576 mHz clock ⁇ in re ⁇ pon ⁇ e to a -4 code) . On average, therefore, one out of every ⁇ ixteen 24.576 mHz clock ⁇ will pa ⁇ s through suppre ⁇ or circuit 178 in re ⁇ pon ⁇ e to an average of -3 and -4 code ⁇ .
  • circuit 178 also performs the additional function of randomly suppre ⁇ ing clock cycles in order to prevent unwanted tones in the output data stream on line 182. Randomizing en ⁇ ures that pulse ⁇ in each of the eight po ⁇ itions (recall that there are eight 24.576 mHz clock pulse ⁇ for each 3.072 mHz clock pulse controlling ⁇ igma-delta modulator 66) are ⁇ uppressed equally, on average. Thi ⁇ may be accomplished by providing a latch for each bit position that i ⁇ set whenever the pulse in that position is ⁇ uppressed.
  • Pul ⁇ e ⁇ in that po ⁇ ition are not ⁇ uppre ⁇ sed again until all latches corre ⁇ ponding to all the po ⁇ ition ⁇ have been ⁇ et, at which time the latches are cleared and the sequence of suppre ⁇ ion i ⁇ repeated.
  • Thi ⁇ reduces tones that result from the clock pulse suppre ⁇ or.
  • Clock ⁇ uppressor circuits are well-known in the art. One example of ⁇ uch a circuit may be found in Pha ⁇ e Locked Loop ⁇ , Theory, De ⁇ ign, and Application ⁇ by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E. Be ⁇ t, published by Dr. Roland E
  • Clock randomizer/suppre ⁇ or circuit 178 output ⁇ a clock signal on line 182 that is ⁇ ent through divider 184 having a divider ratio of 96 and a divider 188 having a divider ratio of 4 that reduce the suppres ⁇ ed and randomized 24.576 mHz clock output by clock randomizer circuit 178 to the frequency of the external clock on line 124.
  • Circuit ⁇ 184 and 188 may be counter ⁇ .
  • the ⁇ ignal on line 182 is approximately 18.432 mHz. When divided by ninety-six and then four, the ⁇ ignal on line 168 i ⁇ 48 kHz. If the external clock on line 124 is 4 kHz, then the signal on line 182 is approximately 1.536 mHz. When divided by ninety-six and then four, the ⁇ ignal on line 168 i ⁇ 4 kHz.
  • Circuit 176 sigma-delta modulator 66 and clock randomizer/suppre ⁇ sor circuit 178 together form a digitally-controlled oscillator.
  • FIG. 7 illustrates one embodiment of the phase locked loop 122 used in the circuit of FIG. 5.
  • Phase locked loop 122 is the same as phase locked loop 120.
  • an external clock source on line 136 is applied to a frequency counter 164 that produces a ⁇ ignal representative of the period of external frequency source on line 136.
  • the external clock on line 136 is applied to phase detector 166 that produce ⁇ a ⁇ ignal proportional to the pha ⁇ e difference between the external clock on line 136 and a ⁇ ignal on line 166 to be de ⁇ cribed in more detail hereinafter.
  • the output of phase detector 166 i ⁇ filtered by differentiating filter 170 and summed in summer 172 with the signal representative of the period of the external clock source on line 136 from the frequency counter 164.
  • the output of summer 172 is fed into an integrating filter 174 that functions as a low-pa ⁇ s filter.
  • the four-bit code from ⁇ igma-delta modulator 94 is used to control interpolator 138 or interpolators 30 or 92 in the ⁇ ame manner a ⁇ described in connection with the embodiment of FIGS. 2 and 3, respectively.
  • the 4-bit code i ⁇ also fed into a clock generation circuit 179 that effectively produces an output clock at 384 times greater than the signal on line 136.
  • Circuit 179 performs this function by suppressing a certain number of 24.576 mHz clock cycles in respon ⁇ e to the 4-bit code from ⁇ igma-delta modulator 94.
  • the following example ⁇ will ⁇ erve to illu ⁇ trate.
  • a ⁇ ume sigma-delta modulator 94 is clocked by a 3.072 mHz clock. For every 3.072 mHz clock, there are eight 24.576 mHz clocks applied to circuit 179.
  • circuit 179 suppres ⁇ e ⁇ a number of 24.576 mHz clock ⁇ as a function of the 4-bit code output by sigma-delta modulator 94. For example, if the external frequency source on line 136 is 32 kHz, then sigma-delta modulator 94 outputs, on average, a 0 code. The 0 code direct ⁇ circuit 179 to allow four out of every eight 24.576 mHz clock ⁇ to pa ⁇ through. Stated another way, circuit 179 ⁇ uppre ⁇ e ⁇ four out of every eight 24.576 mHz clock ⁇ in re ⁇ pon ⁇ e to a 0 code.
  • sigma-delta modulator 94 outputs, on average, an equal number of -3 and -4 code ⁇ .
  • the -3 code direct ⁇ circuit 179 to allow one out of every eight 24.576 mHz clock ⁇ to pass through (i.e, circuit 179 ⁇ uppre ⁇ e ⁇ ⁇ even out of every eight 24.576 mHz clock ⁇ in re ⁇ ponse to a -3 code) .
  • the -4 code directs circuit 179 to allow no 24.576 mHz clocks to pass through (i.e., circuit 179 suppres ⁇ es eight out of every eight 24.576 mHz clocks in response to a -4 code). On average, therefore, one out of every sixteen 24.576 mHz clocks will pa ⁇ s through suppres ⁇ or circuit 178 in re ⁇ pon ⁇ e to an average of -3 and -4 codes.
  • phase locked loop 122 including randomizer/suppressor circuit 179, divider 184, and divider 188 operate in the same manner as discussed in connection with phase locked loop 120.
  • the signal on line 182 is approximately 12.288 mHz. When decimated by ninety-six and then four, the ⁇ ignal on line 168 is 23 kHz. If the external clock on line 136 is 4 kHz, then the signal on line 182 is approximately 1.536 mHz. When decimated by ninety-six and then four, the ⁇ ignal on line 168 is 4 kHz.
  • Circuit 176 sigma-delta modulator 94, and clock randomizer/suppre ⁇ or circuit 179 together form a digitally-controlled oscillator.
  • phase locked loops allow the digital-to-digital converter to accept digital data at any data rate within the working range of the system, and lock to an externally supplied clock source that allows conver ⁇ ion of the incoming digital data to a data rate that is not neces ⁇ arily the ⁇ ame as or even an integer or rational relationship with the master clock controlling the digital-to-digital converter.
  • the embodiment ⁇ of the invention illu ⁇ trated in FIGS. 2-3 and 5-5A may be characterized as using a combination of fixed interpolation followed by variable decimation and then variable interpolation followed by fixed decimation. That is, with reference to FIG. 2, the digital data stream on line 12 is interpolated by a fixed ratio to increase the sample rate. Thi ⁇ higher ⁇ ample rate digital signal is then variably decimated under control of sigma-delta modulator 20 to provide the digital data stream on line 14 at another ⁇ ample rate. Thereafter, the digital data ⁇ tream on line 28 (which has the same data rate as the digital data stream on line 14) is variably interpolated under control of sigma-delta modulator 32 to variably increase the sample rate.
  • This higher sample rate digital signal i ⁇ then decimated by a fixed ratio to provide the digital data ⁇ tream on line 42 at another ⁇ ample rate.
  • the ⁇ ample rates of the digital data ⁇ tream on line ⁇ 14 and 28 are at a common ⁇ ample rate.
  • the common sample rate i 3.072 mHz.
  • FIG. 8 illustrates the method of fixed interpolation followed by variable decimation and then variable interpolation followed by fixed decimation.
  • the method begins in ⁇ tep 200 in which the input digital data having a first data rate is received. From step 200, the method proceeds to ⁇ tep 202 in which the input digital data i ⁇ interpolated by a fixed ratio to increase the sample rate of the digital data to provide an over ⁇ ampled digital data ⁇ tream. From ⁇ tep 202, the method proceed ⁇ to ⁇ tep 204 in which a fir ⁇ t sampling frequency select signal representative of the sample rate of the digital data received in ⁇ tep 200 i ⁇ received. From ⁇ tep 204, the method proceed ⁇ to ⁇ tep 206 in which the first sampling frequency select signal is sigma-delta modulated.
  • the method proceeds to ⁇ tep 208 in which the interpolated digital data i ⁇ decimated under control of the sigma-delta modulated frequency select signal by a ratio determined by the sigma-delta modulated fir ⁇ t sampling frequency select signal. From step 208, the method proceeds to step 210 in which a ⁇ econd ⁇ ampling frequency ⁇ elect ⁇ ignal representative of the desired output sample rate is received. From ⁇ tep 210, the method proceed ⁇ to ⁇ tep 212 in which the ⁇ econd ⁇ ampling frequency ⁇ elect signal is ⁇ igma-delta modulated.
  • step 214 the digital data i ⁇ interpolated by a ratio determined by the ⁇ igma-delta modulated ⁇ econd ⁇ ampling frequency ⁇ elect ⁇ ignal to increase the sample rate of the digital data.
  • step 216 the interpolated digital data is decimated to provide the output digital data at the desired sample rate.
  • step 218 the digital signal is output.
  • FIG. 9 is a block diagram broadly illustrating a second embodiment of the invention.
  • the overall purpo ⁇ e of circuit 250 i ⁇ to receive a digital data ⁇ tream on line 12 at any data rate within a predetermined working range of the ⁇ y ⁇ tem and to convert the digital data to a digital data stream on line 42.
  • the data rate of the digital data stream on line 42 can be the same as, higher, or lower than the data rate of the digital data stream on line 12.
  • circuit 250 operates in the ⁇ ame manner a ⁇ the fir ⁇ t embodiment of the invention.
  • the digital data on line 12 is interpolated by interpolator 252 under control of clock randomizer/suppres ⁇ or circuit 178 which is in turn controlled by sigma-delta modulator 20 to produce a higher sample rate digital signal on line 17.
  • Interpolator 252 increases the sample rate of the digital data stream (that is, converts the digital data stream into a higher sample rate digital data stream) on line 17 by using a sample and hold technique that repeats the digital sample for a specified number of clock cycles in a manner well— nown to those skilled in the art.
  • a sample and hold technique that repeats the digital sample for a specified number of clock cycles in a manner well— nown to those skilled in the art.
  • interpolator 252 i ⁇ to increa ⁇ e the ⁇ ample rate of the digital data ⁇ tream on line 12 to create a ⁇ o-called over ⁇ ampled ⁇ ignal.
  • the interpolation ratio (i.e., the ratio by which the ⁇ ample rate of the digital data on line 12 i ⁇ increased by interpolator 252 is controlled by clock rando izer/suppre ⁇ or circuit 178 which i ⁇ in turn controlled by ⁇ igma-delta modulator 20.
  • filter 18 and decimation block 254 have been illu ⁇ trated a ⁇ ⁇ eparate circuit elements for illustrative purpo ⁇ e ⁇ , one ⁇ killed in the art will appreciate that the ⁇ e functions may be performed by a single computation element, such as an FIR or IIR filter in a well known manner.
  • Sigma-delta modulator 20 operate ⁇ in the ⁇ ame manner a ⁇ de ⁇ cribed in connection with the embodiment of FIGS. 2-3.
  • Circuit 178 operate ⁇ in the ⁇ ame manner a ⁇ already de ⁇ cribed in connection with FIGS. 6 and 7. The following explanation is provided for additional clarification.
  • Circuit 178 provides a clock on line 258 by ⁇ uppre ⁇ ing a certain number of clock ⁇ from clock 262 in re ⁇ pon ⁇ e to the m-bit code on line 260 from sigma-delta modulator 20. If, however, clocks in the same temporal positions are suppre ⁇ ed for each multi-bit code from sigma-delta modulator 20, then unwanted tones may appear in the output data stream on line 258. Therefore, circuit 178 al ⁇ o perform ⁇ the additional function of randomly ⁇ uppressing clock cycle ⁇ in order to prevent unwanted tone ⁇ in the output data ⁇ tream on line 258. A ⁇ de ⁇ cribed previou ⁇ ly, clock ⁇ uppre ⁇ sor and randomizer circuits are well known in the art.
  • Clock randomizer/suppressor circuit 178 is needed in the second embodiment to produce a clock on line 258 having a clock frequency that is 384 times the data rate specified by sampling frequency selection signal 24 since ⁇ igma-delta modulator 20 i ⁇ clocked u ⁇ ing a fixed clock frequency and a variable clock frequency i ⁇ needed to variably interpolate the data on line 12.
  • Clock randomizer/suppres ⁇ or circuit 178 output ⁇ a clock signal on line 258 that controls the interpolation of interpolator 252.
  • the digital data at the predetermined data rate on line 14 is optionally filtered by a filter 11 a ⁇ de ⁇ cribed in connection with the fir ⁇ t embodiment of the invention.
  • the filtered digital data stream on line 28 is ⁇ ent to interpolator 270.
  • Interpolator 270 increa ⁇ es the sample rate of the digital data stream (that i ⁇ , convert ⁇ the digital data ⁇ tream into a higher ⁇ ample rate digital data ⁇ tream) on line 28 by, for example, in ⁇ erting zeros between data samples, in a manner well-known to those skilled in the art.
  • sample and hold techniques may be used for increasing the sample rate of the data stream on line 28, such as sample and hold techniques.
  • a higher ⁇ ample rate digital data stream on line 34 is then ⁇ ent to a digital filter 36 which remove ⁇ any image ⁇ of the original digital ⁇ ignal a ⁇ a result of the interpolation proces ⁇ .
  • the filtered digital data ⁇ tream on line 38 is then sent to a decimation block 272 that decimates the digital data stream on line 38 under control of clock randomizer/suppre ⁇ or circuit 179 which is in turn controlled by the ⁇ igma-delta modulator 32 a ⁇ will be explained in more detail hereinafter.
  • filter 36 and decimation block 272 have been illu ⁇ trated as separate circuit elements for illustrative purposes, one skilled in the art will appreciate that these functions may be performed by a ⁇ ingle computational element, such as an FIR or IIR filter in a well-known manner.
  • Sigma-delta modulator 20 operates in the same manner as de ⁇ cribed in connection with the embodiment of FIGS. 2-3.
  • Circuit 179 operate ⁇ in the same manner as circuit 178. The following explanation is provided for additional clarification.
  • Circuit 179 provide ⁇ a clock on line 268 by ⁇ uppre ⁇ ing a certain number of cycle ⁇ of clock ⁇ from clock 262 in re ⁇ pon ⁇ e to the m-bit code on line 264 from sigma-delta modulator 32. If, however, the same clocks in the ⁇ ame temporal po ⁇ itions are suppres ⁇ ed for each multi-bit code from ⁇ igma-delta modulator 32, then unwanted tones may appear in the output data stream on line 268. Therefore, circuit 179 also performs the additional function of randomly suppre ⁇ ing clock cycle ⁇ in order to prevent unwanted tone ⁇ in the output data ⁇ tream on line 268.
  • Clock ⁇ uppressor/randomizer circuit 179 is needed in the second embodiment to produce a clock on line 268 having a clock frequency that is 384 times the data rate specified by ⁇ ampling frequency selection number 44 since sigma-delta modulator 32 i ⁇ clocked u ⁇ ing a fixed clock frequency and a variable clock frequency i ⁇ needed to variably decimate the data on line 38.
  • Clock randomizer/ ⁇ uppressor circuit 179 output ⁇ a clock ⁇ ignal on line 268 that controls the decimation of decimator 272 to provide the digital data stream on line 42 having a sample rate (Fs2) selected by sampling frequency select signal 44.
  • FIG. 10 illustrate ⁇ a more detailed embodiment 300 of the circuit illu ⁇ trated in FIG. 9.
  • the purpose and operation of circuit 300 is analogous to the first embodiment of the invention illustrated in FIGS. 2-3.
  • the filtered higher sample rate digital data on line 304 is then sent to interpolator 306 that increases the sample rate by a variable ratio so that the digital data on line 308, after filtering by filter 310 and decimation by a fixed ratio of eight in decimator 314, emerges on line 64 with a sample rate of 3.072 mHz.
  • Filter 310 may be an FIR or IIR filter.
  • the functions of decimator 314 and filter 74 may be combined into a single element as noted previously.
  • Sigma-delta modulator 66 produces a four-bit code representative of frequency selection number 72 at a constant rate of 3.072 mHz in respon ⁇ e to clock 70.
  • interpolator 306 mu ⁇ t produce the digital data ⁇ tream on line 308 having a ⁇ ample rate of 24.576 mHz ⁇ o that, when decimated by a factor of eight by decimator 314, the data emerge ⁇ on line 64 with a sample rate of 3.072 mHz. Therefore, clock randomizer/ ⁇ uppressor circuit 178 i ⁇ needed to produce a variable rate clock on line 316 to variably interpolate the data on line 304.
  • Table 1 illu ⁇ trate ⁇ the relationship among the four-bit codes that are produced by ⁇ igma-delta modulator 66, the number of clock ⁇ that are allowed to pa ⁇ through randomizer/ ⁇ uppre ⁇ or circuit 178 and the output ⁇ ample rate that the four-bit code corre ⁇ ponds to when modulator 66 is clocked u ⁇ ing a 3.072 mHz clock and when clock randomizer/ ⁇ uppre ⁇ or circuit 178 and interpolator 306 are clocked u ⁇ ing a 24.576 mHz clock.
  • Some example ⁇ will illu ⁇ trate the operation of the ⁇ econd embodiment.
  • the +2 code is processed by clock randomizer/suppre ⁇ sor circuit 178 to allow six out of every eight 24.576 mHz clock cycles from clock 262 to pas ⁇ through to generate a clock having an average frequency of 18.432 mHz.
  • Interpolator 306 deliver ⁇ data on line 308 at a rate of 24.576 mHz. Data arrive ⁇ at the interpolator 306 on line 304 at 18.432 mHz in thi ⁇ example. Each time the 18.432 mHz clock on line 316 i ⁇ active, a new data point ha ⁇ arrived at the interpolator input on line 304.
  • Interpolator 306 in ⁇ ert ⁇ thi ⁇ data point into the outgoing data ⁇ tream on line 308 ⁇ o that the 18.432 mHz data i ⁇ delivered at 24.576 mHz on line 308. Interpolator 306 perform ⁇ thi ⁇ function by ⁇ ample and holding each 18.432 mHz data point every 24.576 mHz clock until the next 18.432 mHz data point arrive ⁇ . Alternatively, Interpolator 306 may in ⁇ ert zero ⁇ between each data point at 18.432 mHz to deliver the data at 24.576 mHz.
  • interpolator 306 increa ⁇ es the sample rate of the digital data ⁇ tream on line 304 from 18.432 mHz to 24.576 mHz on line 308.
  • filter 310 Upon filtering by filter 310 and decimation by decimator 314, the digital data emerges on line 64 with a ⁇ ample rate of, on average, 3.072 mHz.
  • a ⁇ ume that the digital data ⁇ tream on line 50 has a data rate of 4 kHz.
  • Interpolator 52 increases this data rate to 16 kHz.
  • Interpolator 58 increases the 16 kHz data rate to 1.536 mHz.
  • the digital data stream on line 64 have a data rate of 3.072 mHz, the digital data stream on line 60 at 1.536 mHz must be effectively interpolated by a factor of sixteen so that the data rate of the digital data ⁇ tream on line 308 ha ⁇ a data rate of 24.576 mHz.
  • the twenty-bit frequency ⁇ election number 72 i ⁇ cho ⁇ en ⁇ uch that ⁇ igma-delta modulator 66 produce ⁇ , on average, an equal number of -3 and -4 code ⁇ although other four-bit code ⁇ will be produced, but with a lower frequency of occurrence. That is, occasionally, -2, -1, and even le ⁇ frequently, +1, +2 codes will be produced.
  • the -3 code directs circuit 178 to allow one out of every eight 24.576 mHz clocks to pas ⁇ through (i.e. circuit 178 suppresses seven out of every eight 24.576 mHz clocks in re ⁇ pon ⁇ e to a -3 code) .
  • the -4 code direct ⁇ circuit 178 to allow no 24.576 mHz clock ⁇ to pa ⁇ through (i.e. circuit 178 ⁇ uppre ⁇ e ⁇ eight out of every eight 24.576 mHz clock ⁇ in re ⁇ ponse to a -4 code). On average, therefore, one out of every sixteen 24.576 mHz clocks will pa ⁇ through ⁇ uppre ⁇ or circuit 178 in re ⁇ pon ⁇ e to an average of -3 and -4 code ⁇ .
  • interpolator 306 respond ⁇ to the clock on line 316 to increa ⁇ e the ⁇ ampling frequency of the 1.536 mHz data on line 304 to 24.576 mHz on line 308.
  • N may be any number of bit ⁇ and i ⁇ typically cho ⁇ en to be the wide ⁇ t bit ⁇ tream commen ⁇ urate with the signal-to-noise ratio requirements of the particular application.
  • the ⁇ ample rate converted digital data ⁇ tream on line 64 optionally is sent to filter 74 which operates as described in connection with FIG. 3.
  • the filtered digital data stream having a data rate of 3.072 mHz on line 86 is then fed into circuit part 303 of circuit 300.
  • the filtered digital data ⁇ tream on line 86 is then sent to interpolator 320.
  • Interpolator 320 increases the sample rate of the digital data stream on line 86 by a factor of eight u ⁇ ing, for example, a zero fill technique that in ⁇ ert ⁇ zero ⁇ between the digital ⁇ ample ⁇ .
  • the parameters of filter 324 can be adjusted to compensate for any loss of gain.
  • a higher sample rate signal on line 322 output by interpolator 320 (now at 24.576 mHz) i ⁇ then fed into digital filter 324.
  • sample and hold technique ⁇ may be u ⁇ ed to increase the sampling rate in place of interpolator 320.
  • the filtered higher ⁇ ample rate digital data on line 326 i ⁇ then sent to decimator 328 that decrease ⁇ the sample rate by a variable ratio so that the digital data on line 114, after filtering by filter 98 and decimation by a fixed ratio of ninety-six in decimator 104 and a fixed ratio of four in decimator 112, emerges on line 114 with a sample rate specified by frequency selection number 116.
  • Filter 98 is a ⁇ inc 93 3 -type filter but could be any type of FIR or IIR filter.
  • filter 98 and decimator 328 could be combined into a ⁇ ingle element a ⁇ noted previou ⁇ ly.
  • Sigma-delta modulator 94 produce ⁇ a four-bit code repre ⁇ entative of frequency ⁇ election number 116 at a con ⁇ tant rate of 3.072 mHz in re ⁇ pon ⁇ e to clock 70.
  • decimator 328 mu ⁇ t produce the digital data ⁇ tream on line 96 having ⁇ ample rate ⁇ of, for example, between 1.536 mHz and 24.576 mHz depending upon the desired sample rate of the output data stream. Therefore, clock randomizer/suppres ⁇ or circuit 179 is needed to produce a variable rate clock on line 318 to variable decimate the data on line 326.
  • Table 2 illustrates the relationship among the four-bit code ⁇ that are produced by sigma-delta modulator 94, the number of clock ⁇ that are allowed to pa ⁇ through randomizer/suppressor circuit 179, and the output sample rate that the four-bit code corresponds to when modulator 94 is clocked using a 3.072 mHz clock and when clock randomizer/ ⁇ uppressor circuit 179 is clocked using a 24.576 mHz clock.
  • the ⁇ ample rate of the digital data ⁇ tream on line 86 i ⁇ an over ⁇ ampled data ⁇ tream having a con ⁇ tant ⁇ ample rate of 3.072 mHz.
  • Interpolator 320 increases the data rate of the digital data stream on line 86 by a factor of eight to 24.576 mHz.
  • the digital data stream on line 102 must have a sample rate of 192 kHz and the digital data stream on line 110 must have a sample rate 18.432 mHz.
  • twenty-bit frequency selection number 116 is selected. such that upon ⁇ igma-delta modulation by the fourth order four-bit ⁇ igma-delta modulator 94, the four bit code ⁇ generated will be, on average, a +2 code although other four bit code ⁇ will be produced but with a lower frequency of occurrence.
  • the +2 code is then applied to clock randomizer/suppressor circuit 179. For every 3.072 mHz clock applied to sigma-delta modulator 94, there are eight 24.576 mHz clocks applied to clock randomizer/suppressor circuit 179. In accordance with Table 2, circuit 179 suppresses a number of 24.576 mHz clocks as a function of the four-bit code output by sigma-delta modulator 94.
  • circuit 179 ⁇ uppre ⁇ se ⁇ two out of every eight 24.576 mHz clock ⁇ in response to a +2 code. As discussed previously, circuit 179 randomly suppresses the specified number of clock cycles in order to prevent unwanted tones in the output data stream on line 318.
  • the de ⁇ ired sample rate of the digital data stream on line 114 is 4 kHz.
  • Interpolator 320 increase ⁇ the data rate of the digital data stream on line 86 by a factor of eight to 24.576 mHz.
  • the digital data ⁇ tream on line 102 mu ⁇ t have a sample rate of 16 kHz and the digital data stream on line 110 must have a sample rate of 1.536 ml- Therefore, twenty-bit frequency selection number 116 is selected such that ⁇ igma-delta modulator 94 produces, on average, an equal number of -3 and -4 codes although other four-bit codes will be produced, but with a lower frequency of occurrence.
  • the -3 code directs circuit 179 to allow one out of every eight 24.576 mHz clock ⁇ to pa ⁇ through (i.e., circuit 179 ⁇ uppre ⁇ ses seven out of every eight 24.576 mHz clock ⁇ in re ⁇ pon ⁇ e to a -3 code).
  • the -4 code direct ⁇ circuit 179 to allow no 24.576 mHz clocks to pa ⁇ s through (i.e., circuit 179 suppre ⁇ es eight out of every eight 24.576 mHz clocks in respon ⁇ e to a -4 code). On average, therefore, one out of every ⁇ ixteen 24.576 mHz clock ⁇ will pa ⁇ s through suppressor circuit 179 in response to an average of -3 and -4 codes.
  • digital data ⁇ treams are indicated as being N-bits wide.
  • N may be any number of bit ⁇ and i ⁇ typically cho ⁇ en to be the widest bit stream commensurate with the signal-to-noise ratio requirements of the particular application.
  • FIGS. 9-10 may be characterized as using a combination of variable interpolation followed by fixed decimation and then fixed interpolation followed by variable decimation. That is, with reference to FIG. 9, the digital data stream on line 12 is interpolated under control of ⁇ igma-delta modulator 20 to provide the digital data ⁇ tream on line 17 at a higher ⁇ ample rate. Thi ⁇ higher ⁇ ample rate digital data ⁇ tream i ⁇ then decimated by a fixed ratio to provide the digital data stream on line 14 at another sample rate. Thereafter, the digital data stream on line 28 (which has the ⁇ ame data rate as the digital data stream on line 14) is interpolated by a fixed ratio to increa ⁇ e the sample rate.
  • the sample rates of the digital data stream on lines 14 and 28 are at a common sample rate.
  • the common sample rate is 3.072 mHz.
  • FIG. 11 is a flow chart illustrating a second embodiment of a method of the present invention.
  • FIG. 11 illu ⁇ trate ⁇ the method of variable interpolation followed by fixed decimation and then fixed interpolation followed by variable decimation.
  • the method begin ⁇ in step 340 in which the input digital data having a first data rate i ⁇ received. From step 340, the method proceeds to ⁇ tep 342 in which a first sampling frequency select ⁇ ignal representative of the sample rate of the digital data received in step 340 i ⁇ received.
  • the method proceeds to ⁇ tep 344 in which the fir ⁇ t ⁇ ampling frequency ⁇ elect ⁇ ignal i ⁇ ⁇ igma-delta modulated. From ⁇ tep 344, the method proceeds to ⁇ tep 346 in which the digital data i ⁇ interpolated by a ratio determined by the ⁇ igma-delta modulated first sampling frequency select signal to increa ⁇ e the sample rate of the digital data. From step 346, the method proceeds to step 348 in which the interpolated digital data is decimated by a fixed ratio.
  • step 350 in which the decimated digital data from step 348 is interpolated by a fixed ratio to increase the ⁇ ample rate of the digital data to provide an oversampled digital data stream.
  • the method proceed ⁇ to ⁇ tep 352 in which a ⁇ econd ⁇ ampling frequency select signal representative of the desired output sample rate is received.
  • the method proceeds to ⁇ tep 354 in which the second sampling frequency select signal is ⁇ igma-delta modulated.
  • step 356 the interpolated digital data is decimated under control of the sigma-delta modulated frequency select signal by a ratio determined by the ⁇ igma-delta modulated ⁇ econd sampling frequency select ⁇ ignal to provide the output digital data at the de ⁇ ired sample rate.
  • step 356 the method proceed ⁇ to ⁇ tep 358 in which the digital signal is output.
  • FIG. 12 figure illu ⁇ trate ⁇ a third embodiment 370 of the pre ⁇ ent invention.
  • FIG. 12 modifies the circuit of FIG. 10 by eliminating the clock randomizer/suppre ⁇ or circuit.
  • the components and operation of the circuit of FIG. 12 are the ⁇ ame as those illustrated in FIG. 10.
  • the circuit of FIG. 12 operate ⁇ in accordance with the method illu ⁇ trated in FIG. 11.
  • ⁇ igma-delta modulator 94 produce ⁇ a four-bit code that directly controls the decimation ratio provided by decimation block 328 and sigma-delta modulator 66 produces a four-bit code that directly control ⁇ the interpolation ratio provided by interpolator 306.
  • Table 3 illu ⁇ trate ⁇ the relation ⁇ hip among the four-bit codes that are produced by sigma-delta modulator 66 or 94, the intervals at which decimator 328 produces an output or the ratio by which the sample rate on line 304 is increa ⁇ ed, and the ⁇ ampling frequency that the four-bit code correspond ⁇ to when modulator 66 or 94 i ⁇ clocked u ⁇ ing a 3.072 mHz clock.
  • a -4 code control ⁇ decimator 328 to produce one output for every sample on line 326 and a +3 code controls decimator 328 to produce one output every eight samples on line 326.
  • a -4 code controls interpolator 306 to maintain the same sample rate a ⁇ on line 304 and a +3 code control ⁇ interpolator 306 to increa ⁇ e the ⁇ ample rate on line 304 by a factor of eight.
  • FIG. 13 graphically illustrate ⁇ the 1/n relation ⁇ hip between the four-bit code ⁇ and the corre ⁇ ponding ⁇ ampling frequency.
  • the ⁇ y ⁇ tem i ⁇ nonlinear in the sense of mapping the four-bit codes to a corresponding sampling frequency only because of the particular interpolation ratios, decimation ratios, and data rates chosen.
  • the sy ⁇ tem it ⁇ elf i ⁇ linear and, by providing an operation that corrects for the nonlinear mapping of the four-bit codes to the corresponding sampling frequency, a linearly mapped sy ⁇ tem a ⁇ in the first two embodiments previously de ⁇ cribed can be provided.
  • the interpolation ratio ⁇ , decimation ratio ⁇ , and data rate ⁇ may be ⁇ elected ⁇ o that there i ⁇ a linear relationship between four-bit code ⁇ and corresponding sampling frequencies.
  • the 1/n relationship between four-bit codes and ⁇ ampling frequency illu ⁇ trated in FIG. 13 and Table 2 is meant to be exemplary only; other relationships are possible (for all embodiments of the invention) and are to be con ⁇ idered within the ⁇ cope of the pre ⁇ ent invention.
  • the circuit illu ⁇ trated in FIG. 12 can generate ⁇ ampling frequencie ⁇ within the 0 to 64 kHz range by varying the ratio of four-bit code ⁇ in the same manner as discu ⁇ ed in conjunction with the first two embodiments.
  • the embodiment illustrated in FIG. 12 can al ⁇ o be u ⁇ ed with the circuit ⁇ illu ⁇ trated in FIGS. 14 and 15 in the ⁇ ame manner.
  • the clock randomizer/suppres ⁇ or circuit reproce ⁇ e ⁇ the ⁇ igma-delta modulated clock ⁇ ignal generated by the ⁇ igma-delta modulator and ⁇ uppre ⁇ e ⁇ clock ⁇ ignal ⁇ in a linear manner. This may degrade the noise shaping provided by the sigma-delta modulator.
  • the circuit illu ⁇ trated in FIG. 12 is advantageous in that the clock randomizer/suppre ⁇ or circuit i ⁇ eliminated thereby avoiding degradation in the ⁇ ignal to noi ⁇ e ratio.
  • FIG. 14 illu ⁇ trate ⁇ another embodiment 251 of the invention in which digital pha ⁇ e locked loop ⁇ 120 and 122 are incorporated into the circuits of FIGS. 9 or 10.
  • the phase locked loops operate a ⁇ previously described in connection with the discussion of FIG. 5.
  • FIG. 15 illustrates another embodiment 253 of the invention in which a single phase locked loop i ⁇ u ⁇ ed in the ⁇ econd embodiment of the invention.
  • the pha ⁇ e locked loop operate ⁇ in the manner de ⁇ cribed in connection with FIG. 5A.
  • Pha ⁇ e locked loops can be used in all embodiments of the invention.
  • FIG. 16 illustrate ⁇ another embodiment of the invention in which a number of digital ⁇ ignal ⁇ that may have different data rate ⁇ can be combined into a combined or mixed -digital signal having a data rate that is not neces ⁇ arily and an integer multiple of any of the data rate ⁇ of the incoming digital data ⁇ tream ⁇ .
  • circuit 380 a number of digital data streams are supplied to a multiple number of circuit parts 13, 51, 146, 274 or 301. These circuit parts operate as already previou ⁇ ly de ⁇ cribed. A ⁇ long a ⁇ each circuit part i ⁇ clocked u ⁇ ing the ⁇ ame clock frequency, the digital data ⁇ tream on line ⁇ 388, 390, . . .
  • FIG. 17 illustrates, in circuit 400 an apparatus for suppling digital signal ⁇ that may have different data rates from a digital data stream having a single data rate where the data rate of the digital data ⁇ tream ⁇ to be output doe ⁇ not need to be an integer multiple of the common digital data rate.
  • a digital data ⁇ tream on line 402 having a common data rate is supplied to a multiple number of circuit parts 15, 90, 276, or 303.
  • Each of the ⁇ e circuit parts takes the common data rate and can convert the digital data to digital data streams 404, 406, . . . 408 that may have different data rates.
  • Any combination of circuit parts 15, 90, 276 or 303 can be used in the circuit of FIG. 17.
  • FIG. 18 illustrates the method of digitally mixing or combining digital signals having differing data rates in accordance with the present invention.
  • the method begins in step 420 in which digital data at a first data rate is received. From ⁇ tep 420, the method proceed ⁇ to ⁇ tep 422 in which the digital data at the first data rate is converted to digital data at a second data rate in respon ⁇ e to a fir ⁇ t ⁇ igma-delta modulated control signal to provide a first digital data ⁇ tream at the ⁇ econd data rate. From step 422, the method proceeds to step 424 in which digital data at a third data rate i ⁇ received.
  • step 426 in which the digital data at the third data rate in converted to digital data at the second data rate in response to a second sigma-delta modulated control ⁇ ignal to provide a ⁇ econd digital data stream at the second data rate. From step 426, the method proceed ⁇ to ⁇ tep 428 in which the fir ⁇ t and second digital data stream ⁇ are combined
  • FIG. 19 illu ⁇ trate ⁇ the method of the invention for digitally providing different digital data ⁇ tream ⁇ from a single digital data stream.
  • the method begin ⁇ in ⁇ tep 440 in which digital data at a fir ⁇ t data rate i ⁇ received. From ⁇ tep 440, the method proceeds to step 442 in which the digital data at the first data rate is converted to digital data at a second data rate in response to a first sigma-delta modulated control signal. From step 442, the method proceeds to step 444 in which the digital data at the first data rate is converted to digital data at a third data rate in re ⁇ pon ⁇ e to a second sigma-delta modulated control signal.
  • step 444 the method proceeds to ⁇ tep 446 in which the digital data at the ⁇ econd data rate i ⁇ output. From ⁇ tep 446, the method proceeds to ⁇ tep 448 in which the digital data at the third data rate i ⁇ output.
  • converting ⁇ tep ⁇ 422, 426, 442, and 444 can be performed a ⁇ specifically illustrated by the methods illu ⁇ trated in FIGS. 8 and 11.
  • the present invention converts an incoming digital data stream to a common data rate by interpolating to create an oversampled ⁇ ignal and then variably decimating the over ⁇ ampled ⁇ ignal to provide a digital data ⁇ tream at the common data rate.
  • the common data rate digital data ⁇ tream i ⁇ then variably interpolated to create an over ⁇ ampled signal and then decimated by a fixed decimation ratio to provide a digital data stream at the output having a de ⁇ ired ⁇ ample rate.
  • the present invention converts an incoming digital data stream to a common data rate by variably interpolating the incoming digital data stream to provide an oversampled signal and then decimating the oversampled signal by a fixed decimation ratio to provide a digital data stream at the common data rate.
  • the common data rate digital data ⁇ tream i ⁇ then interpolated by a fixed ratio to provide an over ⁇ ampled ⁇ ignal and then variably decimated to provide a digital data ⁇ tream at the output having a desired ⁇ ample rate.
  • the present invention can thus convert incoming digital data at any data rate within the working range of the system to an output digital data stream at any arbitrary data rate within the working range of the sy ⁇ tem.
  • the present invention may also be used to convert an incoming digital signal to a digital signal having the common data rate.
  • an incoming digital signal on line 12 can be converted to a digital ⁇ ignal having a common data rate on line 28.
  • Thi ⁇ common rate digital on line 28 can be output a ⁇ an output signal to be used by other devices that require digital data at the common data rate.
  • This a ⁇ pect of the pre ⁇ ent invention i ⁇ advantageou ⁇ because it allows digital data stream ⁇ having differing data rate ⁇ to be converted to a digital data ⁇ tream having a common data rate.
  • Thi ⁇ ⁇ ame kind of conver ⁇ ion is also provided by all embodiments of the invention.
  • the present invention provides an advantageous apparatus and method for digitally mixing or combining signal ⁇ that may have different ⁇ ample rate.
  • the digital ⁇ ignal ⁇ to be combined are provided by analog to digital converter ⁇ and reconverted to analog signal ⁇ by a digital to analog converter a ⁇ in the co-pending application ⁇ incorporated herein by reference, the pre ⁇ ent invention provide ⁇ an advantageou ⁇ apparatu ⁇ and method for mixing or combining analog ⁇ ignal ⁇ ource ⁇ .
  • the pre ⁇ ent invention can convert a digital data stream at the common data rate to a digital data stream at any data rate within the working range of the system.
  • a digital data stream on line 28 can be converted to a digital data stream at any data rate and output on line 42.
  • Thi ⁇ a ⁇ pect of the pre ⁇ ent invention i ⁇ advantageou ⁇ becau ⁇ e it allow ⁇ the digital data stream on line 28 at the common data rate to be converted to a digital data stream at any other data rate, thu ⁇ allowing the invention to provide an interface between a common data rate and data rate ⁇ that may be required by other digital ⁇ ystem ⁇ . This same kind of conversion is also provided by all embodiments of the invention.
  • the present invention provides an advantageous apparatus and method for providing a number of analog signal sources from digital signal ⁇ that may have different ⁇ ample rate ⁇ .
  • the present invention advantageously converts an incoming digital data stream at any data rate within the working range of the system to an outgoing digital data stream at any data rate within the working range of the system.
  • the data rates of the incoming digital data stream, the outgoing digital data stream, the common data rate, and the clock rate of the system clock do not need to be related by any integer or rational relationship.
  • the digital-to-digital converter does not have to be capable of interpolating the digital data up to the lowest common frequency between the incoming or outgoing digital data rate and the modulator clock frequency.
  • Thi ⁇ i ⁇ due to the sigma-delta modulation of the sampling intervals.
  • the sampling interval doe ⁇ not have to corre ⁇ pond exactly to a fixed relationship between the incoming or outgoing digital data rate and the modulator clock. Since the incoming, outgoing, and common sample rates are sigma-delta encoded in the present invention, the sample rates, on average, will repre ⁇ ent the de ⁇ ired sample rates with the noise or jitter on the sampling points being pushed into the higher frequency range ⁇ .
  • the present invention thus take ⁇ advantage of ⁇ igma-delta encoding of the time ba ⁇ e to avoid the need for interpolation to very high frequencies, which in the prior art, typically were in the gigahertz range.
  • An additional benefit of this process is that when the pre ⁇ ent invention is incorporated into an integrated circuit, a significant saving ⁇ in chip area can be realized by the u ⁇ e of lower interpolation ratio ⁇ .
  • Another important advantage of the pre ⁇ ent invention i ⁇ that the ⁇ igma-delta modulator ⁇ u ⁇ ed to control decimation and interpolation can be clocked u ⁇ ing a fixed clock frequency, allowing optimization of the modulator operation at the fixed clock frequency.
  • Interpolators and decimators u ⁇ eful in the pre ⁇ ent invention may be constructed as ⁇ hown in Introduction to Digital Signal Proce ⁇ ing by John Proakis and Dimitris Manolaki ⁇ , published by Macmillan Publishing Company, ⁇ 1988.

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)
EP95915415A 1994-05-11 1995-03-23 Digital-to-digital conversion using nonuniform sample rates Withdrawn EP0759233A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US241059 1988-09-06
US08/241,059 US5497152A (en) 1993-09-13 1994-05-11 Digital-to-digital conversion using non-uniform sample rates
PCT/US1994/010268 WO1995008220A1 (en) 1993-09-13 1994-09-13 Analog to digital conversion using nonuniform sample rates
PCT/US1994/010269 WO1995008221A1 (en) 1993-09-13 1994-09-13 Digital to analog conversion using nonuniform sample rates
WOPCT/US94/10269 1994-09-13
WOPCT/US94/10268 1994-09-13
PCT/US1995/003739 WO1995031860A1 (en) 1993-09-13 1995-03-23 Digital-to-digital conversion using nonuniform sample rates

Publications (1)

Publication Number Publication Date
EP0759233A1 true EP0759233A1 (en) 1997-02-26

Family

ID=22909080

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95915415A Withdrawn EP0759233A1 (en) 1994-05-11 1995-03-23 Digital-to-digital conversion using nonuniform sample rates

Country Status (2)

Country Link
EP (1) EP0759233A1 (ja)
JP (1) JPH10511232A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109644004A (zh) * 2017-08-08 2019-04-16 深圳市汇顶科技股份有限公司 转换模块以及转换电路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6766339B2 (en) * 2001-01-11 2004-07-20 Asml Holding N.V. Method and system for efficient and accurate filtering and interpolation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9531860A1 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109644004A (zh) * 2017-08-08 2019-04-16 深圳市汇顶科技股份有限公司 转换模块以及转换电路
CN109644004B (zh) * 2017-08-08 2023-05-26 深圳市汇顶科技股份有限公司 转换模块以及转换电路

Also Published As

Publication number Publication date
JPH10511232A (ja) 1998-10-27

Similar Documents

Publication Publication Date Title
US5497152A (en) Digital-to-digital conversion using non-uniform sample rates
EP0719478B1 (en) Digital to analog conversion using nonuniform sample rates
US5892468A (en) Digital-to-digital conversion using nonuniform sample rates
US5712635A (en) Digital to analog conversion using nonuniform sample rates
US5963160A (en) Analog to digital conversion using nonuniform sample rates
US5485152A (en) Analog to digital conversion using non-uniform sample rates
US5625359A (en) Variable sample rate ADC
US6650258B1 (en) Sample rate converter with rational numerator or denominator
EP0686320A1 (en) Resampling synchronizer of digitally sampled signals
WO1996016482A9 (en) Variable sample rate adc
JPH07506714A (ja) 広周波数帯域信号をデジタル化する方法および装置
GB2271905A (en) Sampling rate conversion
US7259700B2 (en) Method and device for converting the sampling frequency of a digital signal
US5717618A (en) Method for digital interpolation
KR19980070433A (ko) 리샘플링 회로 및 그 제어방법
EP0450817B1 (en) Digital phase detector arrangements
EP0865158A2 (en) Sampling frequency conversion apparatus and fractional frequency dividing apparatus for sampling frequency conversion
JP4740144B2 (ja) 直接デジタル合成方式による周波数合成器
US5613084A (en) Interpolation filter selection circuit for sample rate conversion using phase quantization
WO1995031860A1 (en) Digital-to-digital conversion using nonuniform sample rates
EP0759233A1 (en) Digital-to-digital conversion using nonuniform sample rates
EP1115197B1 (en) Digital FM stereo demodulator and method
Babic POLYNOMIAL-BASED FILTERS IN SAMPLING RATE CONVERSION BY AN INTEGER FACTOR
JP2000507405A (ja) 複数のクロック信号を導出する方法及び装置
JPH10327222A (ja) Ｄｔｍｆ信号発生回路

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19961107

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19991001